Merge bk://drm.bkbits.net/drm-2.6

into ppc970.osdl.org:/home/torvalds/v2.6/linux

drivers/char/drm/r128_state.c

@@ -916,7 +916,7 @@ static int r128_cce_dispatch_write_span( drm_device_t *dev,
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
-		return -EMSGSIZE;
+		return DRM_ERR(EMSGSIZE);
 
 	if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
 		return DRM_ERR(EFAULT);
@@ -1012,7 +1012,7 @@ static int r128_cce_dispatch_write_pixels( drm_device_t *dev,
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
-		return -EMSGSIZE;
+		return DRM_ERR(EMSGSIZE);
 
 	xbuf_size = count * sizeof(*x);
 	ybuf_size = count * sizeof(*y);
@@ -1131,7 +1131,7 @@ static int r128_cce_dispatch_read_span( drm_device_t *dev,
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
-		return -EMSGSIZE;
+		return DRM_ERR(EMSGSIZE);
 
 	if ( DRM_COPY_FROM_USER( &x, depth->x, sizeof(x) ) ) {
 		return DRM_ERR(EFAULT);
@@ -1176,7 +1176,7 @@ static int r128_cce_dispatch_read_pixels( drm_device_t *dev,
 
 	count = depth->n;
 	if (count > 4096 || count <= 0)
-		return -EMSGSIZE;
+		return DRM_ERR(EMSGSIZE);
 
 	if ( count > dev_priv->depth_pitch ) {
 		count = dev_priv->depth_pitch;

drivers/char/drm/radeon.h

@@ -51,7 +51,7 @@
 #define DRIVER_DATE		"20020828"
 
 #define DRIVER_MAJOR		1
-#define DRIVER_MINOR		10
+#define DRIVER_MINOR		11
 #define DRIVER_PATCHLEVEL	0
 
 /* Interface history:
@@ -84,6 +84,8 @@
  * 1.10- Add SETPARAM ioctl; first parameter to set is FB_LOCATION, which
  *       clients use to tell the DRM where they think the framebuffer is 
  *       located in the card's address space
+ * 1.11- Add packet R200_EMIT_RB3D_BLENDCOLOR to support GL_EXT_blend_color
+ *       and GL_EXT_blend_[func|equation]_separate on r200
  */
 #define DRIVER_IOCTLS							     \
  [DRM_IOCTL_NR(DRM_IOCTL_DMA)]               = { radeon_cp_buffers,  1, 0 }, \

drivers/char/drm/radeon_drm.h

@@ -144,7 +144,8 @@
 #define RADEON_EMIT_PP_TEX_SIZE_0                   73
 #define RADEON_EMIT_PP_TEX_SIZE_1                   74
 #define RADEON_EMIT_PP_TEX_SIZE_2                   75
-#define RADEON_MAX_STATE_PACKETS                    76
+#define R200_EMIT_RB3D_BLENDCOLOR                   76
+#define RADEON_MAX_STATE_PACKETS                    77
 
 
 /* Commands understood by cmd_buffer ioctl.  More can be added but

drivers/char/drm/radeon_drv.h

@@ -690,6 +690,7 @@ extern void radeon_do_release(drm_device_t *dev);
 #define R200_SE_VTX_FMT_1                 0x208c
 #define R200_RE_CNTL                      0x1c50 
 
+#define R200_RB3D_BLENDCOLOR              0x3218
 
 /* Constants */
 #define RADEON_MAX_USEC_TIMEOUT		100000	/* 100 ms */

drivers/char/drm/radeon_mem.c

@@ -137,12 +137,12 @@ static int init_heap(struct mem_block **heap, int start, int size)
 	struct mem_block *blocks = DRM_MALLOC(sizeof(*blocks));
 
 	if (!blocks) 
-		return -ENOMEM;
+		return DRM_ERR(ENOMEM);
 	
 	*heap = DRM_MALLOC(sizeof(**heap));
 	if (!*heap) {
 		DRM_FREE( blocks, sizeof(*blocks) );
-		return -ENOMEM;
+		return DRM_ERR(ENOMEM);
 	}
 
 	blocks->start = start;

drivers/char/drm/radeon_state.c

@@ -201,6 +201,7 @@ static __inline__ int radeon_check_and_fixup_packets( drm_radeon_private_t *dev_
 	case RADEON_EMIT_PP_TEX_SIZE_0:
 	case RADEON_EMIT_PP_TEX_SIZE_1:
 	case RADEON_EMIT_PP_TEX_SIZE_2:
+	case R200_EMIT_RB3D_BLENDCOLOR:
 		/* These packets don't contain memory offsets */
 		break;
 
@@ -563,6 +564,7 @@ static struct {
 	{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
 	{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
 	{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_1" },
+	{ R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
 };