Commit 62e2b0e2 authored by Jeff Garzik's avatar Jeff Garzik

[TG3]: More 5705 updates.

- do not zero stats/status block on 5705, they don't exist
  (in controller memory, at least)
- define TG3_MAX_MTU macro such that it takes a (tp) pointer arg,
  because the value varies between 5705 and non-5705
- use the macro to simply tg3_change_mtu
parent f404aa46
...@@ -80,8 +80,8 @@ ...@@ -80,8 +80,8 @@
/* hardware minimum and maximum for a single frame's data payload */ /* hardware minimum and maximum for a single frame's data payload */
#define TG3_MIN_MTU 60 #define TG3_MIN_MTU 60
#define TG3_MAX_MTU 9000 #define TG3_MAX_MTU(tp) \
#define TG3_MAX_MTU_5705 1500 (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705 ? 9000 : 1500)
/* These numbers seem to be hard coded in the NIC firmware somehow. /* These numbers seem to be hard coded in the NIC firmware somehow.
* You can't change the ring sizes, but you can change where you place * You can't change the ring sizes, but you can change where you place
...@@ -2785,11 +2785,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu) ...@@ -2785,11 +2785,7 @@ static int tg3_change_mtu(struct net_device *dev, int new_mtu)
{ {
struct tg3 *tp = dev->priv; struct tg3 *tp = dev->priv;
if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU) if (new_mtu < TG3_MIN_MTU || new_mtu > TG3_MAX_MTU(tp))
return -EINVAL;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705 &&
new_mtu > TG3_MAX_MTU_5705)
return -EINVAL; return -EINVAL;
if (!netif_running(dev)) { if (!netif_running(dev)) {
...@@ -4131,11 +4127,13 @@ static int tg3_reset_hw(struct tg3 *tp) ...@@ -4131,11 +4127,13 @@ static int tg3_reset_hw(struct tg3 *tp)
tg3_init_rings(tp); tg3_init_rings(tp);
/* Clear statistics/status block in chip, and status block in ram. */ /* Clear statistics/status block in chip, and status block in ram. */
for (i = NIC_SRAM_STATS_BLK; if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5705) {
i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE; for (i = NIC_SRAM_STATS_BLK;
i += sizeof(u32)) { i < NIC_SRAM_STATUS_BLK + TG3_HW_STATUS_SIZE;
tg3_write_mem(tp, i, 0); i += sizeof(u32)) {
udelay(40); tg3_write_mem(tp, i, 0);
udelay(40);
}
} }
memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE); memset(tp->hw_status, 0, TG3_HW_STATUS_SIZE);
......
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