Commit 670388c5 authored by Luis R. Rodriguez's avatar Luis R. Rodriguez Committed by John W. Linville

ath9k: add initvals and registry definitions for AR9271

Cc: Stephen Chen <stephen.chen@atheros.com>
Cc: Zhifeng Cai <zhifeng.cai@atheros.com>
Signed-off-by: default avatarLuis R. Rodriguez <lrodriguez@atheros.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent edb1f915
This diff is collapsed.
...@@ -185,6 +185,9 @@ bool ath9k_hw_init_rf(struct ath_hw *ah, ...@@ -185,6 +185,9 @@ bool ath9k_hw_init_rf(struct ath_hw *ah,
#define AR_PHY_PLL_CTL_44_2133 0xeb #define AR_PHY_PLL_CTL_44_2133 0xeb
#define AR_PHY_PLL_CTL_40_2133 0xea #define AR_PHY_PLL_CTL_40_2133 0xea
#define AR_PHY_SPECTRAL_SCAN 0x9912
#define AR_PHY_SPECTRAL_SCAN_ENABLE 0x1
#define AR_PHY_RX_DELAY 0x9914 #define AR_PHY_RX_DELAY 0x9914
#define AR_PHY_SEARCH_START_DELAY 0x9918 #define AR_PHY_SEARCH_START_DELAY 0x9918
#define AR_PHY_RX_DELAY_DELAY 0x00003FFF #define AR_PHY_RX_DELAY_DELAY 0x00003FFF
......
...@@ -1154,12 +1154,32 @@ enum { ...@@ -1154,12 +1154,32 @@ enum {
#define AR9285_AN_RF2G4_DB2_4 0x00003800 #define AR9285_AN_RF2G4_DB2_4 0x00003800
#define AR9285_AN_RF2G4_DB2_4_S 11 #define AR9285_AN_RF2G4_DB2_4_S 11
/* AR9271 : 0x7828, 0x782c different setting from AR9285 */
#define AR9271_AN_RF2G3_OB_cck 0x001C0000
#define AR9271_AN_RF2G3_OB_cck_S 18
#define AR9271_AN_RF2G3_OB_psk 0x00038000
#define AR9271_AN_RF2G3_OB_psk_S 15
#define AR9271_AN_RF2G3_OB_qam 0x00007000
#define AR9271_AN_RF2G3_OB_qam_S 12
#define AR9271_AN_RF2G3_DB_1 0x00E00000
#define AR9271_AN_RF2G3_DB_1_S 21
#define AR9271_AN_RF2G3_CCOMP 0xFFF
#define AR9271_AN_RF2G3_CCOMP_S 0
#define AR9271_AN_RF2G4_DB_2 0xE0000000
#define AR9271_AN_RF2G4_DB_2_S 29
#define AR9285_AN_RF2G6 0x7834 #define AR9285_AN_RF2G6 0x7834
#define AR9285_AN_RF2G6_CCOMP 0x00007800 #define AR9285_AN_RF2G6_CCOMP 0x00007800
#define AR9285_AN_RF2G6_CCOMP_S 11 #define AR9285_AN_RF2G6_CCOMP_S 11
#define AR9285_AN_RF2G6_OFFS 0x03f00000 #define AR9285_AN_RF2G6_OFFS 0x03f00000
#define AR9285_AN_RF2G6_OFFS_S 20 #define AR9285_AN_RF2G6_OFFS_S 20
#define AR9271_AN_RF2G6_OFFS 0x07f00000
#define AR9271_AN_RF2G6_OFFS_S 20
#define AR9285_AN_RF2G7 0x7838 #define AR9285_AN_RF2G7 0x7838
#define AR9285_AN_RF2G7_PWDDB 0x00000002 #define AR9285_AN_RF2G7_PWDDB 0x00000002
#define AR9285_AN_RF2G7_PWDDB_S 1 #define AR9285_AN_RF2G7_PWDDB_S 1
...@@ -1220,6 +1240,11 @@ enum { ...@@ -1220,6 +1240,11 @@ enum {
#define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000 #define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000
#define AR9287_AN_TOP2_XPABIAS_LVL_S 30 #define AR9287_AN_TOP2_XPABIAS_LVL_S 30
/* AR9271 specific stuff */
#define AR9271_RESET_POWER_DOWN_CONTROL 0x50044
#define AR9271_RADIO_RF_RST 0x20
#define AR9271_GATE_MAC_CTL 0x4000
#define AR_STA_ID0 0x8000 #define AR_STA_ID0 0x8000
#define AR_STA_ID1 0x8004 #define AR_STA_ID1 0x8004
#define AR_STA_ID1_SADH_MASK 0x0000FFFF #define AR_STA_ID1_SADH_MASK 0x0000FFFF
......
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