Commit 6725a88f authored by Bhawanpreet Lakha's avatar Bhawanpreet Lakha Committed by Alex Deucher

drm/amd/display: Add DCN3 DML

Add support for DML(Display mode library) for bandwidth calculations
Signed-off-by: default avatarBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 8993dee0
...@@ -61,6 +61,10 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags) ...@@ -61,6 +61,10 @@ CFLAGS_$(AMDDALPATH)/dc/dml/dcn20/display_rq_dlg_calc_20v2.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_mode_vba_21.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dcn21/display_rq_dlg_calc_21.o := $(dml_ccflags)
endif endif
ifdef CONFIG_DRM_AMD_DC_DCN3_0
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_mode_vba_30.o := $(dml_ccflags) -Wframe-larger-than=2048
CFLAGS_$(AMDDALPATH)/dc/dml/dcn30/display_rq_dlg_calc_30.o := $(dml_ccflags)
endif
CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/dml1_display_rq_dlg_calc.o := $(dml_ccflags)
CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags) CFLAGS_$(AMDDALPATH)/dc/dml/display_rq_dlg_helpers.o := $(dml_ccflags)
...@@ -72,6 +76,9 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o ...@@ -72,6 +76,9 @@ DML += dcn20/display_rq_dlg_calc_20v2.o dcn20/display_mode_vba_20v2.o
DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o DML += dcn21/display_rq_dlg_calc_21.o dcn21/display_mode_vba_21.o
endif endif
ifdef CONFIG_DRM_AMD_DC_DCN3_0
DML += dcn30/display_mode_vba_30.o dcn30/display_rq_dlg_calc_30.o
endif
AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML)) AMD_DAL_DML = $(addprefix $(AMDDALPATH)/dc/dml/,$(DML))
......
This diff is collapsed.
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DML30_DISPLAY_MODE_VBA_H__
#define __DML30_DISPLAY_MODE_VBA_H__
void dml30_recalculate(struct display_mode_lib *mode_lib);
void dml30_ModeSupportAndSystemConfigurationFull(struct display_mode_lib *mode_lib);
double dml30_CalculateWriteBackDISPCLK(
enum source_format_class WritebackPixelFormat,
double PixelClock,
double WritebackHRatio,
double WritebackVRatio,
unsigned int WritebackHTaps,
unsigned int WritebackVTaps,
long WritebackSourceWidth,
long WritebackDestinationWidth,
unsigned int HTotal,
unsigned int WritebackLineBufferSize);
#endif /* __DML30_DISPLAY_MODE_VBA_H__ */
/*
* Copyright 2020 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
* Authors: AMD
*
*/
#ifndef __DML30_DISPLAY_RQ_DLG_CALC_H__
#define __DML30_DISPLAY_RQ_DLG_CALC_H__
#include "../display_rq_dlg_helpers.h"
struct display_mode_lib;
// Function: dml_rq_dlg_get_rq_reg
// Main entry point for test to get the register values out of this DML class.
// This function calls <get_rq_param> and <extract_rq_regs> fucntions to calculate
// and then populate the rq_regs struct
// Input:
// pipe_param - pipe source configuration (e.g. vp, pitch, scaling, dest, etc.)
// Output:
// rq_regs - struct that holds all the RQ registers field value.
// See also: <display_rq_regs_st>
void dml30_rq_dlg_get_rq_reg(struct display_mode_lib *mode_lib,
display_rq_regs_st *rq_regs,
const display_pipe_params_st pipe_param);
// Function: dml_rq_dlg_get_dlg_reg
// Calculate and return DLG and TTU register struct given the system setting
// Output:
// dlg_regs - output DLG register struct
// ttu_regs - output DLG TTU register struct
// Input:
// e2e_pipe_param - "compacted" array of e2e pipe param struct
// num_pipes - num of active "pipe" or "route"
// pipe_idx - index that identifies the e2e_pipe_param that corresponding to this dlg
// cstate - 0: when calculate min_ttu_vblank it is assumed cstate is not required. 1: Normal mode, cstate is considered.
// Added for legacy or unrealistic timing tests.
void dml30_rq_dlg_get_dlg_reg(struct display_mode_lib *mode_lib,
display_dlg_regs_st *dlg_regs,
display_ttu_regs_st *ttu_regs,
display_e2e_pipe_params_st *e2e_pipe_param,
const unsigned int num_pipes,
const unsigned int pipe_idx,
const bool cstate_en,
const bool pstate_en,
const bool vm_en,
const bool ignore_viewport_pos,
const bool immediate_flip_support);
#endif
...@@ -37,6 +37,9 @@ enum dml_project { ...@@ -37,6 +37,9 @@ enum dml_project {
DML_PROJECT_NAVI10, DML_PROJECT_NAVI10,
DML_PROJECT_NAVI10v2, DML_PROJECT_NAVI10v2,
DML_PROJECT_DCN21, DML_PROJECT_DCN21,
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
DML_PROJECT_DCN30,
#endif
}; };
struct display_mode_lib; struct display_mode_lib;
...@@ -78,4 +81,12 @@ void dml_init_instance(struct display_mode_lib *lib, ...@@ -78,4 +81,12 @@ void dml_init_instance(struct display_mode_lib *lib,
const char *dml_get_status_message(enum dm_validation_status status); const char *dml_get_status_message(enum dm_validation_status status);
#if defined(CONFIG_DRM_AMD_DC_DCN3_0)
void dml_log_pipe_params(
struct display_mode_lib *mode_lib,
display_e2e_pipe_params_st *pipes,
int pipe_cnt);
void dml_log_mode_support_params(struct display_mode_lib *mode_lib);
#endif // CONFIG_DRM_AMD_DC_DCN3_0
#endif #endif
...@@ -124,6 +124,9 @@ struct _vcs_dpi_soc_bounding_box_st { ...@@ -124,6 +124,9 @@ struct _vcs_dpi_soc_bounding_box_st {
struct _vcs_dpi_ip_params_st { struct _vcs_dpi_ip_params_st {
bool use_min_dcfclk; bool use_min_dcfclk;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool clamp_min_dcfclk;
#endif
bool gpuvm_enable; bool gpuvm_enable;
bool hostvm_enable; bool hostvm_enable;
bool dsc422_native_support; bool dsc422_native_support;
......
...@@ -300,6 +300,9 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib) ...@@ -300,6 +300,9 @@ static void fetch_ip_params(struct display_mode_lib *mode_lib)
// IP Parameters // IP Parameters
mode_lib->vba.UseMinimumRequiredDCFCLK = ip->use_min_dcfclk; mode_lib->vba.UseMinimumRequiredDCFCLK = ip->use_min_dcfclk;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
mode_lib->vba.ClampMinDCFCLK = ip->clamp_min_dcfclk;
#endif
mode_lib->vba.MaxNumDPP = ip->max_num_dpp; mode_lib->vba.MaxNumDPP = ip->max_num_dpp;
mode_lib->vba.MaxNumOTG = ip->max_num_otg; mode_lib->vba.MaxNumOTG = ip->max_num_otg;
mode_lib->vba.MaxNumHDMIFRLOutputs = ip->max_num_hdmi_frl_outputs; mode_lib->vba.MaxNumHDMIFRLOutputs = ip->max_num_hdmi_frl_outputs;
......
...@@ -924,6 +924,9 @@ struct vba_vars_st { ...@@ -924,6 +924,9 @@ struct vba_vars_st {
double BPP; double BPP;
enum odm_combine_policy ODMCombinePolicy; enum odm_combine_policy ODMCombinePolicy;
bool UseMinimumRequiredDCFCLK; bool UseMinimumRequiredDCFCLK;
#ifdef CONFIG_DRM_AMD_DC_DCN3_0
bool ClampMinDCFCLK;
#endif
bool AllowDramClockChangeOneDisplayVactive; bool AllowDramClockChangeOneDisplayVactive;
bool SynchronizeTimingsIfSingleRefreshRate; bool SynchronizeTimingsIfSingleRefreshRate;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment