drm/nouveau/fb: switch to device pri macros

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.c

@@ -29,7 +29,8 @@
 int
 nvkm_fb_bios_memtype(struct nvkm_bios *bios)
 {
-	const u8 ramcfg = (nv_rd32(bios, 0x101000) & 0x0000003c) >> 2;
+	struct nvkm_device *device = bios->subdev.device;
+	const u8 ramcfg = (nvkm_rd32(device, 0x101000) & 0x0000003c) >> 2;
 	struct nvbios_M0203E M0203E;
 	u8 ver, hdr;
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.c

@@ -35,8 +35,9 @@ gf100_fb_memtype_valid(struct nvkm_fb *fb, u32 tile_flags)
 static void
 gf100_fb_intr(struct nvkm_subdev *subdev)
 {
+	struct nvkm_device *device = subdev->device;
 	struct gf100_fb *fb = (void *)subdev;
-	u32 intr = nv_rd32(fb, 0x000100);
+	u32 intr = nvkm_rd32(device, 0x000100);
 	if (intr & 0x08000000)
 		nv_debug(fb, "PFFB intr\n");
 	if (intr & 0x00002000)
@@ -47,6 +48,7 @@ int
 gf100_fb_init(struct nvkm_object *object)
 {
 	struct gf100_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->base.subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(&fb->base);
@@ -54,9 +56,9 @@ gf100_fb_init(struct nvkm_object *object)
 		return ret;
 
 	if (fb->r100c10_page)
-		nv_wr32(fb, 0x100c10, fb->r100c10 >> 8);
+		nvkm_wr32(device, 0x100c10, fb->r100c10 >> 8);
 
-	nv_mask(fb, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
+	nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.c

@@ -25,13 +25,14 @@ static int
 gk20a_fb_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_mask(fb, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
+	nvkm_mask(device, 0x100c80, 0x00000001, 0x00000000); /* 128KiB lpg */
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.c

@@ -37,6 +37,7 @@ static int
 nv04_fb_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(fb);
@@ -47,7 +48,7 @@ nv04_fb_init(struct nvkm_object *object)
 	 * nvidia reading PFB_CFG_0, then writing back its original value.
 	 * (which was 0x701114 in this case)
 	 */
-	nv_wr32(fb, NV04_PFB_CFG0, 0x1114);
+	nvkm_wr32(device, NV04_PFB_CFG0, 0x1114);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.c

@@ -46,10 +46,11 @@ nv10_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 void
 nv10_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(fb, 0x100244 + (i * 0x10), tile->limit);
-	nv_wr32(fb, 0x100248 + (i * 0x10), tile->pitch);
-	nv_wr32(fb, 0x100240 + (i * 0x10), tile->addr);
-	nv_rd32(fb, 0x100240 + (i * 0x10));
+	struct nvkm_device *device = fb->subdev.device;
+	nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit);
+	nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch);
+	nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr);
+	nvkm_rd32(device, 0x100240 + (i * 0x10));
 }
 
 struct nvkm_oclass *

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.c

@@ -68,11 +68,12 @@ nv20_fb_tile_fini(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 void
 nv20_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(fb, 0x100244 + (i * 0x10), tile->limit);
-	nv_wr32(fb, 0x100248 + (i * 0x10), tile->pitch);
-	nv_wr32(fb, 0x100240 + (i * 0x10), tile->addr);
-	nv_rd32(fb, 0x100240 + (i * 0x10));
-	nv_wr32(fb, 0x100300 + (i * 0x04), tile->zcomp);
+	struct nvkm_device *device = fb->subdev.device;
+	nvkm_wr32(device, 0x100244 + (i * 0x10), tile->limit);
+	nvkm_wr32(device, 0x100248 + (i * 0x10), tile->pitch);
+	nvkm_wr32(device, 0x100240 + (i * 0x10), tile->addr);
+	nvkm_rd32(device, 0x100240 + (i * 0x10));
+	nvkm_wr32(device, 0x100300 + (i * 0x04), tile->zcomp);
 }
 
 struct nvkm_oclass *

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.c

@@ -66,7 +66,8 @@ calc_bias(struct nvkm_fb *fb, int k, int i, int j)
 {
 	struct nvkm_device *device = nv_device(fb);
 	int b = (device->chipset > 0x30 ?
-		 nv_rd32(fb, 0x122c + 0x10 * k + 0x4 * j) >> (4 * (i ^ 1)) :
+		 nvkm_rd32(device, 0x122c + 0x10 * k + 0x4 * j) >>
+			(4 * (i ^ 1)) :
 		 0) & 0xf;
 
 	return 2 * (b & 0x8 ? b - 0x10 : b);
@@ -103,16 +104,16 @@ nv30_fb_init(struct nvkm_object *object)
 	    device->chipset == 0x35) {
 		/* Related to ROP count */
 		int n = (device->chipset == 0x31 ? 2 : 4);
-		int l = nv_rd32(fb, 0x1003d0);
+		int l = nvkm_rd32(device, 0x1003d0);
 
 		for (i = 0; i < n; i++) {
 			for (j = 0; j < 3; j++)
-				nv_wr32(fb, 0x10037c + 0xc * i + 0x4 * j,
-					calc_ref(fb, l, 0, j));
+				nvkm_wr32(device, 0x10037c + 0xc * i + 0x4 * j,
+					  calc_ref(fb, l, 0, j));
 
 			for (j = 0; j < 2; j++)
-				nv_wr32(fb, 0x1003ac + 0x8 * i + 0x4 * j,
-					calc_ref(fb, l, 1, j));
+				nvkm_wr32(device, 0x1003ac + 0x8 * i + 0x4 * j,
+					  calc_ref(fb, l, 1, j));
 		}
 	}
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.c

@@ -46,13 +46,14 @@ static int
 nv40_fb_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_mask(fb, 0x10033c, 0x00008000, 0x00000000);
+	nvkm_mask(device, 0x10033c, 0x00008000, 0x00000000);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.c

@@ -28,24 +28,26 @@
 void
 nv41_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(fb, 0x100604 + (i * 0x10), tile->limit);
-	nv_wr32(fb, 0x100608 + (i * 0x10), tile->pitch);
-	nv_wr32(fb, 0x100600 + (i * 0x10), tile->addr);
-	nv_rd32(fb, 0x100600 + (i * 0x10));
-	nv_wr32(fb, 0x100700 + (i * 0x04), tile->zcomp);
+	struct nvkm_device *device = fb->subdev.device;
+	nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);
+	nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);
+	nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);
+	nvkm_rd32(device, 0x100600 + (i * 0x10));
+	nvkm_wr32(device, 0x100700 + (i * 0x04), tile->zcomp);
 }
 
 int
 nv41_fb_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_wr32(fb, 0x100800, 0x00000001);
+	nvkm_wr32(device, 0x100800, 0x00000001);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.c

@@ -38,24 +38,26 @@ nv44_fb_tile_init(struct nvkm_fb *fb, int i, u32 addr, u32 size, u32 pitch,
 void
 nv44_fb_tile_prog(struct nvkm_fb *fb, int i, struct nvkm_fb_tile *tile)
 {
-	nv_wr32(fb, 0x100604 + (i * 0x10), tile->limit);
-	nv_wr32(fb, 0x100608 + (i * 0x10), tile->pitch);
-	nv_wr32(fb, 0x100600 + (i * 0x10), tile->addr);
-	nv_rd32(fb, 0x100600 + (i * 0x10));
+	struct nvkm_device *device = fb->subdev.device;
+	nvkm_wr32(device, 0x100604 + (i * 0x10), tile->limit);
+	nvkm_wr32(device, 0x100608 + (i * 0x10), tile->pitch);
+	nvkm_wr32(device, 0x100600 + (i * 0x10), tile->addr);
+	nvkm_rd32(device, 0x100600 + (i * 0x10));
 }
 
 int
 nv44_fb_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(fb);
 	if (ret)
 		return ret;
 
-	nv_wr32(fb, 0x100850, 0x80000000);
-	nv_wr32(fb, 0x100800, 0x00000001);
+	nvkm_wr32(device, 0x100850, 0x80000000);
+	nvkm_wr32(device, 0x100800, 0x00000001);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c

@@ -153,16 +153,16 @@ nv50_fb_intr(struct nvkm_subdev *subdev)
 	u8 st0, st1, st2, st3;
 	int i;
 
-	idx = nv_rd32(fb, 0x100c90);
+	idx = nvkm_rd32(device, 0x100c90);
 	if (!(idx & 0x80000000))
 		return;
 	idx &= 0x00ffffff;
 
 	for (i = 0; i < 6; i++) {
-		nv_wr32(fb, 0x100c90, idx | i << 24);
-		trap[i] = nv_rd32(fb, 0x100c94);
+		nvkm_wr32(device, 0x100c90, idx | i << 24);
+		trap[i] = nvkm_rd32(device, 0x100c94);
 	}
-	nv_wr32(fb, 0x100c90, idx | 0x80000000);
+	nvkm_wr32(device, 0x100c90, idx | 0x80000000);
 
 	/* decode status bits into something more useful */
 	if (device->chipset  < 0xa3 ||
@@ -286,6 +286,7 @@ nv50_fb_init(struct nvkm_object *object)
 {
 	struct nv50_fb_impl *impl = (void *)object->oclass;
 	struct nv50_fb *fb = (void *)object;
+	struct nvkm_device *device = fb->base.subdev.device;
 	int ret;
 
 	ret = nvkm_fb_init(&fb->base);
@@ -296,11 +297,11 @@ nv50_fb_init(struct nvkm_object *object)
 	 * scratch page, VRAM->GART blits with M2MF (as in DDX DFS)
 	 * cause IOMMU "read from address 0" errors (rh#561267)
 	 */
-	nv_wr32(fb, 0x100c08, fb->r100c08 >> 8);
+	nvkm_wr32(device, 0x100c08, fb->r100c08 >> 8);
 
 	/* This is needed to get meaningful information from 100c90
 	 * on traps. No idea what these values mean exactly. */
-	nv_wr32(fb, 0x100c90, impl->trap);
+	nvkm_wr32(device, 0x100c90, impl->trap);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramfuc.h

 #ifndef __NVKM_FBRAM_FUC_H__
 #define __NVKM_FBRAM_FUC_H__
+#include <subdev/fb.h>
 #include <subdev/pmu.h>
 
 struct ramfuc {
@@ -82,8 +83,9 @@ ramfuc_exec(struct ramfuc *ram, bool exec)
 static inline u32
 ramfuc_rd32(struct ramfuc *ram, struct ramfuc_reg *reg)
 {
+	struct nvkm_device *device = ram->fb->subdev.device;
 	if (reg->sequence != ram->sequence)
-		reg->data = nv_rd32(ram->fb, reg->addr);
+		reg->data = nvkm_rd32(device, reg->addr);
 	return reg->data;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.c

@@ -108,8 +108,9 @@ gf100_ram_train(struct gf100_ramfuc *fuc, u32 magic)
 {
 	struct gf100_ram *ram = container_of(fuc, typeof(*ram), fuc);
 	struct nvkm_fb *fb = nvkm_fb(ram);
-	u32 part = nv_rd32(fb, 0x022438), i;
-	u32 mask = nv_rd32(fb, 0x022554);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 part = nvkm_rd32(device, 0x022438), i;
+	u32 mask = nvkm_rd32(device, 0x022554);
 	u32 addr = 0x110974;
 
 	ram_wr32(fuc, 0x10f910, magic);
@@ -507,13 +508,14 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 		  void **pobject)
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
-	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct nvkm_device *device = fb->subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	struct nvkm_ram *ram;
 	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
 	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-	u32 parts = nv_rd32(fb, 0x022438);
-	u32 pmask = nv_rd32(fb, maskaddr);
-	u32 bsize = nv_rd32(fb, 0x10f20c);
+	u32 parts = nvkm_rd32(device, 0x022438);
+	u32 pmask = nvkm_rd32(device, maskaddr);
+	u32 bsize = nvkm_rd32(device, 0x10f20c);
 	u32 offset, length;
 	bool uniform = true;
 	int ret, part;
@@ -523,24 +525,24 @@ gf100_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	nv_debug(fb, "0x100800: 0x%08x\n", nv_rd32(fb, 0x100800));
+	nv_debug(fb, "0x100800: 0x%08x\n", nvkm_rd32(device, 0x100800));
 	nv_debug(fb, "parts 0x%08x mask 0x%08x\n", parts, pmask);
 
 	ram->type = nvkm_fb_bios_memtype(bios);
-	ram->ranks = (nv_rd32(fb, 0x10f200) & 0x00000004) ? 2 : 1;
+	ram->ranks = (nvkm_rd32(device, 0x10f200) & 0x00000004) ? 2 : 1;
 
 	/* read amount of vram attached to each memory controller */
 	for (part = 0; part < parts; part++) {
 		if (!(pmask & (1 << part))) {
-			u32 psize = nv_rd32(fb, 0x11020c + (part * 0x1000));
-			if (psize != bsize) {
-				if (psize < bsize)
-					bsize = psize;
+			u32 size = nvkm_rd32(device, 0x11020c + (part * 0x1000));
+			if (size != bsize) {
+				if (size < bsize)
+					bsize = size;
 				uniform = false;
 			}
 
-			nv_debug(fb, "%d: mem_amount 0x%08x\n", part, psize);
-			ram->size += (u64)psize << 20;
+			nv_debug(fb, "%d: mem_amount 0x%08x\n", part, size);
+			ram->size += (u64)size << 20;
 		}
 	}
 
@@ -577,6 +579,7 @@ static int
 gf100_ram_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object->parent;
+	struct nvkm_device *device = fb->subdev.device;
 	struct gf100_ram *ram = (void *)object;
 	int ret, i;
 
@@ -601,16 +604,16 @@ gf100_ram_init(struct nvkm_object *object)
 		};
 
 		for (i = 0; i < 0x30; i++) {
-			nv_wr32(fb, 0x10f968, 0x00000000 | (i << 8));
-			nv_wr32(fb, 0x10f96c, 0x00000000 | (i << 8));
-			nv_wr32(fb, 0x10f920, 0x00000100 | train0[i % 12]);
-			nv_wr32(fb, 0x10f924, 0x00000100 | train0[i % 12]);
-			nv_wr32(fb, 0x10f918,              train1[i % 12]);
-			nv_wr32(fb, 0x10f91c,              train1[i % 12]);
-			nv_wr32(fb, 0x10f920, 0x00000000 | train0[i % 12]);
-			nv_wr32(fb, 0x10f924, 0x00000000 | train0[i % 12]);
-			nv_wr32(fb, 0x10f918,              train1[i % 12]);
-			nv_wr32(fb, 0x10f91c,              train1[i % 12]);
+			nvkm_wr32(device, 0x10f968, 0x00000000 | (i << 8));
+			nvkm_wr32(device, 0x10f96c, 0x00000000 | (i << 8));
+			nvkm_wr32(device, 0x10f920, 0x00000100 | train0[i % 12]);
+			nvkm_wr32(device, 0x10f924, 0x00000100 | train0[i % 12]);
+			nvkm_wr32(device, 0x10f918,              train1[i % 12]);
+			nvkm_wr32(device, 0x10f91c,              train1[i % 12]);
+			nvkm_wr32(device, 0x10f920, 0x00000000 | train0[i % 12]);
+			nvkm_wr32(device, 0x10f924, 0x00000000 | train0[i % 12]);
+			nvkm_wr32(device, 0x10f918,              train1[i % 12]);
+			nvkm_wr32(device, 0x10f91c,              train1[i % 12]);
 		}
 	}	break;
 	default:

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.c

@@ -228,8 +228,9 @@ static void
 gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
 	       u32 _mask, u32 _data, u32 _copy)
 {
-	struct gk104_fb *fb = (void *)nvkm_fb(ram);
+	struct nvkm_fb *fb = nvkm_fb(ram);
 	struct ramfuc *fuc = &ram->fuc.base;
+	struct nvkm_device *device = fb->subdev.device;
 	u32 addr = 0x110000 + (reg->addr & 0xfff);
 	u32 mask = _mask | _copy;
 	u32 data = (_data & _mask) | (reg->data & _copy);
@@ -237,7 +238,7 @@ gk104_ram_nuts(struct gk104_ram *ram, struct ramfuc_reg *reg,
 
 	for (i = 0; i < 16; i++, addr += 0x1000) {
 		if (ram->pnuts & (1 << i)) {
-			u32 prev = nv_rd32(fb, addr);
+			u32 prev = nvkm_rd32(device, addr);
 			u32 next = (prev & ~mask) | data;
 			nvkm_memx_wr32(fuc->memx, addr, next);
 		}
@@ -1067,6 +1068,7 @@ gk104_ram_calc(struct nvkm_fb *fb, u32 freq)
 static void
 gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq)
 {
+	struct nvkm_device *device = fb->subdev.device;
 	struct gk104_ram *ram = (void *)fb->ram;
 	struct nvkm_ram_data *cfg;
 	u32 mhz = freq / 1000;
@@ -1089,31 +1091,31 @@ gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq)
 		data |= cfg->bios.rammap_11_09_01ff;
 		mask |= 0x000001ff;
 	}
-	nv_mask(fb, 0x10f468, mask, data);
+	nvkm_mask(device, 0x10f468, mask, data);
 
 	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0400) {
 		data |= cfg->bios.rammap_11_0a_0400;
 		mask |= 0x00000001;
 	}
-	nv_mask(fb, 0x10f420, mask, data);
+	nvkm_mask(device, 0x10f420, mask, data);
 
 	if (mask = 0, data = 0, ram->diff.rammap_11_0a_0800) {
 		data |= cfg->bios.rammap_11_0a_0800;
 		mask |= 0x00000001;
 	}
-	nv_mask(fb, 0x10f430, mask, data);
+	nvkm_mask(device, 0x10f430, mask, data);
 
 	if (mask = 0, data = 0, ram->diff.rammap_11_0b_01f0) {
 		data |= cfg->bios.rammap_11_0b_01f0;
 		mask |= 0x0000001f;
 	}
-	nv_mask(fb, 0x10f400, mask, data);
+	nvkm_mask(device, 0x10f400, mask, data);
 
 	if (mask = 0, data = 0, ram->diff.rammap_11_0b_0200) {
 		data |= cfg->bios.rammap_11_0b_0200 << 9;
 		mask |= 0x00000200;
 	}
-	nv_mask(fb, 0x10f410, mask, data);
+	nvkm_mask(device, 0x10f410, mask, data);
 
 	if (mask = 0, data = 0, ram->diff.rammap_11_0d) {
 		data |= cfg->bios.rammap_11_0d << 16;
@@ -1123,7 +1125,7 @@ gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq)
 		data |= cfg->bios.rammap_11_0f << 8;
 		mask |= 0x0000ff00;
 	}
-	nv_mask(fb, 0x10f440, mask, data);
+	nvkm_mask(device, 0x10f440, mask, data);
 
 	if (mask = 0, data = 0, ram->diff.rammap_11_0e) {
 		data |= cfg->bios.rammap_11_0e << 8;
@@ -1137,7 +1139,7 @@ gk104_ram_prog_0(struct nvkm_fb *fb, u32 freq)
 		data |= cfg->bios.rammap_11_0b_0400 << 5;
 		mask |= 0x00000020;
 	}
-	nv_mask(fb, 0x10f444, mask, data);
+	nvkm_mask(device, 0x10f444, mask, data);
 }
 
 static int
@@ -1245,6 +1247,7 @@ gk104_ram_train_type(struct nvkm_fb *fb, int i, u8 ramcfg,
 static int
 gk104_ram_train_init_0(struct nvkm_fb *fb, struct gk104_ram_train *train)
 {
+	struct nvkm_device *device = fb->subdev.device;
 	int i, j;
 
 	if ((train->mask & 0x03d3) != 0x03d3) {
@@ -1254,22 +1257,22 @@ gk104_ram_train_init_0(struct nvkm_fb *fb, struct gk104_ram_train *train)
 
 	for (i = 0; i < 0x30; i++) {
 		for (j = 0; j < 8; j += 4) {
-			nv_wr32(fb, 0x10f968 + j, 0x00000000 | (i << 8));
-			nv_wr32(fb, 0x10f920 + j, 0x00000000 |
+			nvkm_wr32(device, 0x10f968 + j, 0x00000000 | (i << 8));
+			nvkm_wr32(device, 0x10f920 + j, 0x00000000 |
 						   train->type08.data[i] << 4 |
 						   train->type06.data[i]);
-			nv_wr32(fb, 0x10f918 + j, train->type00.data[i]);
-			nv_wr32(fb, 0x10f920 + j, 0x00000100 |
+			nvkm_wr32(device, 0x10f918 + j, train->type00.data[i]);
+			nvkm_wr32(device, 0x10f920 + j, 0x00000100 |
 						   train->type09.data[i] << 4 |
 						   train->type07.data[i]);
-			nv_wr32(fb, 0x10f918 + j, train->type01.data[i]);
+			nvkm_wr32(device, 0x10f918 + j, train->type01.data[i]);
 		}
 	}
 
 	for (j = 0; j < 8; j += 4) {
 		for (i = 0; i < 0x100; i++) {
-			nv_wr32(fb, 0x10f968 + j, i);
-			nv_wr32(fb, 0x10f900 + j, train->type04.data[i]);
+			nvkm_wr32(device, 0x10f968 + j, i);
+			nvkm_wr32(device, 0x10f900 + j, train->type04.data[i]);
 		}
 	}
 
@@ -1310,7 +1313,8 @@ gk104_ram_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = (void *)object->parent;
 	struct gk104_ram *ram   = (void *)object;
-	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct nvkm_device *device = fb->subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	u8  ver, hdr, cnt, len, snr, ssz;
 	u32 data, save;
 	int ret, i;
@@ -1336,10 +1340,10 @@ gk104_ram_init(struct nvkm_object *object)
 
 	cnt  = nv_ro08(bios, data + 0x14); /* guess at count */
 	data = nv_ro32(bios, data + 0x10); /* guess u32... */
-	save = nv_rd32(fb, 0x10f65c) & 0x000000f0;
+	save = nvkm_rd32(device, 0x10f65c) & 0x000000f0;
 	for (i = 0; i < cnt; i++, data += 4) {
 		if (i != save >> 4) {
-			nv_mask(fb, 0x10f65c, 0x000000f0, i << 4);
+			nvkm_mask(device, 0x10f65c, 0x000000f0, i << 4);
 			nvbios_exec(&(struct nvbios_init) {
 					.subdev = nv_subdev(fb),
 					.bios = bios,
@@ -1348,10 +1352,10 @@ gk104_ram_init(struct nvkm_object *object)
 				    });
 		}
 	}
-	nv_mask(fb, 0x10f65c, 0x000000f0, save);
-	nv_mask(fb, 0x10f584, 0x11000000, 0x00000000);
-	nv_wr32(fb, 0x10ecc0, 0xffffffff);
-	nv_mask(fb, 0x10f160, 0x00000010, 0x00000010);
+	nvkm_mask(device, 0x10f65c, 0x000000f0, save);
+	nvkm_mask(device, 0x10f584, 0x11000000, 0x00000000);
+	nvkm_wr32(device, 0x10ecc0, 0xffffffff);
+	nvkm_mask(device, 0x10f160, 0x00000010, 0x00000010);
 
 	return gk104_ram_train_init(fb);
 }
@@ -1445,8 +1449,9 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	       struct nvkm_object **pobject)
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
-	struct nvkm_bios *bios = nvkm_bios(fb);
-	struct nvkm_gpio *gpio = nvkm_gpio(fb);
+	struct nvkm_device *device = fb->subdev.device;
+	struct nvkm_bios *bios = device->bios;
+	struct nvkm_gpio *gpio = device->gpio;
 	struct dcb_gpio_func func;
 	struct gk104_ram *ram;
 	int ret, i;
@@ -1477,12 +1482,12 @@ gk104_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	 * already without having to treat some of them differently to
 	 * the others....
 	 */
-	ram->parts = nv_rd32(fb, 0x022438);
-	ram->pmask = nv_rd32(fb, 0x022554);
+	ram->parts = nvkm_rd32(device, 0x022438);
+	ram->pmask = nvkm_rd32(device, 0x022554);
 	ram->pnuts = 0;
 	for (i = 0, tmp = 0; i < ram->parts; i++) {
 		if (!(ram->pmask & (1 << i))) {
-			u32 cfg1 = nv_rd32(fb, 0x110204 + (i * 0x1000));
+			u32 cfg1 = nvkm_rd32(device, 0x110204 + (i * 0x1000));
 			if (tmp && tmp != cfg1) {
 				ram->pnuts |= (1 << i);
 				continue;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.c

@@ -198,12 +198,12 @@ gt215_link_train(struct nvkm_fb *fb)
 		goto out;
 
 	/* Do this *after* calc, eliminates write in script */
-	nv_wr32(fb, 0x111400, 0x00000000);
+	nvkm_wr32(device, 0x111400, 0x00000000);
 	/* XXX: Magic writes that improve train reliability? */
-	nv_mask(fb, 0x100674, 0x0000ffff, 0x00000000);
-	nv_mask(fb, 0x1005e4, 0x0000ffff, 0x00000000);
-	nv_mask(fb, 0x100b0c, 0x000000ff, 0x00000000);
-	nv_wr32(fb, 0x100c04, 0x00000400);
+	nvkm_mask(device, 0x100674, 0x0000ffff, 0x00000000);
+	nvkm_mask(device, 0x1005e4, 0x0000ffff, 0x00000000);
+	nvkm_mask(device, 0x100b0c, 0x000000ff, 0x00000000);
+	nvkm_wr32(device, 0x100c04, 0x00000400);
 
 	/* Now the training script */
 	r1700 = ram_rd32(fuc, 0x001700);
@@ -240,8 +240,8 @@ gt215_link_train(struct nvkm_fb *fb)
 	ram_exec(fuc, true);
 
 	/* Post-processing, avoids flicker */
-	nv_mask(fb, 0x616308, 0x10, 0x10);
-	nv_mask(fb, 0x616b08, 0x10, 0x10);
+	nvkm_mask(device, 0x616308, 0x10, 0x10);
+	nvkm_mask(device, 0x616b08, 0x10, 0x10);
 
 	gt215_clk_post(clk, f);
 
@@ -279,7 +279,8 @@ gt215_link_train_init(struct nvkm_fb *fb)
 		0x33333333, 0x55555555, 0x77777777, 0x66666666,
 		0x99999999, 0x88888888, 0xeeeeeeee, 0xbbbbbbbb,
 	};
-	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct nvkm_device *device = fb->subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	struct gt215_ram *ram = (void *)fb->ram;
 	struct gt215_ltrain *train = &ram->ltrain;
 	struct nvkm_mem *mem;
@@ -306,32 +307,32 @@ gt215_link_train_init(struct nvkm_fb *fb)
 
 	mem = ram->ltrain.mem;
 
-	nv_wr32(fb, 0x100538, 0x10000000 | (mem->offset >> 16));
-	nv_wr32(fb, 0x1005a8, 0x0000ffff);
-	nv_mask(fb, 0x10f800, 0x00000001, 0x00000001);
+	nvkm_wr32(device, 0x100538, 0x10000000 | (mem->offset >> 16));
+	nvkm_wr32(device, 0x1005a8, 0x0000ffff);
+	nvkm_mask(device, 0x10f800, 0x00000001, 0x00000001);
 
 	for (i = 0; i < 0x30; i++) {
-		nv_wr32(fb, 0x10f8c0, (i << 8) | i);
-		nv_wr32(fb, 0x10f900, pattern[i % 16]);
+		nvkm_wr32(device, 0x10f8c0, (i << 8) | i);
+		nvkm_wr32(device, 0x10f900, pattern[i % 16]);
 	}
 
 	for (i = 0; i < 0x30; i++) {
-		nv_wr32(fb, 0x10f8e0, (i << 8) | i);
-		nv_wr32(fb, 0x10f920, pattern[i % 16]);
+		nvkm_wr32(device, 0x10f8e0, (i << 8) | i);
+		nvkm_wr32(device, 0x10f920, pattern[i % 16]);
 	}
 
 	/* And upload the pattern */
-	r001700 = nv_rd32(fb, 0x1700);
-	nv_wr32(fb, 0x1700, mem->offset >> 16);
+	r001700 = nvkm_rd32(device, 0x1700);
+	nvkm_wr32(device, 0x1700, mem->offset >> 16);
 	for (i = 0; i < 16; i++)
-		nv_wr32(fb, 0x700000 + (i << 2), pattern[i]);
+		nvkm_wr32(device, 0x700000 + (i << 2), pattern[i]);
 	for (i = 0; i < 16; i++)
-		nv_wr32(fb, 0x700100 + (i << 2), pattern[i]);
-	nv_wr32(fb, 0x1700, r001700);
+		nvkm_wr32(device, 0x700100 + (i << 2), pattern[i]);
+	nvkm_wr32(device, 0x1700, r001700);
 
-	train->r_100720 = nv_rd32(fb, 0x100720);
-	train->r_1111e0 = nv_rd32(fb, 0x1111e0);
-	train->r_111400 = nv_rd32(fb, 0x111400);
+	train->r_100720 = nvkm_rd32(device, 0x100720);
+	train->r_1111e0 = nvkm_rd32(device, 0x1111e0);
+	train->r_111400 = nvkm_rd32(device, 0x111400);
 	return 0;
 }
 
@@ -351,15 +352,16 @@ gt215_link_train_fini(struct nvkm_fb *fb)
 static int
 gt215_ram_timing_calc(struct nvkm_fb *fb, u32 *timing)
 {
+	struct nvkm_device *device = fb->subdev.device;
 	struct gt215_ram *ram = (void *)fb->ram;
 	struct nvbios_ramcfg *cfg = &ram->base.target.bios;
 	int tUNK_base, tUNK_40_0, prevCL;
 	u32 cur2, cur3, cur7, cur8;
 
-	cur2 = nv_rd32(fb, 0x100228);
-	cur3 = nv_rd32(fb, 0x10022c);
-	cur7 = nv_rd32(fb, 0x10023c);
-	cur8 = nv_rd32(fb, 0x100240);
+	cur2 = nvkm_rd32(device, 0x100228);
+	cur3 = nvkm_rd32(device, 0x10022c);
+	cur7 = nvkm_rd32(device, 0x10023c);
+	cur8 = nvkm_rd32(device, 0x100240);
 
 
 	switch ((!T(CWL)) * ram->base.type) {
@@ -864,16 +866,16 @@ gt215_ram_prog(struct nvkm_fb *fb)
 	bool exec = nvkm_boolopt(device->cfgopt, "NvMemExec", true);
 
 	if (exec) {
-		nv_mask(fb, 0x001534, 0x2, 0x2);
+		nvkm_mask(device, 0x001534, 0x2, 0x2);
 
 		ram_exec(fuc, true);
 
 		/* Post-processing, avoids flicker */
-		nv_mask(fb, 0x002504, 0x1, 0x0);
-		nv_mask(fb, 0x001534, 0x2, 0x0);
+		nvkm_mask(device, 0x002504, 0x1, 0x0);
+		nvkm_mask(device, 0x001534, 0x2, 0x0);
 
-		nv_mask(fb, 0x616308, 0x10, 0x10);
-		nv_mask(fb, 0x616b08, 0x10, 0x10);
+		nvkm_mask(device, 0x616308, 0x10, 0x10);
+		nvkm_mask(device, 0x616b08, 0x10, 0x10);
 	} else {
 		ram_exec(fuc, false);
 	}

drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.c

@@ -36,6 +36,7 @@ mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 	u32 rsvd_head = ( 256 * 1024); /* vga memory */
 	u32 rsvd_tail = (1024 * 1024); /* vbios etc */
 	struct nvkm_fb *fb = nvkm_fb(parent);
+	struct nvkm_device *device = fb->subdev.device;
 	struct mcp77_ram *ram;
 	int ret;
 
@@ -45,8 +46,8 @@ mcp77_ram_ctor(struct nvkm_object *parent, struct nvkm_object *engine,
 		return ret;
 
 	ram->base.type   = NV_MEM_TYPE_STOLEN;
-	ram->base.stolen = (u64)nv_rd32(fb, 0x100e10) << 12;
-	ram->base.size   = (u64)nv_rd32(fb, 0x100e14) << 12;
+	ram->base.stolen = (u64)nvkm_rd32(device, 0x100e10) << 12;
+	ram->base.size   = (u64)nvkm_rd32(device, 0x100e14) << 12;
 
 	rsvd_tail += 0x1000;
 	ram->poller_base = ram->base.size - rsvd_tail;
@@ -66,6 +67,7 @@ static int
 mcp77_ram_init(struct nvkm_object *object)
 {
 	struct nvkm_fb *fb = nvkm_fb(object);
+	struct nvkm_device *device = fb->subdev.device;
 	struct mcp77_ram *ram = (void *)object;
 	int ret;
 	u64 dniso, hostnb, flush;
@@ -81,12 +83,12 @@ mcp77_ram_init(struct nvkm_object *object)
 	/* Enable NISO poller for various clients and set their associated
 	 * read address, only for MCP77/78 and MCP79/7A. (fd#25701)
 	 */
-	nv_wr32(fb, 0x100c18, dniso);
-	nv_mask(fb, 0x100c14, 0x00000000, 0x00000001);
-	nv_wr32(fb, 0x100c1c, hostnb);
-	nv_mask(fb, 0x100c14, 0x00000000, 0x00000002);
-	nv_wr32(fb, 0x100c24, flush);
-	nv_mask(fb, 0x100c14, 0x00000000, 0x00010000);
+	nvkm_wr32(device, 0x100c18, dniso);
+	nvkm_mask(device, 0x100c14, 0x00000000, 0x00000001);
+	nvkm_wr32(device, 0x100c1c, hostnb);
+	nvkm_mask(device, 0x100c14, 0x00000000, 0x00000002);
+	nvkm_wr32(device, 0x100c24, flush);
+	nvkm_mask(device, 0x100c14, 0x00000000, 0x00010000);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.c

@@ -31,7 +31,8 @@ nv04_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
-	u32 boot0 = nv_rd32(fb, NV04_PFB_BOOT_0);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 boot0 = nvkm_rd32(device, NV04_PFB_BOOT_0);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.c

@@ -30,7 +30,8 @@ nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
-	u32 cfg0 = nv_rd32(fb, 0x100200);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 cfg0 = nvkm_rd32(device, 0x100200);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -43,7 +44,7 @@ nv10_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	else
 		ram->type = NV_MEM_TYPE_SDRAM;
 
-	ram->size = nv_rd32(fb, 0x10020c) & 0xff000000;
+	ram->size = nvkm_rd32(device, 0x10020c) & 0xff000000;
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.c

@@ -30,7 +30,8 @@ nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
-	u32 pbus1218 = nv_rd32(fb, 0x001218);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 pbus1218 = nvkm_rd32(device, 0x001218);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -44,9 +45,9 @@ nv20_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	case 0x00000200: ram->type = NV_MEM_TYPE_GDDR3; break;
 	case 0x00000300: ram->type = NV_MEM_TYPE_GDDR2; break;
 	}
-	ram->size  = (nv_rd32(fb, 0x10020c) & 0xff000000);
-	ram->parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
-	ram->tags  = nv_rd32(fb, 0x100320);
+	ram->size  = (nvkm_rd32(device, 0x10020c) & 0xff000000);
+	ram->parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;
+	ram->tags  = nvkm_rd32(device, 0x100320);
 	return 0;
 }
 

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.c

@@ -66,7 +66,8 @@ nv40_ram_calc(struct nvkm_fb *fb, u32 freq)
 int
 nv40_ram_prog(struct nvkm_fb *fb)
 {
-	struct nvkm_bios *bios = nvkm_bios(fb);
+	struct nvkm_device *device = fb->subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	struct nv40_ram *ram = (void *)fb->ram;
 	struct bit_entry M;
 	u32 crtc_mask = 0;
@@ -75,12 +76,12 @@ nv40_ram_prog(struct nvkm_fb *fb)
 
 	/* determine which CRTCs are active, fetch VGA_SR1 for each */
 	for (i = 0; i < 2; i++) {
-		u32 vbl = nv_rd32(fb, 0x600808 + (i * 0x2000));
+		u32 vbl = nvkm_rd32(device, 0x600808 + (i * 0x2000));
 		u32 cnt = 0;
 		do {
-			if (vbl != nv_rd32(fb, 0x600808 + (i * 0x2000))) {
-				nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
-				sr1[i] = nv_rd08(fb, 0x0c03c5 + (i * 0x2000));
+			if (vbl != nvkm_rd32(device, 0x600808 + (i * 0x2000))) {
+				nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
+				sr1[i] = nvkm_rd08(device, 0x0c03c5 + (i * 0x2000));
 				if (!(sr1[i] & 0x20))
 					crtc_mask |= (1 << i);
 				break;
@@ -95,45 +96,45 @@ nv40_ram_prog(struct nvkm_fb *fb)
 			continue;
 		nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00000000);
 		nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
-		nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
-		nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
+		nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
+		nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i] | 0x20);
 	}
 
 	/* prepare ram for reclocking */
-	nv_wr32(fb, 0x1002d4, 0x00000001); /* precharge */
-	nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */
-	nv_wr32(fb, 0x1002d0, 0x00000001); /* refresh */
-	nv_mask(fb, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
-	nv_wr32(fb, 0x1002dc, 0x00000001); /* enable self-refresh */
+	nvkm_wr32(device, 0x1002d4, 0x00000001); /* precharge */
+	nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */
+	nvkm_wr32(device, 0x1002d0, 0x00000001); /* refresh */
+	nvkm_mask(device, 0x100210, 0x80000000, 0x00000000); /* no auto refresh */
+	nvkm_wr32(device, 0x1002dc, 0x00000001); /* enable self-refresh */
 
 	/* change the PLL of each memory partition */
-	nv_mask(fb, 0x00c040, 0x0000c000, 0x00000000);
-	switch (nv_device(fb)->chipset) {
+	nvkm_mask(device, 0x00c040, 0x0000c000, 0x00000000);
+	switch (device->chipset) {
 	case 0x40:
 	case 0x45:
 	case 0x41:
 	case 0x42:
 	case 0x47:
-		nv_mask(fb, 0x004044, 0xc0771100, ram->ctrl);
-		nv_mask(fb, 0x00402c, 0xc0771100, ram->ctrl);
-		nv_wr32(fb, 0x004048, ram->coef);
-		nv_wr32(fb, 0x004030, ram->coef);
+		nvkm_mask(device, 0x004044, 0xc0771100, ram->ctrl);
+		nvkm_mask(device, 0x00402c, 0xc0771100, ram->ctrl);
+		nvkm_wr32(device, 0x004048, ram->coef);
+		nvkm_wr32(device, 0x004030, ram->coef);
 	case 0x43:
 	case 0x49:
 	case 0x4b:
-		nv_mask(fb, 0x004038, 0xc0771100, ram->ctrl);
-		nv_wr32(fb, 0x00403c, ram->coef);
+		nvkm_mask(device, 0x004038, 0xc0771100, ram->ctrl);
+		nvkm_wr32(device, 0x00403c, ram->coef);
 	default:
-		nv_mask(fb, 0x004020, 0xc0771100, ram->ctrl);
-		nv_wr32(fb, 0x004024, ram->coef);
+		nvkm_mask(device, 0x004020, 0xc0771100, ram->ctrl);
+		nvkm_wr32(device, 0x004024, ram->coef);
 		break;
 	}
 	udelay(100);
-	nv_mask(fb, 0x00c040, 0x0000c000, 0x0000c000);
+	nvkm_mask(device, 0x00c040, 0x0000c000, 0x0000c000);
 
 	/* re-enable normal operation of memory controller */
-	nv_wr32(fb, 0x1002dc, 0x00000000);
-	nv_mask(fb, 0x100210, 0x80000000, 0x80000000);
+	nvkm_wr32(device, 0x1002dc, 0x00000000);
+	nvkm_mask(device, 0x100210, 0x80000000, 0x80000000);
 	udelay(100);
 
 	/* execute memory reset script from vbios */
@@ -155,8 +156,8 @@ nv40_ram_prog(struct nvkm_fb *fb)
 		if (!(crtc_mask & (1 << i)))
 			continue;
 		nv_wait(fb, 0x600808 + (i * 0x2000), 0x00010000, 0x00010000);
-		nv_wr08(fb, 0x0c03c4 + (i * 0x2000), 0x01);
-		nv_wr08(fb, 0x0c03c5 + (i * 0x2000), sr1[i]);
+		nvkm_wr08(device, 0x0c03c4 + (i * 0x2000), 0x01);
+		nvkm_wr08(device, 0x0c03c5 + (i * 0x2000), sr1[i]);
 	}
 
 	return 0;
@@ -174,7 +175,8 @@ nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 pbus1218 = nv_rd32(fb, 0x001218);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 pbus1218 = nvkm_rd32(device, 0x001218);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -189,9 +191,9 @@ nv40_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	case 0x00000300: ram->base.type = NV_MEM_TYPE_DDR2; break;
 	}
 
-	ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(fb, 0x100320);
+	ram->base.size  =  nvkm_rd32(device, 0x10020c) & 0xff000000;
+	ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;
+	ram->base.tags  =  nvkm_rd32(device, 0x100320);
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.c

@@ -30,7 +30,8 @@ nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 fb474 = nv_rd32(fb, 0x100474);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 fb474 = nvkm_rd32(device, 0x100474);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -45,9 +46,9 @@ nv41_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (fb474 & 0x00000001)
 		ram->base.type = NV_MEM_TYPE_DDR1;
 
-	ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(fb, 0x100320);
+	ram->base.size  =  nvkm_rd32(device, 0x10020c) & 0xff000000;
+	ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;
+	ram->base.tags  =  nvkm_rd32(device, 0x100320);
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.c

@@ -30,7 +30,8 @@ nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 fb474 = nv_rd32(fb, 0x100474);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 fb474 = nvkm_rd32(device, 0x100474);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -45,7 +46,7 @@ nv44_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (fb474 & 0x00000001)
 		ram->base.type = NV_MEM_TYPE_DDR1;
 
-	ram->base.size = nv_rd32(fb, 0x10020c) & 0xff000000;
+	ram->base.size = nvkm_rd32(device, 0x10020c) & 0xff000000;
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.c

@@ -30,7 +30,8 @@ nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nv40_ram *ram;
-	u32 fb914 = nv_rd32(fb, 0x100914);
+	struct nvkm_device *device = fb->subdev.device;
+	u32 fb914 = nvkm_rd32(device, 0x100914);
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -45,9 +46,9 @@ nv49_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	case 0x00000003: break;
 	}
 
-	ram->base.size  =  nv_rd32(fb, 0x10020c) & 0xff000000;
-	ram->base.parts = (nv_rd32(fb, 0x100200) & 0x00000003) + 1;
-	ram->base.tags  =  nv_rd32(fb, 0x100320);
+	ram->base.size  =  nvkm_rd32(device, 0x10020c) & 0xff000000;
+	ram->base.parts = (nvkm_rd32(device, 0x100200) & 0x00000003) + 1;
+	ram->base.tags  =  nvkm_rd32(device, 0x100320);
 	ram->base.calc = nv40_ram_calc;
 	ram->base.prog = nv40_ram_prog;
 	ram->base.tidy = nv40_ram_tidy;

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.c

@@ -30,6 +30,7 @@ nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	struct nvkm_fb *fb = nvkm_fb(parent);
 	struct nvkm_ram *ram;
+	struct nvkm_device *device = fb->subdev.device;
 	int ret;
 
 	ret = nvkm_ram_create(parent, engine, oclass, &ram);
@@ -37,7 +38,7 @@ nv4e_ram_create(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	ram->size = nv_rd32(fb, 0x10020c) & 0xff000000;
+	ram->size = nvkm_rd32(device, 0x10020c) & 0xff000000;
 	ram->type = NV_MEM_TYPE_STOLEN;
 	return 0;
 }

drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.c

@@ -68,15 +68,16 @@ struct nv50_ram {
 static int
 nv50_ram_timing_calc(struct nvkm_fb *fb, u32 *timing)
 {
+	struct nvkm_device *device = fb->subdev.device;
 	struct nv50_ram *ram = (void *)fb->ram;
 	struct nvbios_ramcfg *cfg = &ram->base.target.bios;
 	u32 cur2, cur4, cur7, cur8;
 	u8 unkt3b;
 
-	cur2 = nv_rd32(fb, 0x100228);
-	cur4 = nv_rd32(fb, 0x100230);
-	cur7 = nv_rd32(fb, 0x10023c);
-	cur8 = nv_rd32(fb, 0x100240);
+	cur2 = nvkm_rd32(device, 0x100228);
+	cur4 = nvkm_rd32(device, 0x100230);
+	cur7 = nvkm_rd32(device, 0x10023c);
+	cur8 = nvkm_rd32(device, 0x100240);
 
 	switch ((!T(CWL)) * ram->base.type) {
 	case NV_MEM_TYPE_DDR2:
@@ -493,15 +494,16 @@ nv50_ram_get(struct nvkm_fb *fb, u64 size, u32 align, u32 ncmin,
 static u32
 nv50_fb_vram_rblock(struct nvkm_fb *fb, struct nvkm_ram *ram)
 {
+	struct nvkm_device *device = fb->subdev.device;
 	int colbits, rowbitsa, rowbitsb, banks;
 	u64 rowsize, predicted;
 	u32 r0, r4, rt, rblock_size;
 
-	r0 = nv_rd32(fb, 0x100200);
-	r4 = nv_rd32(fb, 0x100204);
-	rt = nv_rd32(fb, 0x100250);
+	r0 = nvkm_rd32(device, 0x100200);
+	r4 = nvkm_rd32(device, 0x100204);
+	rt = nvkm_rd32(device, 0x100250);
 	nv_debug(fb, "memcfg 0x%08x 0x%08x 0x%08x 0x%08x\n",
-		 r0, r4, rt, nv_rd32(fb, 0x001540));
+		 r0, r4, rt, nvkm_rd32(device, 0x001540));
 
 	colbits  =  (r4 & 0x0000f000) >> 12;
 	rowbitsa = ((r4 & 0x000f0000) >> 16) + 8;
@@ -532,8 +534,9 @@ nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 {
 	const u32 rsvd_head = ( 256 * 1024) >> 12; /* vga memory */
 	const u32 rsvd_tail = (1024 * 1024) >> 12; /* vbios etc */
-	struct nvkm_bios *bios = nvkm_bios(parent);
 	struct nvkm_fb *fb = nvkm_fb(parent);
+	struct nvkm_device *device = fb->subdev.device;
+	struct nvkm_bios *bios = device->bios;
 	struct nvkm_ram *ram;
 	int ret;
 
@@ -542,13 +545,13 @@ nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	ram->size = nv_rd32(fb, 0x10020c);
+	ram->size = nvkm_rd32(device, 0x10020c);
 	ram->size = (ram->size & 0xffffff00) | ((ram->size & 0x000000ff) << 32);
 
-	ram->part_mask = (nv_rd32(fb, 0x001540) & 0x00ff0000) >> 16;
+	ram->part_mask = (nvkm_rd32(device, 0x001540) & 0x00ff0000) >> 16;
 	ram->parts = hweight8(ram->part_mask);
 
-	switch (nv_rd32(fb, 0x100714) & 0x00000007) {
+	switch (nvkm_rd32(device, 0x100714) & 0x00000007) {
 	case 0: ram->type = NV_MEM_TYPE_DDR1; break;
 	case 1:
 		if (nvkm_fb_bios_memtype(bios) == NV_MEM_TYPE_DDR3)
@@ -569,8 +572,8 @@ nv50_ram_create_(struct nvkm_object *parent, struct nvkm_object *engine,
 	if (ret)
 		return ret;
 
-	ram->ranks = (nv_rd32(fb, 0x100200) & 0x4) ? 2 : 1;
-	ram->tags  =  nv_rd32(fb, 0x100320);
+	ram->ranks = (nvkm_rd32(device, 0x100200) & 0x4) ? 2 : 1;
+	ram->tags  =  nvkm_rd32(device, 0x100320);
 	ram->get = nv50_ram_get;
 	ram->put = nv50_ram_put;
 	return 0;