Commit 6845664a authored by Thomas Gleixner's avatar Thomas Gleixner

arm: Cleanup the irq namespace

Convert to the new function names. Automated with coccinelle.
Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 25a5662a
...@@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on) ...@@ -213,8 +213,8 @@ static int gic_set_wake(struct irq_data *d, unsigned int on)
static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{ {
struct gic_chip_data *chip_data = get_irq_data(irq); struct gic_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = get_irq_chip(irq); struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, gic_irq; unsigned int cascade_irq, gic_irq;
unsigned long status; unsigned long status;
...@@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) ...@@ -257,9 +257,9 @@ void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
{ {
if (gic_nr >= MAX_GIC_NR) if (gic_nr >= MAX_GIC_NR)
BUG(); BUG();
if (set_irq_data(irq, &gic_data[gic_nr]) != 0) if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
BUG(); BUG();
set_irq_chained_handler(irq, gic_handle_cascade_irq); irq_set_chained_handler(irq, gic_handle_cascade_irq);
} }
static void __init gic_dist_init(struct gic_chip_data *gic, static void __init gic_dist_init(struct gic_chip_data *gic,
...@@ -319,9 +319,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic, ...@@ -319,9 +319,9 @@ static void __init gic_dist_init(struct gic_chip_data *gic,
* Setup the Linux IRQ subsystem. * Setup the Linux IRQ subsystem.
*/ */
for (i = irq_start; i < irq_limit; i++) { for (i = irq_start; i < irq_limit; i++) {
set_irq_chip(i, &gic_chip); irq_set_chip(i, &gic_chip);
set_irq_chip_data(i, gic); irq_set_chip_data(i, gic);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
......
...@@ -88,8 +88,8 @@ void it8152_init_irq(void) ...@@ -88,8 +88,8 @@ void it8152_init_irq(void)
__raw_writel((0), IT8152_INTC_LDCNIRR); __raw_writel((0), IT8152_INTC_LDCNIRR);
for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) { for (irq = IT8152_IRQ(0); irq <= IT8152_LAST_IRQ; irq++) {
set_irq_chip(irq, &it8152_irq_chip); irq_set_chip(irq, &it8152_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
} }
......
...@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = { ...@@ -140,7 +140,7 @@ static struct locomo_dev_info locomo_devices[] = {
static void locomo_handler(unsigned int irq, struct irq_desc *desc) static void locomo_handler(unsigned int irq, struct irq_desc *desc)
{ {
struct locomo *lchip = get_irq_chip_data(irq); struct locomo *lchip = irq_get_chip_data(irq);
int req, i; int req, i;
/* Acknowledge the parent IRQ */ /* Acknowledge the parent IRQ */
...@@ -197,15 +197,15 @@ static void locomo_setup_irq(struct locomo *lchip) ...@@ -197,15 +197,15 @@ static void locomo_setup_irq(struct locomo *lchip)
/* /*
* Install handler for IRQ_LOCOMO_HW. * Install handler for IRQ_LOCOMO_HW.
*/ */
set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(lchip->irq, IRQ_TYPE_EDGE_FALLING);
set_irq_chip_data(lchip->irq, lchip); irq_set_chip_data(lchip->irq, lchip);
set_irq_chained_handler(lchip->irq, locomo_handler); irq_set_chained_handler(lchip->irq, locomo_handler);
/* Install handlers for IRQ_LOCOMO_* */ /* Install handlers for IRQ_LOCOMO_* */
for ( ; irq <= lchip->irq_base + 3; irq++) { for ( ; irq <= lchip->irq_base + 3; irq++) {
set_irq_chip(irq, &locomo_chip); irq_set_chip(irq, &locomo_chip);
set_irq_chip_data(irq, lchip); irq_set_chip_data(irq, lchip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
} }
...@@ -476,8 +476,8 @@ static void __locomo_remove(struct locomo *lchip) ...@@ -476,8 +476,8 @@ static void __locomo_remove(struct locomo *lchip)
device_for_each_child(lchip->dev, NULL, locomo_remove_child); device_for_each_child(lchip->dev, NULL, locomo_remove_child);
if (lchip->irq != NO_IRQ) { if (lchip->irq != NO_IRQ) {
set_irq_chained_handler(lchip->irq, NULL); irq_set_chained_handler(lchip->irq, NULL);
set_irq_data(lchip->irq, NULL); irq_set_handler_data(lchip->irq, NULL);
} }
iounmap(lchip->base); iounmap(lchip->base);
......
...@@ -202,7 +202,7 @@ static void ...@@ -202,7 +202,7 @@ static void
sa1111_irq_handler(unsigned int irq, struct irq_desc *desc) sa1111_irq_handler(unsigned int irq, struct irq_desc *desc)
{ {
unsigned int stat0, stat1, i; unsigned int stat0, stat1, i;
struct sa1111 *sachip = get_irq_data(irq); struct sa1111 *sachip = irq_get_handler_data(irq);
void __iomem *mapbase = sachip->base + SA1111_INTC; void __iomem *mapbase = sachip->base + SA1111_INTC;
stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0); stat0 = sa1111_readl(mapbase + SA1111_INTSTATCLR0);
...@@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip) ...@@ -472,25 +472,25 @@ static void sa1111_setup_irq(struct sa1111 *sachip)
sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1); sa1111_writel(~0, irqbase + SA1111_INTSTATCLR1);
for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) { for (irq = IRQ_GPAIN0; irq <= SSPROR; irq++) {
set_irq_chip(irq, &sa1111_low_chip); irq_set_chip(irq, &sa1111_low_chip);
set_irq_chip_data(irq, sachip); irq_set_chip_data(irq, sachip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) { for (irq = AUDXMTDMADONEA; irq <= IRQ_S1_BVD1_STSCHG; irq++) {
set_irq_chip(irq, &sa1111_high_chip); irq_set_chip(irq, &sa1111_high_chip);
set_irq_chip_data(irq, sachip); irq_set_chip_data(irq, sachip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
/* /*
* Register SA1111 interrupt * Register SA1111 interrupt
*/ */
set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING); irq_set_irq_type(sachip->irq, IRQ_TYPE_EDGE_RISING);
set_irq_data(sachip->irq, sachip); irq_set_handler_data(sachip->irq, sachip);
set_irq_chained_handler(sachip->irq, sa1111_irq_handler); irq_set_chained_handler(sachip->irq, sa1111_irq_handler);
} }
/* /*
...@@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip) ...@@ -815,8 +815,8 @@ static void __sa1111_remove(struct sa1111 *sachip)
clk_disable(sachip->clk); clk_disable(sachip->clk);
if (sachip->irq != NO_IRQ) { if (sachip->irq != NO_IRQ) {
set_irq_chained_handler(sachip->irq, NULL); irq_set_chained_handler(sachip->irq, NULL);
set_irq_data(sachip->irq, NULL); irq_set_handler_data(sachip->irq, NULL);
release_mem_region(sachip->phys + SA1111_INTC, 512); release_mem_region(sachip->phys + SA1111_INTC, 512);
} }
......
...@@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base, ...@@ -305,9 +305,9 @@ static void __init vic_set_irq_sources(void __iomem *base,
if (vic_sources & (1 << i)) { if (vic_sources & (1 << i)) {
unsigned int irq = irq_start + i; unsigned int irq = irq_start + i;
set_irq_chip(irq, &vic_chip); irq_set_chip(irq, &vic_chip);
set_irq_chip_data(irq, base); irq_set_chip_data(irq, base);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
} }
......
...@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type) ...@@ -1043,8 +1043,8 @@ ecard_probe(int slot, card_type_t type)
*/ */
if (slot < 8) { if (slot < 8) {
ec->irq = 32 + slot; ec->irq = 32 + slot;
set_irq_chip(ec->irq, &ecard_chip); irq_set_chip(ec->irq, &ecard_chip);
set_irq_handler(ec->irq, handle_level_irq); irq_set_handler(ec->irq, handle_level_irq);
set_irq_flags(ec->irq, IRQF_VALID); set_irq_flags(ec->irq, IRQF_VALID);
} }
...@@ -1103,7 +1103,7 @@ static int __init ecard_init(void) ...@@ -1103,7 +1103,7 @@ static int __init ecard_init(void)
irqhw = ecard_probeirqhw(); irqhw = ecard_probeirqhw();
set_irq_chained_handler(IRQ_EXPANSIONCARD, irq_set_chained_handler(IRQ_EXPANSIONCARD,
irqhw ? ecard_irqexp_handler : ecard_irq_handler); irqhw ? ecard_irqexp_handler : ecard_irq_handler);
ecard_proc_init(); ecard_proc_init();
......
...@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data) ...@@ -72,7 +72,7 @@ void __init at91_add_device_usbh(struct at91_usbh_data *data)
return; return;
if (cpu_is_at91cap9_revB()) if (cpu_is_at91cap9_revB())
set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH); irq_set_irq_type(AT91CAP9_ID_UHP, IRQ_TYPE_LEVEL_HIGH);
/* Enable VBus control for UHP ports */ /* Enable VBus control for UHP ports */
for (i = 0; i < data->ports; i++) { for (i = 0; i < data->ports; i++) {
...@@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = { ...@@ -157,7 +157,7 @@ static struct platform_device at91_usba_udc_device = {
void __init at91_add_device_usba(struct usba_platform_data *data) void __init at91_add_device_usba(struct usba_platform_data *data)
{ {
if (cpu_is_at91cap9_revB()) { if (cpu_is_at91cap9_revB()) {
set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH); irq_set_irq_type(AT91CAP9_ID_UDPHS, IRQ_TYPE_LEVEL_HIGH);
at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS | at91_sys_write(AT91_MATRIX_UDPHS, AT91_MATRIX_SELECT_UDPHS |
AT91_MATRIX_UDPHS_BYPASS_LOCK); AT91_MATRIX_UDPHS_BYPASS_LOCK);
} }
...@@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) ...@@ -861,7 +861,7 @@ void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data)
return; return;
if (cpu_is_at91cap9_revB()) if (cpu_is_at91cap9_revB())
set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH); irq_set_irq_type(AT91CAP9_ID_LCDC, IRQ_TYPE_LEVEL_HIGH);
at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PC1, 0); /* LCDHSYNC */
at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PC2, 0); /* LCDDOTCK */
......
...@@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state) ...@@ -287,7 +287,7 @@ static int gpio_irq_set_wake(struct irq_data *d, unsigned state)
else else
wakeups[bank] &= ~mask; wakeups[bank] &= ~mask;
set_irq_wake(gpio_chip[bank].bank->id, state); irq_set_irq_wake(gpio_chip[bank].bank->id, state);
return 0; return 0;
} }
...@@ -511,8 +511,8 @@ void __init at91_gpio_irq_setup(void) ...@@ -511,8 +511,8 @@ void __init at91_gpio_irq_setup(void)
* Can use the "simple" and not "edge" handler since it's * Can use the "simple" and not "edge" handler since it's
* shorter, and the AIC handles interrupts sanely. * shorter, and the AIC handles interrupts sanely.
*/ */
set_irq_chip(pin, &gpio_irqchip); irq_set_chip(pin, &gpio_irqchip);
set_irq_handler(pin, handle_simple_irq); irq_set_handler(pin, handle_simple_irq);
set_irq_flags(pin, IRQF_VALID); set_irq_flags(pin, IRQF_VALID);
} }
...@@ -523,8 +523,8 @@ void __init at91_gpio_irq_setup(void) ...@@ -523,8 +523,8 @@ void __init at91_gpio_irq_setup(void)
if (prev && prev->next == this) if (prev && prev->next == this)
continue; continue;
set_irq_chip_data(id, this); irq_set_chip_data(id, this);
set_irq_chained_handler(id, gpio_irq_handler); irq_set_chained_handler(id, gpio_irq_handler);
} }
pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks); pr_info("AT91: %d gpio irqs in %d banks\n", pin - PIN_BASE, gpio_banks);
} }
......
...@@ -143,8 +143,8 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS]) ...@@ -143,8 +143,8 @@ void __init at91_aic_init(unsigned int priority[NR_AIC_IRQS])
/* Active Low interrupt, with the specified priority */ /* Active Low interrupt, with the specified priority */
at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]); at91_sys_write(AT91_AIC_SMR(i), AT91_AIC_SRCTYPE_LOW | priority[i]);
set_irq_chip(i, &at91_aic_chip); irq_set_chip(i, &at91_aic_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
/* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */ /* Perform 8 End Of Interrupt Command to make sure AIC will not Lock out nIRQ */
......
...@@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip, ...@@ -93,11 +93,11 @@ static void vic_init(void __iomem *base, struct irq_chip *chip,
unsigned int i; unsigned int i;
for (i = 0; i < 32; i++) { for (i = 0; i < 32; i++) {
unsigned int irq = irq_start + i; unsigned int irq = irq_start + i;
set_irq_chip(irq, chip); irq_set_chip(irq, chip);
set_irq_chip_data(irq, base); irq_set_chip_data(irq, base);
if (vic_sources & (1 << i)) { if (vic_sources & (1 << i)) {
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
} }
...@@ -119,9 +119,9 @@ void __init bcmring_init_irq(void) ...@@ -119,9 +119,9 @@ void __init bcmring_init_irq(void)
/* special cases */ /* special cases */
if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) { if (INTCHW_INTC1_GPIO0 & IRQ_INTC1_VALID_MASK) {
set_irq_handler(IRQ_GPIO0, handle_simple_irq); irq_set_handler(IRQ_GPIO0, handle_simple_irq);
} }
if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) { if (INTCHW_INTC1_GPIO1 & IRQ_INTC1_VALID_MASK) {
set_irq_handler(IRQ_GPIO1, handle_simple_irq); irq_set_handler(IRQ_GPIO1, handle_simple_irq);
} }
} }
...@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void) ...@@ -112,13 +112,13 @@ void __init clps711x_init_irq(void)
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
if (INT1_IRQS & (1 << i)) { if (INT1_IRQS & (1 << i)) {
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_chip(i, &int1_chip); irq_set_chip(i, &int1_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
if (INT2_IRQS & (1 << i)) { if (INT2_IRQS & (1 << i)) {
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_chip(i, &int2_chip); irq_set_chip(i, &int2_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
} }
......
...@@ -167,9 +167,9 @@ void __init cp_intc_init(void) ...@@ -167,9 +167,9 @@ void __init cp_intc_init(void)
/* Set up genirq dispatching for cp_intc */ /* Set up genirq dispatching for cp_intc */
for (i = 0; i < num_irq; i++) { for (i = 0; i < num_irq; i++) {
set_irq_chip(i, &cp_intc_irq_chip); irq_set_chip(i, &cp_intc_irq_chip);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
} }
/* Enable global interrupt */ /* Enable global interrupt */
......
...@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq) ...@@ -62,7 +62,7 @@ static inline struct davinci_gpio_regs __iomem *irq2regs(int irq)
{ {
struct davinci_gpio_regs __iomem *g; struct davinci_gpio_regs __iomem *g;
g = (__force struct davinci_gpio_regs __iomem *)get_irq_chip_data(irq); g = (__force struct davinci_gpio_regs __iomem *)irq_get_chip_data(irq);
return g; return g;
} }
...@@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup); ...@@ -208,7 +208,7 @@ pure_initcall(davinci_gpio_setup);
static void gpio_irq_disable(struct irq_data *d) static void gpio_irq_disable(struct irq_data *d)
{ {
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d); u32 mask = (u32) irq_data_get_irq_handler_data(d);
__raw_writel(mask, &g->clr_falling); __raw_writel(mask, &g->clr_falling);
__raw_writel(mask, &g->clr_rising); __raw_writel(mask, &g->clr_rising);
...@@ -217,7 +217,7 @@ static void gpio_irq_disable(struct irq_data *d) ...@@ -217,7 +217,7 @@ static void gpio_irq_disable(struct irq_data *d)
static void gpio_irq_enable(struct irq_data *d) static void gpio_irq_enable(struct irq_data *d)
{ {
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d); u32 mask = (u32) irq_data_get_irq_handler_data(d);
unsigned status = irqd_get_trigger_type(d); unsigned status = irqd_get_trigger_type(d);
status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING; status &= IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING;
...@@ -233,7 +233,7 @@ static void gpio_irq_enable(struct irq_data *d) ...@@ -233,7 +233,7 @@ static void gpio_irq_enable(struct irq_data *d)
static int gpio_irq_type(struct irq_data *d, unsigned trigger) static int gpio_irq_type(struct irq_data *d, unsigned trigger)
{ {
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d); u32 mask = (u32) irq_data_get_irq_handler_data(d);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL; return -EINVAL;
...@@ -276,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc) ...@@ -276,7 +276,7 @@ gpio_irq_handler(unsigned irq, struct irq_desc *desc)
status >>= 16; status >>= 16;
/* now demux them to the right lowlevel handler */ /* now demux them to the right lowlevel handler */
n = (int)get_irq_data(irq); n = (int)irq_get_handler_data(irq);
while (status) { while (status) {
res = ffs(status); res = ffs(status);
n += res; n += res;
...@@ -314,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset) ...@@ -314,7 +314,7 @@ static int gpio_to_irq_unbanked(struct gpio_chip *chip, unsigned offset)
static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger) static int gpio_irq_type_unbanked(struct irq_data *d, unsigned trigger)
{ {
struct davinci_gpio_regs __iomem *g = irq2regs(d->irq); struct davinci_gpio_regs __iomem *g = irq2regs(d->irq);
u32 mask = (u32) irq_data_get_irq_data(d); u32 mask = (u32) irq_data_get_irq_handler_data(d);
if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) if (trigger & ~(IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
return -EINVAL; return -EINVAL;
...@@ -397,9 +397,9 @@ static int __init davinci_gpio_irq_setup(void) ...@@ -397,9 +397,9 @@ static int __init davinci_gpio_irq_setup(void)
/* set the direct IRQs up to use that irqchip */ /* set the direct IRQs up to use that irqchip */
for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) { for (gpio = 0; gpio < soc_info->gpio_unbanked; gpio++, irq++) {
set_irq_chip(irq, &gpio_irqchip_unbanked); irq_set_chip(irq, &gpio_irqchip_unbanked);
set_irq_data(irq, (void *) __gpio_mask(gpio)); irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
set_irq_chip_data(irq, (__force void *) g); irq_set_chip_data(irq, (__force void *)g);
irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH); irq_set_status_flags(irq, IRQ_TYPE_EDGE_BOTH);
} }
...@@ -421,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void) ...@@ -421,15 +421,15 @@ static int __init davinci_gpio_irq_setup(void)
__raw_writel(~0, &g->clr_rising); __raw_writel(~0, &g->clr_rising);
/* set up all irqs in this bank */ /* set up all irqs in this bank */
set_irq_chained_handler(bank_irq, gpio_irq_handler); irq_set_chained_handler(bank_irq, gpio_irq_handler);
set_irq_chip_data(bank_irq, (__force void *) g); irq_set_chip_data(bank_irq, (__force void *)g);
set_irq_data(bank_irq, (void *) irq); irq_set_handler_data(bank_irq, (void *)irq);
for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) { for (i = 0; i < 16 && gpio < ngpio; i++, irq++, gpio++) {
set_irq_chip(irq, &gpio_irqchip); irq_set_chip(irq, &gpio_irqchip);
set_irq_chip_data(irq, (__force void *) g); irq_set_chip_data(irq, (__force void *)g);
set_irq_data(irq, (void *) __gpio_mask(gpio)); irq_set_handler_data(irq, (void *)__gpio_mask(gpio));
set_irq_handler(irq, handle_simple_irq); irq_set_handler(irq, handle_simple_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
......
...@@ -154,11 +154,11 @@ void __init davinci_irq_init(void) ...@@ -154,11 +154,11 @@ void __init davinci_irq_init(void)
/* set up genirq dispatch for ARM INTC */ /* set up genirq dispatch for ARM INTC */
for (i = 0; i < davinci_soc_info.intc_irq_num; i++) { for (i = 0; i < davinci_soc_info.intc_irq_num; i++) {
set_irq_chip(i, &davinci_irq_chip_0); irq_set_chip(i, &davinci_irq_chip_0);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
if (i != IRQ_TINT1_TINT34) if (i != IRQ_TINT1_TINT34)
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
else else
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
} }
} }
...@@ -102,14 +102,14 @@ void __init dove_init_irq(void) ...@@ -102,14 +102,14 @@ void __init dove_init_irq(void)
*/ */
orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0, orion_gpio_init(0, 32, DOVE_GPIO_LO_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START); IRQ_DOVE_GPIO_START);
set_irq_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_GPIO_24_31, gpio_irq_handler);
orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0, orion_gpio_init(32, 32, DOVE_GPIO_HI_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 32); IRQ_DOVE_GPIO_START + 32);
set_irq_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler); irq_set_chained_handler(IRQ_DOVE_HIGH_GPIO, gpio_irq_handler);
orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0, orion_gpio_init(64, 8, DOVE_GPIO2_VIRT_BASE, 0,
IRQ_DOVE_GPIO_START + 64); IRQ_DOVE_GPIO_START + 64);
...@@ -121,10 +121,10 @@ void __init dove_init_irq(void) ...@@ -121,10 +121,10 @@ void __init dove_init_irq(void)
writel(0, PMU_INTERRUPT_CAUSE); writel(0, PMU_INTERRUPT_CAUSE);
for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) { for (i = IRQ_DOVE_PMU_START; i < NR_IRQS; i++) {
set_irq_chip(i, &pmu_irq_chip); irq_set_chip(i, &pmu_irq_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
irq_set_status_flags(i, IRQ_LEVEL); irq_set_status_flags(i, IRQ_LEVEL);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
set_irq_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler); irq_set_chained_handler(IRQ_DOVE_PMU, pmu_irq_handler);
} }
...@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void) ...@@ -66,8 +66,8 @@ static void __init ebsa110_init_irq(void)
local_irq_restore(flags); local_irq_restore(flags);
for (irq = 0; irq < NR_IRQS; irq++) { for (irq = 0; irq < NR_IRQS; irq++) {
set_irq_chip(irq, &ebsa110_irq_chip); irq_set_chip(irq, &ebsa110_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
} }
......
...@@ -231,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void) ...@@ -231,20 +231,29 @@ void __init ep93xx_gpio_init_irq(void)
for (gpio_irq = gpio_to_irq(0); for (gpio_irq = gpio_to_irq(0);
gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) { gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip); irq_set_chip(gpio_irq, &ep93xx_gpio_irq_chip);
set_irq_handler(gpio_irq, handle_level_irq); irq_set_handler(gpio_irq, handle_level_irq);
set_irq_flags(gpio_irq, IRQF_VALID); set_irq_flags(gpio_irq, IRQF_VALID);
} }
set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler); irq_set_chained_handler(IRQ_EP93XX_GPIO_AB,
set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler); ep93xx_gpio_ab_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler); irq_set_chained_handler(IRQ_EP93XX_GPIO0MUX,
set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler); ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler); irq_set_chained_handler(IRQ_EP93XX_GPIO1MUX,
set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler); ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler); irq_set_chained_handler(IRQ_EP93XX_GPIO2MUX,
set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler); ep93xx_gpio_f_irq_handler);
set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler); irq_set_chained_handler(IRQ_EP93XX_GPIO3MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO4MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO5MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO6MUX,
ep93xx_gpio_f_irq_handler);
irq_set_chained_handler(IRQ_EP93XX_GPIO7MUX,
ep93xx_gpio_f_irq_handler);
} }
......
...@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data) ...@@ -54,8 +54,8 @@ static void combiner_unmask_irq(struct irq_data *data)
static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) static void combiner_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
{ {
struct combiner_chip_data *chip_data = get_irq_data(irq); struct combiner_chip_data *chip_data = irq_get_handler_data(irq);
struct irq_chip *chip = get_irq_chip(irq); struct irq_chip *chip = irq_get_chip(irq);
unsigned int cascade_irq, combiner_irq; unsigned int cascade_irq, combiner_irq;
unsigned long status; unsigned long status;
...@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq) ...@@ -93,9 +93,9 @@ void __init combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq)
{ {
if (combiner_nr >= MAX_COMBINER_NR) if (combiner_nr >= MAX_COMBINER_NR)
BUG(); BUG();
if (set_irq_data(irq, &combiner_data[combiner_nr]) != 0) if (irq_set_handler_data(irq, &combiner_data[combiner_nr]) != 0)
BUG(); BUG();
set_irq_chained_handler(irq, combiner_handle_cascade_irq); irq_set_chained_handler(irq, combiner_handle_cascade_irq);
} }
void __init combiner_init(unsigned int combiner_nr, void __iomem *base, void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
...@@ -119,9 +119,9 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base, ...@@ -119,9 +119,9 @@ void __init combiner_init(unsigned int combiner_nr, void __iomem *base,
for (i = irq_start; i < combiner_data[combiner_nr].irq_offset for (i = irq_start; i < combiner_data[combiner_nr].irq_offset
+ MAX_IRQ_IN_COMBINER; i++) { + MAX_IRQ_IN_COMBINER; i++) {
set_irq_chip(i, &combiner_chip); irq_set_chip(i, &combiner_chip);
set_irq_chip_data(i, &combiner_data[combiner_nr]); irq_set_chip_data(i, &combiner_data[combiner_nr]);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
} }
...@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc) ...@@ -190,8 +190,8 @@ static void exynos4_irq_demux_eint16_31(unsigned int irq, struct irq_desc *desc)
static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc) static void exynos4_irq_eint0_15(unsigned int irq, struct irq_desc *desc)
{ {
u32 *irq_data = get_irq_data(irq); u32 *irq_data = irq_get_handler_data(irq);
struct irq_chip *chip = get_irq_chip(irq); struct irq_chip *chip = irq_get_chip(irq);
chip->irq_mask(&desc->irq_data); chip->irq_mask(&desc->irq_data);
...@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void) ...@@ -208,18 +208,19 @@ int __init exynos4_init_irq_eint(void)
int irq; int irq;
for (irq = 0 ; irq <= 31 ; irq++) { for (irq = 0 ; irq <= 31 ; irq++) {
set_irq_chip(IRQ_EINT(irq), &exynos4_irq_eint); irq_set_chip(IRQ_EINT(irq), &exynos4_irq_eint);
set_irq_handler(IRQ_EINT(irq), handle_level_irq); irq_set_handler(IRQ_EINT(irq), handle_level_irq);
set_irq_flags(IRQ_EINT(irq), IRQF_VALID); set_irq_flags(IRQ_EINT(irq), IRQF_VALID);
} }
set_irq_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31); irq_set_chained_handler(IRQ_EINT16_31, exynos4_irq_demux_eint16_31);
for (irq = 0 ; irq <= 15 ; irq++) { for (irq = 0 ; irq <= 15 ; irq++) {
eint0_15_data[irq] = IRQ_EINT(irq); eint0_15_data[irq] = IRQ_EINT(irq);
set_irq_data(exynos4_get_irq_nr(irq), &eint0_15_data[irq]); irq_set_handler_data(exynos4_get_irq_nr(irq),
set_irq_chained_handler(exynos4_get_irq_nr(irq), &eint0_15_data[irq]);
irq_set_chained_handler(exynos4_get_irq_nr(irq),
exynos4_irq_eint0_15); exynos4_irq_eint0_15);
} }
......
...@@ -102,8 +102,8 @@ static void __init __fb_init_irq(void) ...@@ -102,8 +102,8 @@ static void __init __fb_init_irq(void)
*CSR_FIQ_DISABLE = -1; *CSR_FIQ_DISABLE = -1;
for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) { for (irq = _DC21285_IRQ(0); irq < _DC21285_IRQ(20); irq++) {
set_irq_chip(irq, &fb_chip); irq_set_chip(irq, &fb_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
} }
......
...@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq) ...@@ -151,14 +151,14 @@ void __init isa_init_irq(unsigned int host_irq)
if (host_irq != (unsigned int)-1) { if (host_irq != (unsigned int)-1) {
for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) { for (irq = _ISA_IRQ(0); irq < _ISA_IRQ(8); irq++) {
set_irq_chip(irq, &isa_lo_chip); irq_set_chip(irq, &isa_lo_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) { for (irq = _ISA_IRQ(8); irq < _ISA_IRQ(16); irq++) {
set_irq_chip(irq, &isa_hi_chip); irq_set_chip(irq, &isa_hi_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
...@@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq) ...@@ -166,7 +166,7 @@ void __init isa_init_irq(unsigned int host_irq)
request_resource(&ioport_resource, &pic2_resource); request_resource(&ioport_resource, &pic2_resource);
setup_irq(IRQ_ISA_CASCADE, &irq_cascade); setup_irq(IRQ_ISA_CASCADE, &irq_cascade);
set_irq_chained_handler(host_irq, isa_irq_handler); irq_set_chained_handler(host_irq, isa_irq_handler);
/* /*
* On the NetWinder, don't automatically * On the NetWinder, don't automatically
......
...@@ -217,13 +217,13 @@ void __init gemini_gpio_init(void) ...@@ -217,13 +217,13 @@ void __init gemini_gpio_init(void)
for (j = GPIO_IRQ_BASE + i * 32; for (j = GPIO_IRQ_BASE + i * 32;
j < GPIO_IRQ_BASE + (i + 1) * 32; j++) { j < GPIO_IRQ_BASE + (i + 1) * 32; j++) {
set_irq_chip(j, &gpio_irq_chip); irq_set_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_edge_irq); irq_set_handler(j, handle_edge_irq);
set_irq_flags(j, IRQF_VALID); set_irq_flags(j, IRQF_VALID);
} }
set_irq_chained_handler(IRQ_GPIO(i), gpio_irq_handler); irq_set_chained_handler(IRQ_GPIO(i), gpio_irq_handler);
set_irq_data(IRQ_GPIO(i), (void *)i); irq_set_handler_data(IRQ_GPIO(i), (void *)i);
} }
BUG_ON(gpiochip_add(&gemini_gpio_chip)); BUG_ON(gpiochip_add(&gemini_gpio_chip));
......
...@@ -81,13 +81,13 @@ void __init gemini_init_irq(void) ...@@ -81,13 +81,13 @@ void __init gemini_init_irq(void)
request_resource(&iomem_resource, &irq_resource); request_resource(&iomem_resource, &irq_resource);
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &gemini_irq_chip); irq_set_chip(i, &gemini_irq_chip);
if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) { if((i >= IRQ_TIMER1 && i <= IRQ_TIMER3) || (i >= IRQ_SERIRQ0 && i <= IRQ_SERIRQ1)) {
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
mode |= 1 << i; mode |= 1 << i;
level |= 1 << i; level |= 1 << i;
} else { } else {
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
} }
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
......
...@@ -199,29 +199,29 @@ void __init h720x_init_irq (void) ...@@ -199,29 +199,29 @@ void __init h720x_init_irq (void)
/* Initialize global IRQ's, fast path */ /* Initialize global IRQ's, fast path */
for (irq = 0; irq < NR_GLBL_IRQS; irq++) { for (irq = 0; irq < NR_GLBL_IRQS; irq++) {
set_irq_chip(irq, &h720x_global_chip); irq_set_chip(irq, &h720x_global_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
/* Initialize multiplexed IRQ's, slow path */ /* Initialize multiplexed IRQ's, slow path */
for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) { for (irq = IRQ_CHAINED_GPIOA(0) ; irq <= IRQ_CHAINED_GPIOD(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip); irq_set_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID ); set_irq_flags(irq, IRQF_VALID );
} }
set_irq_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler); irq_set_chained_handler(IRQ_GPIOA, h720x_gpioa_demux_handler);
set_irq_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler); irq_set_chained_handler(IRQ_GPIOB, h720x_gpiob_demux_handler);
set_irq_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler); irq_set_chained_handler(IRQ_GPIOC, h720x_gpioc_demux_handler);
set_irq_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler); irq_set_chained_handler(IRQ_GPIOD, h720x_gpiod_demux_handler);
#ifdef CONFIG_CPU_H7202 #ifdef CONFIG_CPU_H7202
for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) { for (irq = IRQ_CHAINED_GPIOE(0) ; irq <= IRQ_CHAINED_GPIOE(31); irq++) {
set_irq_chip(irq, &h720x_gpio_chip); irq_set_chip(irq, &h720x_gpio_chip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID ); set_irq_flags(irq, IRQF_VALID );
} }
set_irq_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler); irq_set_chained_handler(IRQ_GPIOE, h720x_gpioe_demux_handler);
#endif #endif
/* Enable multiplexed irq's */ /* Enable multiplexed irq's */
......
...@@ -202,11 +202,11 @@ void __init h7202_init_irq (void) ...@@ -202,11 +202,11 @@ void __init h7202_init_irq (void)
for (irq = IRQ_TIMER1; for (irq = IRQ_TIMER1;
irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) { irq < IRQ_CHAINED_TIMERX(NR_TIMERX_IRQS); irq++) {
__mask_timerx_irq(irq); __mask_timerx_irq(irq);
set_irq_chip(irq, &h7202_timerx_chip); irq_set_chip(irq, &h7202_timerx_chip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID ); set_irq_flags(irq, IRQF_VALID );
} }
set_irq_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler); irq_set_chained_handler(IRQ_TIMERX, h7202_timerx_demux_handler);
h720x_init_irq(); h720x_init_irq();
} }
......
...@@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void) ...@@ -224,15 +224,15 @@ void __init iop13xx_init_irq(void)
for(i = 0; i <= IRQ_IOP13XX_HPI; i++) { for(i = 0; i <= IRQ_IOP13XX_HPI; i++) {
if (i < 32) if (i < 32)
set_irq_chip(i, &iop13xx_irqchip1); irq_set_chip(i, &iop13xx_irqchip1);
else if (i < 64) else if (i < 64)
set_irq_chip(i, &iop13xx_irqchip2); irq_set_chip(i, &iop13xx_irqchip2);
else if (i < 96) else if (i < 96)
set_irq_chip(i, &iop13xx_irqchip3); irq_set_chip(i, &iop13xx_irqchip3);
else else
set_irq_chip(i, &iop13xx_irqchip4); irq_set_chip(i, &iop13xx_irqchip4);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
......
...@@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc) ...@@ -118,7 +118,7 @@ static void iop13xx_msi_handler(unsigned int irq, struct irq_desc *desc)
void __init iop13xx_msi_init(void) void __init iop13xx_msi_init(void)
{ {
set_irq_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler); irq_set_chained_handler(IRQ_IOP13XX_INBD_MSI, iop13xx_msi_handler);
} }
/* /*
...@@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ...@@ -178,7 +178,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
if (irq < 0) if (irq < 0)
return irq; return irq;
set_irq_msi(irq, desc); irq_set_msi_desc(irq, desc);
msg.address_hi = 0x0; msg.address_hi = 0x0;
msg.address_lo = IOP13XX_MU_MIMR_PCI; msg.address_lo = IOP13XX_MU_MIMR_PCI;
...@@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc) ...@@ -187,7 +187,7 @@ int arch_setup_msi_irq(struct pci_dev *pdev, struct msi_desc *desc)
msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f); msg.data = (id << IOP13XX_MU_MIMR_CORE_SELECT) | (irq & 0x7f);
write_msi_msg(irq, &msg); write_msi_msg(irq, &msg);
set_irq_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq); irq_set_chip_and_handler(irq, &iop13xx_msi_chip, handle_simple_irq);
return 0; return 0;
} }
...@@ -68,8 +68,8 @@ void __init iop32x_init_irq(void) ...@@ -68,8 +68,8 @@ void __init iop32x_init_irq(void)
*IOP3XX_PCIIRSR = 0x0f; *IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ext_chip); irq_set_chip(i, &ext_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
} }
...@@ -110,8 +110,9 @@ void __init iop33x_init_irq(void) ...@@ -110,8 +110,9 @@ void __init iop33x_init_irq(void)
*IOP3XX_PCIIRSR = 0x0f; *IOP3XX_PCIIRSR = 0x0f;
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2); irq_set_chip(i,
set_irq_handler(i, handle_level_irq); (i < 32) ? &iop33x_irqchip1 : &iop33x_irqchip2);
irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE); set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
} }
} }
...@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void) ...@@ -476,8 +476,8 @@ void __init ixp2000_init_irq(void)
*/ */
for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) { for (irq = IRQ_IXP2000_SOFT_INT; irq <= IRQ_IXP2000_THDB3; irq++) {
if ((1 << irq) & IXP2000_VALID_IRQ_MASK) { if ((1 << irq) & IXP2000_VALID_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_irq_chip); irq_set_chip(irq, &ixp2000_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} else set_irq_flags(irq, 0); } else set_irq_flags(irq, 0);
} }
...@@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void) ...@@ -485,21 +485,21 @@ void __init ixp2000_init_irq(void)
for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) { for (irq = IRQ_IXP2000_DRAM0_MIN_ERR; irq <= IRQ_IXP2000_SP_INT; irq++) {
if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) & if((1 << (irq - IRQ_IXP2000_DRAM0_MIN_ERR)) &
IXP2000_VALID_ERR_IRQ_MASK) { IXP2000_VALID_ERR_IRQ_MASK) {
set_irq_chip(irq, &ixp2000_err_irq_chip); irq_set_chip(irq, &ixp2000_err_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
else else
set_irq_flags(irq, 0); set_irq_flags(irq, 0);
} }
set_irq_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler); irq_set_chained_handler(IRQ_IXP2000_ERRSUM, ixp2000_err_irq_handler);
for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) { for (irq = IRQ_IXP2000_GPIO0; irq <= IRQ_IXP2000_GPIO7; irq++) {
set_irq_chip(irq, &ixp2000_GPIO_irq_chip); irq_set_chip(irq, &ixp2000_GPIO_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
set_irq_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler); irq_set_chained_handler(IRQ_IXP2000_GPIO, ixp2000_GPIO_irq_handler);
/* /*
* Enable PCI irqs. The actual PCI[AB] decoding is done in * Enable PCI irqs. The actual PCI[AB] decoding is done in
...@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void) ...@@ -508,8 +508,8 @@ void __init ixp2000_init_irq(void)
*/ */
ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI)); ixp2000_reg_write(IXP2000_IRQ_ENABLE_SET, (1 << IRQ_IXP2000_PCI));
for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) { for (irq = IRQ_IXP2000_PCIA; irq <= IRQ_IXP2000_PCIB; irq++) {
set_irq_chip(irq, &ixp2000_pci_irq_chip); irq_set_chip(irq, &ixp2000_pci_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
} }
......
...@@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne ...@@ -158,13 +158,13 @@ void __init ixdp2x00_init_irq(volatile unsigned long *stat_reg, volatile unsigne
*board_irq_mask = 0xffffffff; *board_irq_mask = 0xffffffff;
for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) { for(irq = IXP2000_BOARD_IRQ(0); irq < IXP2000_BOARD_IRQ(board_irq_count); irq++) {
set_irq_chip(irq, &ixdp2x00_cpld_irq_chip); irq_set_chip(irq, &ixdp2x00_cpld_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
/* Hook into PCI interrupt */ /* Hook into PCI interrupt */
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler); irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x00_irq_handler);
} }
/************************************************************************* /*************************************************************************
......
...@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void) ...@@ -115,8 +115,8 @@ void __init ixdp2x01_init_irq(void)
for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) { for (irq = NR_IXP2000_IRQS; irq < NR_IXDP2X01_IRQS; irq++) {
if (irq & valid_irq_mask) { if (irq & valid_irq_mask) {
set_irq_chip(irq, &ixdp2x01_irq_chip); irq_set_chip(irq, &ixdp2x01_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} else { } else {
set_irq_flags(irq, 0); set_irq_flags(irq, 0);
...@@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void) ...@@ -124,7 +124,7 @@ void __init ixdp2x01_init_irq(void)
} }
/* Hook into PCI interrupts */ /* Hook into PCI interrupts */
set_irq_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler); irq_set_chained_handler(IRQ_IXP2000_PCIB, ixdp2x01_irq_handler);
} }
......
...@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type) ...@@ -289,12 +289,12 @@ static void ixp23xx_config_irq(unsigned int irq, enum ixp23xx_irq_type type)
{ {
switch (type) { switch (type) {
case IXP23XX_IRQ_LEVEL: case IXP23XX_IRQ_LEVEL:
set_irq_chip(irq, &ixp23xx_irq_level_chip); irq_set_chip(irq, &ixp23xx_irq_level_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
break; break;
case IXP23XX_IRQ_EDGE: case IXP23XX_IRQ_EDGE:
set_irq_chip(irq, &ixp23xx_irq_edge_chip); irq_set_chip(irq, &ixp23xx_irq_edge_chip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
break; break;
} }
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
...@@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void) ...@@ -324,12 +324,12 @@ void __init ixp23xx_init_irq(void)
} }
for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) { for (irq = IRQ_IXP23XX_INTA; irq <= IRQ_IXP23XX_INTB; irq++) {
set_irq_chip(irq, &ixp23xx_pci_irq_chip); irq_set_chip(irq, &ixp23xx_pci_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
set_irq_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler); irq_set_chained_handler(IRQ_IXP23XX_PCI_INT_RPH, pci_handler);
} }
......
...@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void) ...@@ -136,8 +136,8 @@ void __init ixdp2351_init_irq(void)
irq++) { irq++) {
if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) { if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_chip(irq, &ixdp2351_inta_chip); irq_set_chip(irq, &ixdp2351_inta_chip);
} }
} }
...@@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void) ...@@ -147,13 +147,13 @@ void __init ixdp2351_init_irq(void)
irq++) { irq++) {
if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) { if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_chip(irq, &ixdp2351_intb_chip); irq_set_chip(irq, &ixdp2351_intb_chip);
} }
} }
set_irq_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler); irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
set_irq_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler); irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
} }
/* /*
......
...@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin) ...@@ -110,8 +110,8 @@ static int __init roadrunner_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
static void __init roadrunner_pci_preinit(void) static void __init roadrunner_pci_preinit(void)
{ {
set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTC, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_ROADRUNNER_PCI_INTD, IRQ_TYPE_LEVEL_LOW);
ixp23xx_pci_preinit(); ixp23xx_pci_preinit();
} }
......
...@@ -39,10 +39,10 @@ ...@@ -39,10 +39,10 @@
void __init avila_pci_preinit(void) void __init avila_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void) ...@@ -252,8 +252,8 @@ void __init ixp4xx_init_irq(void)
/* Default to all level triggered */ /* Default to all level triggered */
for(i = 0; i < NR_IRQS; i++) { for(i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &ixp4xx_irq_chip); irq_set_chip(i, &ixp4xx_irq_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
} }
......
...@@ -32,8 +32,8 @@ ...@@ -32,8 +32,8 @@
void __init coyote_pci_preinit(void) void __init coyote_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT0_INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(SLOT1_INTA), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -35,12 +35,12 @@ ...@@ -35,12 +35,12 @@
void __init dsmg600_pci_preinit(void) void __init dsmg600_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTF), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -32,9 +32,9 @@ ...@@ -32,9 +32,9 @@
void __init fsg_pci_preinit(void) void __init fsg_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -29,8 +29,8 @@ ...@@ -29,8 +29,8 @@
void __init gateway7001_pci_preinit(void) void __init gateway7001_pci_preinit(void)
{ {
set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_IXP4XX_GPIO10, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_IXP4XX_GPIO11, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -420,8 +420,8 @@ static void __init gmlr_init(void) ...@@ -420,8 +420,8 @@ static void __init gmlr_init(void)
gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT); gpio_line_config(GPIO_HSS1_RTS_N, IXP4XX_GPIO_OUT);
gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS0_DCD_N, IXP4XX_GPIO_IN);
gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN); gpio_line_config(GPIO_HSS1_DCD_N, IXP4XX_GPIO_IN);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH); irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS0_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH); irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_HSS1_DCD_N), IRQ_TYPE_EDGE_BOTH);
set_control(CONTROL_HSS0_DTR_N, 1); set_control(CONTROL_HSS0_DTR_N, 1);
set_control(CONTROL_HSS1_DTR_N, 1); set_control(CONTROL_HSS1_DTR_N, 1);
...@@ -441,10 +441,10 @@ static void __init gmlr_init(void) ...@@ -441,10 +441,10 @@ static void __init gmlr_init(void)
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
static void __init gmlr_pci_preinit(void) static void __init gmlr_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_ETHB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_NEC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(GPIO_IRQ_MPCI), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -43,8 +43,8 @@ ...@@ -43,8 +43,8 @@
*/ */
void __init gtwx5715_pci_preinit(void) void __init gtwx5715_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -36,10 +36,10 @@ ...@@ -36,10 +36,10 @@
void __init ixdp425_pci_preinit(void) void __init ixdp425_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -25,8 +25,8 @@ ...@@ -25,8 +25,8 @@
void __init ixdpg425_pci_preinit(void) void __init ixdpg425_pci_preinit(void)
{ {
set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_IXP4XX_GPIO6, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_IXP4XX_GPIO7, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -33,11 +33,11 @@ ...@@ -33,11 +33,11 @@
void __init nas100d_pci_preinit(void) void __init nas100d_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTD), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTE), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -32,9 +32,9 @@ ...@@ -32,9 +32,9 @@
void __init nslu2_pci_preinit(void) void __init nslu2_pci_preinit(void)
{ {
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTC), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void) ...@@ -38,8 +38,8 @@ void __init vulcan_pci_preinit(void)
pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n", pr_info("Vulcan PCI: limiting CardBus memory size to %dMB\n",
(int)(pci_cardbus_mem_size >> 20)); (int)(pci_cardbus_mem_size >> 20));
#endif #endif
set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTA), IRQ_TYPE_LEVEL_LOW);
set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IXP4XX_GPIO_IRQ(INTB), IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -29,8 +29,8 @@ ...@@ -29,8 +29,8 @@
void __init wg302v2_pci_preinit(void) void __init wg302v2_pci_preinit(void)
{ {
set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_IXP4XX_GPIO8, IRQ_TYPE_LEVEL_LOW);
set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(IRQ_IXP4XX_GPIO9, IRQ_TYPE_LEVEL_LOW);
ixp4xx_pci_preinit(); ixp4xx_pci_preinit();
} }
......
...@@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void) ...@@ -35,14 +35,15 @@ void __init kirkwood_init_irq(void)
*/ */
orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0, orion_gpio_init(0, 32, GPIO_LOW_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START); IRQ_KIRKWOOD_GPIO_START);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_LOW_24_31, gpio_irq_handler);
orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0, orion_gpio_init(32, 18, GPIO_HIGH_VIRT_BASE, 0,
IRQ_KIRKWOOD_GPIO_START + 32); IRQ_KIRKWOOD_GPIO_START + 32);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_KIRKWOOD_GPIO_HIGH_16_23,
gpio_irq_handler);
} }
...@@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type) ...@@ -80,7 +80,7 @@ int ks8695_gpio_interrupt(unsigned int pin, unsigned int type)
local_irq_restore(flags); local_irq_restore(flags);
/* Set IRQ triggering type */ /* Set IRQ triggering type */
set_irq_type(gpio_irq[pin], type); irq_set_irq_type(gpio_irq[pin], type);
/* enable interrupt mode */ /* enable interrupt mode */
ks8695_gpio_mode(pin, 0); ks8695_gpio_mode(pin, 0);
......
...@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type) ...@@ -115,12 +115,12 @@ static int ks8695_irq_set_type(struct irq_data *d, unsigned int type)
} }
if (level_triggered) { if (level_triggered) {
set_irq_chip(d->irq, &ks8695_irq_level_chip); irq_set_chip(d->irq, &ks8695_irq_level_chip);
set_irq_handler(d->irq, handle_level_irq); irq_set_handler(d->irq, handle_level_irq);
} }
else { else {
set_irq_chip(d->irq, &ks8695_irq_edge_chip); irq_set_chip(d->irq, &ks8695_irq_edge_chip);
set_irq_handler(d->irq, handle_edge_irq); irq_set_handler(d->irq, handle_edge_irq);
} }
__raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC); __raw_writel(ctrl, KS8695_GPIO_VA + KS8695_IOPC);
...@@ -158,16 +158,16 @@ void __init ks8695_init_irq(void) ...@@ -158,16 +158,16 @@ void __init ks8695_init_irq(void)
case KS8695_IRQ_UART_RX: case KS8695_IRQ_UART_RX:
case KS8695_IRQ_COMM_TX: case KS8695_IRQ_COMM_TX:
case KS8695_IRQ_COMM_RX: case KS8695_IRQ_COMM_RX:
set_irq_chip(irq, &ks8695_irq_level_chip); irq_set_chip(irq, &ks8695_irq_level_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
break; break;
/* Edge-triggered interrupts */ /* Edge-triggered interrupts */
default: default:
/* clear pending bit */ /* clear pending bit */
ks8695_irq_ack(irq_get_irq_data(irq)); ks8695_irq_ack(irq_get_irq_data(irq));
set_irq_chip(irq, &ks8695_irq_edge_chip); irq_set_chip(irq, &ks8695_irq_edge_chip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
} }
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
......
...@@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type) ...@@ -290,7 +290,7 @@ static int lpc32xx_set_irq_type(struct irq_data *d, unsigned int type)
} }
/* Ok to use the level handler for all types */ /* Ok to use the level handler for all types */
set_irq_handler(d->irq, handle_level_irq); irq_set_handler(d->irq, handle_level_irq);
return 0; return 0;
} }
...@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void) ...@@ -390,8 +390,8 @@ void __init lpc32xx_init_irq(void)
/* Configure supported IRQ's */ /* Configure supported IRQ's */
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
set_irq_chip(i, &lpc32xx_irq_chip); irq_set_chip(i, &lpc32xx_irq_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
...@@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void) ...@@ -406,8 +406,8 @@ void __init lpc32xx_init_irq(void)
__raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE)); __raw_writel(0, LPC32XX_INTC_MASK(LPC32XX_SIC2_BASE));
/* MIC SUBIRQx interrupts will route handling to the chain handlers */ /* MIC SUBIRQx interrupts will route handling to the chain handlers */
set_irq_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler); irq_set_chained_handler(IRQ_LPC32XX_SUB1IRQ, lpc32xx_sic1_handler);
set_irq_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler); irq_set_chained_handler(IRQ_LPC32XX_SUB2IRQ, lpc32xx_sic2_handler);
/* Initially disable all wake events */ /* Initially disable all wake events */
__raw_writel(0, LPC32XX_CLKPWR_P01_ER); __raw_writel(0, LPC32XX_CLKPWR_P01_ER);
......
...@@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num) ...@@ -110,9 +110,9 @@ static void init_mux_irq(struct irq_chip *chip, int start, int num)
if (chip->irq_ack) if (chip->irq_ack)
chip->irq_ack(d); chip->irq_ack(d);
set_irq_chip(irq, chip); irq_set_chip(irq, chip);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
} }
} }
...@@ -122,7 +122,7 @@ void __init mmp2_init_icu(void) ...@@ -122,7 +122,7 @@ void __init mmp2_init_icu(void)
for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) { for (irq = 0; irq < IRQ_MMP2_MUX_BASE; irq++) {
icu_mask_irq(irq_get_irq_data(irq)); icu_mask_irq(irq_get_irq_data(irq));
set_irq_chip(irq, &icu_irq_chip); irq_set_chip(irq, &icu_irq_chip);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
switch (irq) { switch (irq) {
...@@ -133,7 +133,7 @@ void __init mmp2_init_icu(void) ...@@ -133,7 +133,7 @@ void __init mmp2_init_icu(void)
case IRQ_MMP2_SSP_MUX: case IRQ_MMP2_SSP_MUX:
break; break;
default: default:
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
break; break;
} }
} }
...@@ -149,9 +149,9 @@ void __init mmp2_init_icu(void) ...@@ -149,9 +149,9 @@ void __init mmp2_init_icu(void)
init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15); init_mux_irq(&misc_irq_chip, IRQ_MMP2_MISC_BASE, 15);
init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2); init_mux_irq(&ssp_irq_chip, IRQ_MMP2_SSP_BASE, 2);
set_irq_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux); irq_set_chained_handler(IRQ_MMP2_PMIC_MUX, pmic_irq_demux);
set_irq_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux); irq_set_chained_handler(IRQ_MMP2_RTC_MUX, rtc_irq_demux);
set_irq_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux); irq_set_chained_handler(IRQ_MMP2_TWSI_MUX, twsi_irq_demux);
set_irq_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux); irq_set_chained_handler(IRQ_MMP2_MISC_MUX, misc_irq_demux);
set_irq_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux); irq_set_chained_handler(IRQ_MMP2_SSP_MUX, ssp_irq_demux);
} }
...@@ -48,8 +48,8 @@ void __init icu_init_irq(void) ...@@ -48,8 +48,8 @@ void __init icu_init_irq(void)
for (irq = 0; irq < 64; irq++) { for (irq = 0; irq < 64; irq++) {
icu_mask_irq(irq_get_irq_data(irq)); icu_mask_irq(irq_get_irq_data(irq));
set_irq_chip(irq, &icu_irq_chip); irq_set_chip(irq, &icu_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
} }
...@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void) ...@@ -53,7 +53,7 @@ static void __init msm8960_init_irq(void)
*/ */
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq); irq_set_handler(i, handle_percpu_irq);
} }
} }
......
...@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void) ...@@ -56,7 +56,7 @@ static void __init msm8x60_init_irq(void)
*/ */
for (i = GIC_PPI_START; i < GIC_SPI_START; i++) { for (i = GIC_PPI_START; i < GIC_SPI_START; i++) {
if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE) if (i != AVS_SVICINT && i != AVS_SVICINTSWDONE)
set_irq_handler(i, handle_percpu_irq); irq_set_handler(i, handle_percpu_irq);
} }
} }
......
...@@ -214,17 +214,17 @@ int __init trout_init_gpio(void) ...@@ -214,17 +214,17 @@ int __init trout_init_gpio(void)
{ {
int i; int i;
for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) { for(i = TROUT_INT_START; i <= TROUT_INT_END; i++) {
set_irq_chip(i, &trout_gpio_irq_chip); irq_set_chip(i, &trout_gpio_irq_chip);
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++) for (i = 0; i < ARRAY_SIZE(msm_gpio_banks); i++)
gpiochip_add(&msm_gpio_banks[i].chip); gpiochip_add(&msm_gpio_banks[i].chip);
set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH); irq_set_irq_type(MSM_GPIO_TO_INT(17), IRQF_TRIGGER_HIGH);
set_irq_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler); irq_set_chained_handler(MSM_GPIO_TO_INT(17), trout_gpio_irq_handler);
set_irq_wake(MSM_GPIO_TO_INT(17), 1); irq_set_irq_wake(MSM_GPIO_TO_INT(17), 1);
return 0; return 0;
} }
......
...@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev) ...@@ -174,7 +174,7 @@ int __init trout_init_mmc(unsigned int sys_rev)
if (IS_ERR(vreg_sdslot)) if (IS_ERR(vreg_sdslot))
return PTR_ERR(vreg_sdslot); return PTR_ERR(vreg_sdslot);
set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1); irq_set_irq_wake(TROUT_GPIO_TO_INT(TROUT_GPIO_SDMC_CD_N), 1);
if (!opt_disable_sdcard) if (!opt_disable_sdcard)
msm_add_sdcc(2, &trout_sdslot_data, msm_add_sdcc(2, &trout_sdslot_data,
......
...@@ -328,12 +328,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on) ...@@ -328,12 +328,12 @@ static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
if (on) { if (on) {
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1);
set_bit(gpio, msm_gpio.wake_irqs); set_bit(gpio, msm_gpio.wake_irqs);
} else { } else {
clear_bit(gpio, msm_gpio.wake_irqs); clear_bit(gpio, msm_gpio.wake_irqs);
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS))
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); irq_set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0);
} }
return 0; return 0;
...@@ -362,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev) ...@@ -362,12 +362,12 @@ static int __devinit msm_gpio_probe(struct platform_device *dev)
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) {
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i);
set_irq_chip(irq, &msm_gpio_irq_chip); irq_set_chip(irq, &msm_gpio_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, irq_set_chained_handler(TLMM_SCSS_SUMMARY_IRQ,
msm_summary_irq_handler); msm_summary_irq_handler);
return 0; return 0;
} }
...@@ -379,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev) ...@@ -379,7 +379,7 @@ static int __devexit msm_gpio_remove(struct platform_device *dev)
if (ret < 0) if (ret < 0)
return ret; return ret;
set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); irq_set_handler(TLMM_SCSS_SUMMARY_IRQ, NULL);
return 0; return 0;
} }
......
...@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void) ...@@ -354,9 +354,9 @@ static int __init msm_init_gpio(void)
msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.base +
msm_gpio_chips[j].chip.ngpio) msm_gpio_chips[j].chip.ngpio)
j++; j++;
set_irq_chip_data(i, &msm_gpio_chips[j]); irq_set_chip_data(i, &msm_gpio_chips[j]);
set_irq_chip(i, &msm_gpio_irq_chip); irq_set_chip(i, &msm_gpio_irq_chip);
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
...@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void) ...@@ -366,10 +366,10 @@ static int __init msm_init_gpio(void)
gpiochip_add(&msm_gpio_chips[i].chip); gpiochip_add(&msm_gpio_chips[i].chip);
} }
set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); irq_set_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler);
set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); irq_set_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler);
set_irq_wake(INT_GPIO_GROUP1, 1); irq_set_irq_wake(INT_GPIO_GROUP1, 1);
set_irq_wake(INT_GPIO_GROUP2, 2); irq_set_irq_wake(INT_GPIO_GROUP2, 2);
return 0; return 0;
} }
......
...@@ -357,8 +357,8 @@ void __init msm_init_irq(void) ...@@ -357,8 +357,8 @@ void __init msm_init_irq(void)
writel(3, VIC_INT_MASTEREN); writel(3, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) { for (n = 0; n < NR_MSM_IRQS; n++) {
set_irq_chip(n, &msm_irq_chip); irq_set_chip(n, &msm_irq_chip);
set_irq_handler(n, handle_level_irq); irq_set_handler(n, handle_level_irq);
set_irq_flags(n, IRQF_VALID); set_irq_flags(n, IRQF_VALID);
} }
} }
...@@ -145,8 +145,8 @@ void __init msm_init_irq(void) ...@@ -145,8 +145,8 @@ void __init msm_init_irq(void)
writel(1, VIC_INT_MASTEREN); writel(1, VIC_INT_MASTEREN);
for (n = 0; n < NR_MSM_IRQS; n++) { for (n = 0; n < NR_MSM_IRQS; n++) {
set_irq_chip(n, &msm_irq_chip); irq_set_chip(n, &msm_irq_chip);
set_irq_handler(n, handle_level_irq); irq_set_handler(n, handle_level_irq);
set_irq_flags(n, IRQF_VALID); set_irq_flags(n, IRQF_VALID);
} }
} }
...@@ -158,15 +158,15 @@ void __init msm_init_sirc(void) ...@@ -158,15 +158,15 @@ void __init msm_init_sirc(void)
wake_enable = 0; wake_enable = 0;
for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) { for (i = FIRST_SIRC_IRQ; i < LAST_SIRC_IRQ; i++) {
set_irq_chip(i, &sirc_irq_chip); irq_set_chip(i, &sirc_irq_chip);
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) { for (i = 0; i < ARRAY_SIZE(sirc_reg_table); i++) {
set_irq_chained_handler(sirc_reg_table[i].cascade_irq, irq_set_chained_handler(sirc_reg_table[i].cascade_irq,
sirc_irq_handler); sirc_irq_handler);
set_irq_wake(sirc_reg_table[i].cascade_irq, 1); irq_set_irq_wake(sirc_reg_table[i].cascade_irq, 1);
} }
return; return;
} }
......
...@@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void) ...@@ -38,8 +38,8 @@ void __init mv78xx0_init_irq(void)
orion_gpio_init(0, 32, GPIO_VIRT_BASE, orion_gpio_init(0, 32, GPIO_VIRT_BASE,
mv78xx0_core_index() ? 0x18 : 0, mv78xx0_core_index() ? 0x18 : 0,
IRQ_MV78XX0_GPIO_START); IRQ_MV78XX0_GPIO_START);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler); irq_set_chained_handler(IRQ_MV78XX0_GPIO_24_31, gpio_irq_handler);
} }
...@@ -199,12 +199,12 @@ static void __init mx31ads_init_expio(void) ...@@ -199,12 +199,12 @@ static void __init mx31ads_init_expio(void)
__raw_writew(0xFFFF, PBC_INTSTATUS_REG); __raw_writew(0xFFFF, PBC_INTSTATUS_REG);
for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES); for (i = MXC_EXP_IO_BASE; i < (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES);
i++) { i++) {
set_irq_chip(i, &expio_irq_chip); irq_set_chip(i, &expio_irq_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH); irq_set_irq_type(EXPIO_PARENT_INT, IRQ_TYPE_LEVEL_HIGH);
set_irq_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler); irq_set_chained_handler(EXPIO_PARENT_INT, mx31ads_expio_irq_handler);
} }
#ifdef CONFIG_MACH_MX31ADS_WM1133_EV1 #ifdef CONFIG_MACH_MX31ADS_WM1133_EV1
......
...@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void) ...@@ -212,7 +212,7 @@ void __init eukrea_mbimx51_baseboard_init(void)
gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq"); gpio_request(MBIMX51_TSC2007_GPIO, "tsc2007_irq");
gpio_direction_input(MBIMX51_TSC2007_GPIO); gpio_direction_input(MBIMX51_TSC2007_GPIO);
set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING); irq_set_irq_type(MBIMX51_TSC2007_IRQ, IRQF_TRIGGER_FALLING);
i2c_register_board_info(1, mbimx51_i2c_devices, i2c_register_board_info(1, mbimx51_i2c_devices,
ARRAY_SIZE(mbimx51_i2c_devices)); ARRAY_SIZE(mbimx51_i2c_devices));
......
...@@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type) ...@@ -136,7 +136,7 @@ static int mxs_gpio_set_irq_type(struct irq_data *d, unsigned int type)
static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc) static void mxs_gpio_irq_handler(u32 irq, struct irq_desc *desc)
{ {
u32 irq_stat; u32 irq_stat;
struct mxs_gpio_port *port = (struct mxs_gpio_port *)get_irq_data(irq); struct mxs_gpio_port *port = (struct mxs_gpio_port *)irq_get_handler_data(irq);
u32 gpio_irq_no_base = port->virtual_irq_start; u32 gpio_irq_no_base = port->virtual_irq_start;
desc->irq_data.chip->irq_ack(&desc->irq_data); desc->irq_data.chip->irq_ack(&desc->irq_data);
...@@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt) ...@@ -265,14 +265,14 @@ int __init mxs_gpio_init(struct mxs_gpio_port *port, int cnt)
for (j = port[i].virtual_irq_start; for (j = port[i].virtual_irq_start;
j < port[i].virtual_irq_start + 32; j++) { j < port[i].virtual_irq_start + 32; j++) {
set_irq_chip(j, &gpio_irq_chip); irq_set_chip(j, &gpio_irq_chip);
set_irq_handler(j, handle_level_irq); irq_set_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID); set_irq_flags(j, IRQF_VALID);
} }
/* setup one handler for each entry */ /* setup one handler for each entry */
set_irq_chained_handler(port[i].irq, mxs_gpio_irq_handler); irq_set_chained_handler(port[i].irq, mxs_gpio_irq_handler);
set_irq_data(port[i].irq, &port[i]); irq_set_handler_data(port[i].irq, &port[i]);
/* register gpio chip */ /* register gpio chip */
port[i].chip.direction_input = mxs_gpio_direction_input; port[i].chip.direction_input = mxs_gpio_direction_input;
......
...@@ -74,8 +74,8 @@ void __init icoll_init_irq(void) ...@@ -74,8 +74,8 @@ void __init icoll_init_irq(void)
mxs_reset_block(icoll_base + HW_ICOLL_CTRL); mxs_reset_block(icoll_base + HW_ICOLL_CTRL);
for (i = 0; i < MXS_INTERNAL_IRQS; i++) { for (i = 0; i < MXS_INTERNAL_IRQS; i++) {
set_irq_chip(i, &mxs_icoll_chip); irq_set_chip(i, &mxs_icoll_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
} }
...@@ -171,13 +171,13 @@ void __init netx_init_irq(void) ...@@ -171,13 +171,13 @@ void __init netx_init_irq(void)
vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0); vic_init(__io(io_p2v(NETX_PA_VIC)), 0, ~0, 0);
for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) { for (irq = NETX_IRQ_HIF_CHAINED(0); irq <= NETX_IRQ_HIF_LAST; irq++) {
set_irq_chip(irq, &netx_hif_chip); irq_set_chip(irq, &netx_hif_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN); writel(NETX_DPMAS_INT_EN_GLB_EN, NETX_DPMAS_INT_EN);
set_irq_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler); irq_set_chained_handler(NETX_IRQ_HIF, netx_hif_demux_handler);
} }
static int __init netx_init(void) static int __init netx_init(void)
......
...@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void) ...@@ -107,8 +107,8 @@ void __init board_a9m9750dev_init_irq(void)
__func__); __func__);
for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) { for (i = FPGA_IRQ(0); i <= FPGA_IRQ(7); ++i) {
set_irq_chip(i, &a9m9750dev_fpga_chip); irq_set_chip(i, &a9m9750dev_fpga_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
...@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void) ...@@ -118,8 +118,8 @@ void __init board_a9m9750dev_init_irq(void)
REGSET(eic, SYS_EIC, LVEDG, LEVEL); REGSET(eic, SYS_EIC, LVEDG, LEVEL);
__raw_writel(eic, SYS_EIC(2)); __raw_writel(eic, SYS_EIC(2));
set_irq_chained_handler(IRQ_NS9XXX_EXT2, irq_set_chained_handler(IRQ_NS9XXX_EXT2,
a9m9750dev_fpga_demux_handler); a9m9750dev_fpga_demux_handler);
} }
void __init board_a9m9750dev_init_machine(void) void __init board_a9m9750dev_init_machine(void)
......
...@@ -67,8 +67,8 @@ void __init ns9xxx_init_irq(void) ...@@ -67,8 +67,8 @@ void __init ns9xxx_init_irq(void)
__raw_writel(prio2irq(i), SYS_IVA(i)); __raw_writel(prio2irq(i), SYS_IVA(i));
for (i = 0; i <= 31; ++i) { for (i = 0; i <= 31; ++i) {
set_irq_chip(i, &ns9xxx_chip); irq_set_chip(i, &ns9xxx_chip);
set_irq_handler(i, handle_fasteoi_irq); irq_set_handler(i, handle_fasteoi_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
irq_set_status_flags(i, IRQ_LEVEL); irq_set_status_flags(i, IRQ_LEVEL);
} }
......
...@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void) ...@@ -59,8 +59,8 @@ void __init nuc93x_init_irq(void)
__raw_writel(0xFFFFFFFE, REG_AIC_MDCR); __raw_writel(0xFFFFFFFE, REG_AIC_MDCR);
for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) { for (irqno = IRQ_WDT; irqno <= NR_IRQS; irqno++) {
set_irq_chip(irqno, &nuc93x_irq_chip); irq_set_chip(irqno, &nuc93x_irq_chip);
set_irq_handler(irqno, handle_level_irq); irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID); set_irq_flags(irqno, IRQF_VALID);
} }
} }
...@@ -276,7 +276,7 @@ static void __init osk_init_cf(void) ...@@ -276,7 +276,7 @@ static void __init osk_init_cf(void)
return; return;
} }
/* the CF I/O IRQ is really active-low */ /* the CF I/O IRQ is really active-low */
set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(gpio_to_irq(62), IRQ_TYPE_EDGE_FALLING);
} }
static void __init osk_init_irq(void) static void __init osk_init_irq(void)
...@@ -482,7 +482,7 @@ static void __init osk_mistral_init(void) ...@@ -482,7 +482,7 @@ static void __init osk_mistral_init(void)
omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */ omap_cfg_reg(P20_1610_GPIO4); /* PENIRQ */
gpio_request(4, "ts_int"); gpio_request(4, "ts_int");
gpio_direction_input(4); gpio_direction_input(4);
set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(gpio_to_irq(4), IRQ_TYPE_EDGE_FALLING);
spi_register_board_info(mistral_boardinfo, spi_register_board_info(mistral_boardinfo,
ARRAY_SIZE(mistral_boardinfo)); ARRAY_SIZE(mistral_boardinfo));
...@@ -500,7 +500,7 @@ static void __init osk_mistral_init(void) ...@@ -500,7 +500,7 @@ static void __init osk_mistral_init(void)
int irq = gpio_to_irq(OMAP_MPUIO(2)); int irq = gpio_to_irq(OMAP_MPUIO(2));
gpio_direction_input(OMAP_MPUIO(2)); gpio_direction_input(OMAP_MPUIO(2));
set_irq_type(irq, IRQ_TYPE_EDGE_RISING); irq_set_irq_type(irq, IRQ_TYPE_EDGE_RISING);
#ifdef CONFIG_PM #ifdef CONFIG_PM
/* share the IRQ in case someone wants to use the /* share the IRQ in case someone wants to use the
* button for more than wakeup from system sleep. * button for more than wakeup from system sleep.
......
...@@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id) ...@@ -256,12 +256,12 @@ palmz71_powercable(int irq, void *dev_id)
{ {
if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) { if (gpio_get_value(PALMZ71_USBDETECT_GPIO)) {
printk(KERN_INFO "PM: Power cable connected\n"); printk(KERN_INFO "PM: Power cable connected\n");
set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
IRQ_TYPE_EDGE_FALLING); IRQ_TYPE_EDGE_FALLING);
} else { } else {
printk(KERN_INFO "PM: Power cable disconnected\n"); printk(KERN_INFO "PM: Power cable disconnected\n");
set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO), irq_set_irq_type(gpio_to_irq(PALMZ71_USBDETECT_GPIO),
IRQ_TYPE_EDGE_RISING); IRQ_TYPE_EDGE_RISING);
} }
return IRQ_HANDLED; return IRQ_HANDLED;
} }
......
...@@ -279,10 +279,10 @@ static void __init voiceblue_init(void) ...@@ -279,10 +279,10 @@ static void __init voiceblue_init(void)
gpio_request(13, "16C554 irq"); gpio_request(13, "16C554 irq");
gpio_request(14, "16C554 irq"); gpio_request(14, "16C554 irq");
gpio_request(15, "16C554 irq"); gpio_request(15, "16C554 irq");
set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(12), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(14), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(15), IRQ_TYPE_EDGE_RISING);
platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices)); platform_add_devices(voiceblue_devices, ARRAY_SIZE(voiceblue_devices));
omap_board_config = voiceblue_config; omap_board_config = voiceblue_config;
......
...@@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void) ...@@ -156,17 +156,17 @@ void omap1510_fpga_init_irq(void)
* The touchscreen interrupt is level-sensitive, so * The touchscreen interrupt is level-sensitive, so
* we'll use the regular mask_ack routine for it. * we'll use the regular mask_ack routine for it.
*/ */
set_irq_chip(i, &omap_fpga_irq_ack); irq_set_chip(i, &omap_fpga_irq_ack);
} }
else { else {
/* /*
* All FPGA interrupts except the touchscreen are * All FPGA interrupts except the touchscreen are
* edge-sensitive, so we won't mask them. * edge-sensitive, so we won't mask them.
*/ */
set_irq_chip(i, &omap_fpga_irq); irq_set_chip(i, &omap_fpga_irq);
} }
set_irq_handler(i, handle_edge_irq); irq_set_handler(i, handle_edge_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
...@@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void) ...@@ -183,6 +183,6 @@ void omap1510_fpga_init_irq(void)
return; return;
} }
gpio_direction_input(13); gpio_direction_input(13);
set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(13), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux); irq_set_chained_handler(OMAP1510_INT_FPGA, innovator_fpga_IRQ_demux);
} }
...@@ -230,8 +230,8 @@ void __init omap_init_irq(void) ...@@ -230,8 +230,8 @@ void __init omap_init_irq(void)
irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j); irq_trigger = irq_banks[i].trigger_map >> IRQ_BIT(j);
omap_irq_set_cfg(j, 0, 0, irq_trigger); omap_irq_set_cfg(j, 0, 0, irq_trigger);
set_irq_chip(j, &omap_irq_chip); irq_set_chip(j, &omap_irq_chip);
set_irq_handler(j, handle_level_irq); irq_set_handler(j, handle_level_irq);
set_irq_flags(j, IRQF_VALID); set_irq_flags(j, IRQF_VALID);
} }
} }
......
...@@ -743,7 +743,7 @@ static int __init gpmc_init(void) ...@@ -743,7 +743,7 @@ static int __init gpmc_init(void)
/* initalize the irq_chained */ /* initalize the irq_chained */
irq = OMAP_GPMC_IRQ_BASE; irq = OMAP_GPMC_IRQ_BASE;
for (cs = 0; cs < GPMC_CS_NUM; cs++) { for (cs = 0; cs < GPMC_CS_NUM; cs++) {
set_irq_chip_and_handler(irq, &dummy_irq_chip, irq_set_chip_and_handler(irq, &dummy_irq_chip,
handle_simple_irq); handle_simple_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
irq++; irq++;
......
...@@ -223,8 +223,8 @@ void __init omap_init_irq(void) ...@@ -223,8 +223,8 @@ void __init omap_init_irq(void)
nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : ""); nr_of_irqs, nr_banks, nr_banks > 1 ? "s" : "");
for (i = 0; i < nr_of_irqs; i++) { for (i = 0; i < nr_of_irqs; i++) {
set_irq_chip(i, &omap_irq_chip); irq_set_chip(i, &omap_irq_chip);
set_irq_handler(i, handle_level_irq); irq_set_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
} }
} }
......
...@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void) ...@@ -213,7 +213,7 @@ void __init db88f5281_pci_preinit(void)
pin = DB88F5281_PCI_SLOT0_IRQ_PIN; pin = DB88F5281_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "db88f5281_pci_preinit faield to " printk(KERN_ERR "db88f5281_pci_preinit faield to "
"set_irq_type pin %d\n", pin); "set_irq_type pin %d\n", pin);
...@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void) ...@@ -226,7 +226,7 @@ void __init db88f5281_pci_preinit(void)
pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN; pin = DB88F5281_PCI_SLOT1_SLOT2_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "db88f5281_pci_preinit faield " printk(KERN_ERR "db88f5281_pci_preinit faield "
"to set_irq_type pin %d\n", pin); "to set_irq_type pin %d\n", pin);
......
...@@ -34,8 +34,8 @@ void __init orion5x_init_irq(void) ...@@ -34,8 +34,8 @@ void __init orion5x_init_irq(void)
* Initialize gpiolib for GPIOs 0-31. * Initialize gpiolib for GPIOs 0-31.
*/ */
orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START); orion_gpio_init(0, 32, GPIO_VIRT_BASE, 0, IRQ_ORION5X_GPIO_START);
set_irq_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler); irq_set_chained_handler(IRQ_ORION5X_GPIO_0_7, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler); irq_set_chained_handler(IRQ_ORION5X_GPIO_8_15, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler); irq_set_chained_handler(IRQ_ORION5X_GPIO_16_23, gpio_irq_handler);
set_irq_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler); irq_set_chained_handler(IRQ_ORION5X_GPIO_24_31, gpio_irq_handler);
} }
...@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void) ...@@ -148,7 +148,7 @@ void __init rd88f5182_pci_preinit(void)
pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN; pin = RD88F5182_PCI_SLOT0_IRQ_A_PIN;
if (gpio_request(pin, "PCI IntA") == 0) { if (gpio_request(pin, "PCI IntA") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to " printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin); "set_irq_type pin %d\n", pin);
...@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void) ...@@ -161,7 +161,7 @@ void __init rd88f5182_pci_preinit(void)
pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN; pin = RD88F5182_PCI_SLOT0_IRQ_B_PIN;
if (gpio_request(pin, "PCI IntB") == 0) { if (gpio_request(pin, "PCI IntB") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "rd88f5182_pci_preinit faield to " printk(KERN_ERR "rd88f5182_pci_preinit faield to "
"set_irq_type pin %d\n", pin); "set_irq_type pin %d\n", pin);
......
...@@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void) ...@@ -88,7 +88,7 @@ void __init tsp2_pci_preinit(void)
pin = TSP2_PCI_SLOT0_IRQ_PIN; pin = TSP2_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "tsp2_pci_preinit failed " printk(KERN_ERR "tsp2_pci_preinit failed "
"to set_irq_type pin %d\n", pin); "to set_irq_type pin %d\n", pin);
......
...@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void) ...@@ -117,7 +117,7 @@ void __init qnap_ts209_pci_preinit(void)
pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN; pin = QNAP_TS209_PCI_SLOT0_IRQ_PIN;
if (gpio_request(pin, "PCI Int1") == 0) { if (gpio_request(pin, "PCI Int1") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed to " printk(KERN_ERR "qnap_ts209_pci_preinit failed to "
"set_irq_type pin %d\n", pin); "set_irq_type pin %d\n", pin);
...@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void) ...@@ -131,7 +131,7 @@ void __init qnap_ts209_pci_preinit(void)
pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN; pin = QNAP_TS209_PCI_SLOT1_IRQ_PIN;
if (gpio_request(pin, "PCI Int2") == 0) { if (gpio_request(pin, "PCI Int2") == 0) {
if (gpio_direction_input(pin) == 0) { if (gpio_direction_input(pin) == 0) {
set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW); irq_set_irq_type(gpio_to_irq(pin), IRQ_TYPE_LEVEL_LOW);
} else { } else {
printk(KERN_ERR "qnap_ts209_pci_preinit failed " printk(KERN_ERR "qnap_ts209_pci_preinit failed "
"to set_irq_type pin %d\n", pin); "to set_irq_type pin %d\n", pin);
......
...@@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type) ...@@ -58,22 +58,22 @@ static int pnx4008_set_irq_type(struct irq_data *d, unsigned int type)
case IRQ_TYPE_EDGE_RISING: case IRQ_TYPE_EDGE_RISING:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /*rising edge */
set_irq_handler(d->irq, handle_edge_irq); irq_set_handler(d->irq, handle_edge_irq);
break; break;
case IRQ_TYPE_EDGE_FALLING: case IRQ_TYPE_EDGE_FALLING:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */ __raw_writel(__raw_readl(INTC_ATR(d->irq)) | INTC_BIT(d->irq), INTC_ATR(d->irq)); /*edge sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*falling edge */
set_irq_handler(d->irq, handle_edge_irq); irq_set_handler(d->irq, handle_edge_irq);
break; break;
case IRQ_TYPE_LEVEL_LOW: case IRQ_TYPE_LEVEL_LOW:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */ __raw_writel(__raw_readl(INTC_APR(d->irq)) & ~INTC_BIT(d->irq), INTC_APR(d->irq)); /*low level */
set_irq_handler(d->irq, handle_level_irq); irq_set_handler(d->irq, handle_level_irq);
break; break;
case IRQ_TYPE_LEVEL_HIGH: case IRQ_TYPE_LEVEL_HIGH:
__raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */ __raw_writel(__raw_readl(INTC_ATR(d->irq)) & ~INTC_BIT(d->irq), INTC_ATR(d->irq)); /*level sensitive */
__raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */ __raw_writel(__raw_readl(INTC_APR(d->irq)) | INTC_BIT(d->irq), INTC_APR(d->irq)); /* high level */
set_irq_handler(d->irq, handle_level_irq); irq_set_handler(d->irq, handle_level_irq);
break; break;
/* IRQ_TYPE_EDGE_BOTH is not supported */ /* IRQ_TYPE_EDGE_BOTH is not supported */
...@@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void) ...@@ -98,7 +98,7 @@ void __init pnx4008_init_irq(void)
/* configure IRQ's */ /* configure IRQ's */
for (i = 0; i < NR_IRQS; i++) { for (i = 0; i < NR_IRQS; i++) {
set_irq_flags(i, IRQF_VALID); set_irq_flags(i, IRQF_VALID);
set_irq_chip(i, &pnx4008_irq_chip); irq_set_chip(i, &pnx4008_irq_chip);
pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]); pnx4008_set_irq_type(irq_get_irq_data(i), pnx4008_irq_type[i]);
} }
......
...@@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void) ...@@ -527,13 +527,13 @@ static void __init balloon3_init_irq(void)
pxa27x_init_irq(); pxa27x_init_irq();
/* setup extra Balloon3 irqs */ /* setup extra Balloon3 irqs */
for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) { for (irq = BALLOON3_IRQ(0); irq <= BALLOON3_IRQ(7); irq++) {
set_irq_chip(irq, &balloon3_irq_chip); irq_set_chip(irq, &balloon3_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
set_irq_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler); irq_set_chained_handler(BALLOON3_AUX_NIRQ, balloon3_irq_handler);
set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(BALLOON3_AUX_NIRQ, IRQ_TYPE_EDGE_FALLING);
pr_debug("%s: chained handler installed - irq %d automatically " pr_debug("%s: chained handler installed - irq %d automatically "
"enabled\n", __func__, BALLOON3_AUX_NIRQ); "enabled\n", __func__, BALLOON3_AUX_NIRQ);
......
...@@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio) ...@@ -70,9 +70,10 @@ void __cmx2xx_pci_init_irq(int irq_gpio)
cmx2xx_it8152_irq_gpio = irq_gpio; cmx2xx_it8152_irq_gpio = irq_gpio;
set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(irq_gpio), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(irq_gpio), cmx2xx_it8152_irq_demux); irq_set_chained_handler(gpio_to_irq(irq_gpio),
cmx2xx_it8152_irq_demux);
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM
......
...@@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void) ...@@ -765,7 +765,7 @@ static void __init cm_x300_init_da9030(void)
{ {
pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info); pxa3xx_set_i2c_power_info(&cm_x300_pwr_i2c_info);
i2c_register_board_info(1, &cm_x300_pmic_info, 1); i2c_register_board_info(1, &cm_x300_pmic_info, 1);
set_irq_wake(IRQ_WAKEUP0, 1); irq_set_irq_wake(IRQ_WAKEUP0, 1);
} }
static void __init cm_x300_init_wi2wi(void) static void __init cm_x300_init_wi2wi(void)
......
...@@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn) ...@@ -137,9 +137,9 @@ static void __init pxa_init_low_gpio_irq(set_wake_t fn)
GEDR0 = 0x3; GEDR0 = 0x3;
for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) { for (irq = IRQ_GPIO0; irq <= IRQ_GPIO1; irq++) {
set_irq_chip(irq, &pxa_low_gpio_chip); irq_set_chip(irq, &pxa_low_gpio_chip);
set_irq_chip_data(irq, irq_base(0)); irq_set_chip_data(irq, irq_base(0));
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
...@@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn) ...@@ -165,9 +165,9 @@ void __init pxa_init_irq(int irq_nr, set_wake_t fn)
__raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i)); __raw_writel(i | IPR_VALID, IRQ_BASE + IPR(i));
irq = PXA_IRQ(i); irq = PXA_IRQ(i);
set_irq_chip(irq, &pxa_internal_irq_chip); irq_set_chip(irq, &pxa_internal_irq_chip);
set_irq_chip_data(irq, base); irq_set_chip_data(irq, base);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
} }
......
...@@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void) ...@@ -149,12 +149,12 @@ static void __init lpd270_init_irq(void)
/* setup extra LogicPD PXA270 irqs */ /* setup extra LogicPD PXA270 irqs */
for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) { for (irq = LPD270_IRQ(2); irq <= LPD270_IRQ(4); irq++) {
set_irq_chip(irq, &lpd270_irq_chip); irq_set_chip(irq, &lpd270_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
set_irq_chained_handler(IRQ_GPIO(0), lpd270_irq_handler); irq_set_chained_handler(IRQ_GPIO(0), lpd270_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
} }
......
...@@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void) ...@@ -165,13 +165,13 @@ static void __init lubbock_init_irq(void)
/* setup extra lubbock irqs */ /* setup extra lubbock irqs */
for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) { for (irq = LUBBOCK_IRQ(0); irq <= LUBBOCK_LAST_IRQ; irq++) {
set_irq_chip(irq, &lubbock_irq_chip); irq_set_chip(irq, &lubbock_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
set_irq_chained_handler(IRQ_GPIO(0), lubbock_irq_handler); irq_set_chained_handler(IRQ_GPIO(0), lubbock_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM
......
...@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void) ...@@ -166,8 +166,8 @@ static void __init mainstone_init_irq(void)
/* setup extra Mainstone irqs */ /* setup extra Mainstone irqs */
for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) { for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
set_irq_chip(irq, &mainstone_irq_chip); irq_set_chip(irq, &mainstone_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14)) if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
else else
...@@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void) ...@@ -179,8 +179,8 @@ static void __init mainstone_init_irq(void)
MST_INTMSKENA = 0; MST_INTMSKENA = 0;
MST_INTSETCLR = 0; MST_INTSETCLR = 0;
set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler); irq_set_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(IRQ_GPIO(0), IRQ_TYPE_EDGE_FALLING);
} }
#ifdef CONFIG_PM #ifdef CONFIG_PM
......
...@@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void) ...@@ -281,16 +281,16 @@ static void __init pcm990_init_irq(void)
/* setup extra PCM990 irqs */ /* setup extra PCM990 irqs */
for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) { for (irq = PCM027_IRQ(0); irq <= PCM027_IRQ(3); irq++) {
set_irq_chip(irq, &pcm990_irq_chip); irq_set_chip(irq, &pcm990_irq_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
} }
PCM990_INTMSKENA = 0x00; /* disable all Interrupts */ PCM990_INTMSKENA = 0x00; /* disable all Interrupts */
PCM990_INTSETCLR = 0xFF; PCM990_INTSETCLR = 0xFF;
set_irq_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler); irq_set_chained_handler(PCM990_CTRL_INT_IRQ, pcm990_irq_handler);
set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE); irq_set_irq_type(PCM990_CTRL_INT_IRQ, PCM990_CTRL_INT_IRQ_EDGE);
} }
static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int, static int pcm990_mci_init(struct device *dev, irq_handler_t mci_detect_int,
......
...@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn) ...@@ -362,8 +362,8 @@ static void __init pxa_init_ext_wakeup_irq(set_wake_t fn)
int irq; int irq;
for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) { for (irq = IRQ_WAKEUP0; irq <= IRQ_WAKEUP1; irq++) {
set_irq_chip(irq, &pxa_ext_wakeup_chip); irq_set_chip(irq, &pxa_ext_wakeup_chip);
set_irq_handler(irq, handle_edge_irq); irq_set_handler(irq, handle_edge_irq);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
} }
......
...@@ -310,14 +310,14 @@ static void __init viper_init_irq(void) ...@@ -310,14 +310,14 @@ static void __init viper_init_irq(void)
/* setup ISA IRQs */ /* setup ISA IRQs */
for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) { for (level = 0; level < ARRAY_SIZE(viper_isa_irqs); level++) {
isa_irq = viper_bit_to_irq(level); isa_irq = viper_bit_to_irq(level);
set_irq_chip(isa_irq, &viper_irq_chip); irq_set_chip(isa_irq, &viper_irq_chip);
set_irq_handler(isa_irq, handle_edge_irq); irq_set_handler(isa_irq, handle_edge_irq);
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
} }
set_irq_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO), irq_set_chained_handler(gpio_to_irq(VIPER_CPLD_GPIO),
viper_irq_handler); viper_irq_handler);
set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH); irq_set_irq_type(gpio_to_irq(VIPER_CPLD_GPIO), IRQ_TYPE_EDGE_BOTH);
} }
/* Flat Panel */ /* Flat Panel */
......
...@@ -136,22 +136,23 @@ static void __init zeus_init_irq(void) ...@@ -136,22 +136,23 @@ static void __init zeus_init_irq(void)
/* Peripheral IRQs. It would be nice to move those inside driver /* Peripheral IRQs. It would be nice to move those inside driver
configuration, but it is not supported at the moment. */ configuration, but it is not supported at the moment. */
set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_AC97_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_WAKEUP_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_PTT_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO), IRQ_TYPE_EDGE_FALLING); irq_set_irq_type(gpio_to_irq(ZEUS_EXTGPIO_GPIO),
set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING); IRQ_TYPE_EDGE_FALLING);
irq_set_irq_type(gpio_to_irq(ZEUS_CAN_GPIO), IRQ_TYPE_EDGE_FALLING);
/* Setup ISA IRQs */ /* Setup ISA IRQs */
for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) { for (level = 0; level < ARRAY_SIZE(zeus_isa_irqs); level++) {
isa_irq = zeus_bit_to_irq(level); isa_irq = zeus_bit_to_irq(level);
set_irq_chip(isa_irq, &zeus_irq_chip); irq_set_chip(isa_irq, &zeus_irq_chip);
set_irq_handler(isa_irq, handle_edge_irq); irq_set_handler(isa_irq, handle_edge_irq);
set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE); set_irq_flags(isa_irq, IRQF_VALID | IRQF_PROBE);
} }
set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING); irq_set_irq_type(gpio_to_irq(ZEUS_ISA_GPIO), IRQ_TYPE_EDGE_RISING);
set_irq_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler); irq_set_chained_handler(gpio_to_irq(ZEUS_ISA_GPIO), zeus_irq_handler);
} }
......
...@@ -133,25 +133,25 @@ void __init rpc_init_irq(void) ...@@ -133,25 +133,25 @@ void __init rpc_init_irq(void)
switch (irq) { switch (irq) {
case 0 ... 7: case 0 ... 7:
set_irq_chip(irq, &iomd_a_chip); irq_set_chip(irq, &iomd_a_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, flags); set_irq_flags(irq, flags);
break; break;
case 8 ... 15: case 8 ... 15:
set_irq_chip(irq, &iomd_b_chip); irq_set_chip(irq, &iomd_b_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, flags); set_irq_flags(irq, flags);
break; break;
case 16 ... 21: case 16 ... 21:
set_irq_chip(irq, &iomd_dma_chip); irq_set_chip(irq, &iomd_dma_chip);
set_irq_handler(irq, handle_level_irq); irq_set_handler(irq, handle_level_irq);
set_irq_flags(irq, flags); set_irq_flags(irq, flags);
break; break;
case 64 ... 71: case 64 ... 71:
set_irq_chip(irq, &iomd_fiq_chip); irq_set_chip(irq, &iomd_fiq_chip);
set_irq_flags(irq, IRQF_VALID); set_irq_flags(irq, IRQF_VALID);
break; break;
} }
......
...@@ -147,15 +147,15 @@ static __init int bast_irq_init(void) ...@@ -147,15 +147,15 @@ static __init int bast_irq_init(void)
__raw_writeb(0x0, BAST_VA_PC104_IRQMASK); __raw_writeb(0x0, BAST_VA_PC104_IRQMASK);
set_irq_chained_handler(IRQ_ISA, bast_irq_pc104_demux); irq_set_chained_handler(IRQ_ISA, bast_irq_pc104_demux);
/* register our IRQs */ /* register our IRQs */
for (i = 0; i < 4; i++) { for (i = 0; i < 4; i++) {
unsigned int irqno = bast_pc104_irqs[i]; unsigned int irqno = bast_pc104_irqs[i];
set_irq_chip(irqno, &bast_pc104_chip); irq_set_chip(irqno, &bast_pc104_chip);
set_irq_handler(irqno, handle_level_irq); irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID); set_irq_flags(irqno, IRQF_VALID);
} }
} }
......
...@@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev) ...@@ -175,18 +175,18 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
unsigned int irqno; unsigned int irqno;
for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) {
set_irq_chip(irqno, &s3c2412_irq_eint0t4); irq_set_chip(irqno, &s3c2412_irq_eint0t4);
set_irq_handler(irqno, handle_edge_irq); irq_set_handler(irqno, handle_edge_irq);
set_irq_flags(irqno, IRQF_VALID); set_irq_flags(irqno, IRQF_VALID);
} }
/* add demux support for CF/SDI */ /* add demux support for CF/SDI */
set_irq_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi); irq_set_chained_handler(IRQ_S3C2412_CFSDI, s3c2412_irq_demux_cfsdi);
for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) { for (irqno = IRQ_S3C2412_SDI; irqno <= IRQ_S3C2412_CF; irqno++) {
set_irq_chip(irqno, &s3c2412_irq_cfsdi); irq_set_chip(irqno, &s3c2412_irq_cfsdi);
set_irq_handler(irqno, handle_level_irq); irq_set_handler(irqno, handle_level_irq);
set_irq_flags(irqno, IRQF_VALID); set_irq_flags(irqno, IRQF_VALID);
} }
...@@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev) ...@@ -195,7 +195,7 @@ static int s3c2412_irq_add(struct sys_device *sysdev)
s3c2412_irq_rtc_chip = s3c_irq_chip; s3c2412_irq_rtc_chip = s3c_irq_chip;
s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake; s3c2412_irq_rtc_chip.irq_set_wake = s3c2412_irq_rtc_wake;
set_irq_chip(IRQ_RTC, &s3c2412_irq_rtc_chip); irq_set_chip(IRQ_RTC, &s3c2412_irq_rtc_chip);
return 0; return 0;
} }
......
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