[PATCH] ppc64: move the lppaca defining header file

This patch just renames asm/iSeries/ItLpPaca.h to asm/lppaca.h as the
lppaca structure is no longer just legacy iSeries specific.
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>

arch/ppc64/kernel/LparData.c

@@ -16,7 +16,7 @@
 #include <asm/naca.h>
 #include <asm/abs_addr.h>
 #include <asm/iSeries/ItLpNaca.h>
-#include <asm/iSeries/ItLpPaca.h>
+#include <asm/lppaca.h>
 #include <asm/iSeries/ItLpRegSave.h>
 #include <asm/paca.h>
 #include <asm/iSeries/HvReleaseData.h>

arch/ppc64/kernel/asm-offsets.c

@@ -29,7 +29,7 @@
 #include <asm/processor.h>
 
 #include <asm/paca.h>
-#include <asm/iSeries/ItLpPaca.h>
+#include <asm/lppaca.h>
 #include <asm/iSeries/ItLpQueue.h>
 #include <asm/iSeries/HvLpEvent.h>
 #include <asm/rtas.h>

arch/ppc64/kernel/iSeries_proc.c

@@ -24,7 +24,7 @@
 #include <asm/paca.h>
 #include <asm/processor.h>
 #include <asm/time.h>
-#include <asm/iSeries/ItLpPaca.h>
+#include <asm/lppaca.h>
 #include <asm/iSeries/ItLpQueue.h>
 #include <asm/iSeries/HvCallXm.h>
 #include <asm/iSeries/IoHriMainStore.h>

arch/ppc64/kernel/lparcfg.c

@@ -27,7 +27,7 @@
 #include <linux/seq_file.h>
 #include <asm/uaccess.h>
 #include <asm/iSeries/HvLpConfig.h>
-#include <asm/iSeries/ItLpPaca.h>
+#include <asm/lppaca.h>
 #include <asm/iSeries/LparData.h>
 #include <asm/hvcall.h>
 #include <asm/cputable.h>

arch/ppc64/kernel/pacaData.c

@@ -16,7 +16,7 @@
 #include <asm/ptrace.h>
 #include <asm/page.h>
 
-#include <asm/iSeries/ItLpPaca.h>
+#include <asm/lppaca.h>
 #include <asm/iSeries/ItLpQueue.h>
 #include <asm/paca.h>
 

arch/ppc64/kernel/sysfs.c

@@ -17,7 +17,7 @@
 #include <asm/prom.h>
 #include <asm/systemcfg.h>
 #include <asm/paca.h>
-#include <asm/iSeries/ItLpPaca.h>
+#include <asm/lppaca.h>
 
 
 static DEFINE_PER_CPU(struct cpu, cpu_devices);

include/asm-ppc64/iSeries/LparData.h

@@ -25,7 +25,6 @@
 #include <asm/abs_addr.h>
 
 #include <asm/iSeries/ItLpNaca.h>
-#include <asm/iSeries/ItLpPaca.h>
 #include <asm/iSeries/ItLpRegSave.h>
 #include <asm/iSeries/HvReleaseData.h>
 #include <asm/iSeries/LparMap.h>

include/asm-ppc64/iSeries/ItLpPaca.h → include/asm-ppc64/lppaca.h

 /*
- * ItLpPaca.h
+ * lppaca.h
  * Copyright (C) 2001  Mike Corrigan IBM Corporation
- * 
+ *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
  * the Free Software Foundation; either version 2 of the License, or
  * (at your option) any later version.
- * 
+ *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
- * 
+ *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
-#ifndef _ITLPPACA_H
-#define _ITLPPACA_H
+#ifndef _ASM_LPPACA_H
+#define _ASM_LPPACA_H
 
 //=============================================================================
-//                                   
-//	This control block contains the data that is shared between the 
+//
+//	This control block contains the data that is shared between the
 //	hypervisor (PLIC) and the OS.
-//    
+//
 //
 //----------------------------------------------------------------------------
 #include <asm/types.h>
@@ -32,8 +32,8 @@ struct ItLpPaca
 {
 //=============================================================================
 // CACHE_LINE_1 0x0000 - 0x007F Contains read-only data
-// NOTE: The xDynXyz fields are fields that will be dynamically changed by 
-// PLIC when preparing to bring a processor online or when dispatching a 
+// NOTE: The xDynXyz fields are fields that will be dynamically changed by
+// PLIC when preparing to bring a processor online or when dispatching a
 // virtual processor!
 //=============================================================================
 	u32	xDesc;			// Eye catcher 0xD397D781	x00-x03
@@ -54,11 +54,11 @@ struct ItLpPaca
 	u32	xDseiData;           	// DSEI data                  	x24-x27
 	u64	xSPRG3;               	// SPRG3 value                	x28-x2F
 	u8	xRsvd1_3[80];		// Reserved			x30-x7F
-   
+
 //=============================================================================
 // CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data
 //=============================================================================
-	// This Dword contains a byte for each type of interrupt that can occur.  
+	// This Dword contains a byte for each type of interrupt that can occur.
 	// The IPI is a count while the others are just a binary 1 or 0.
 	union {
 		u64	xAnyInt;
@@ -73,17 +73,17 @@ struct ItLpPaca
 		} xFields;
 	} xIntDword;
 
-	// Whenever any fields in this Dword are set then PLIC will defer the 
-	// processing of external interrupts.  Note that PLIC will store the 
-	// XIRR directly into the xXirrValue field so that another XIRR will 
-	// not be presented until this one clears.  The layout of the low 
-	// 4-bytes of this Dword is upto SLIC - PLIC just checks whether the 
-	// entire Dword is zero or not.  A non-zero value in the low order 
-	// 2-bytes will result in SLIC being granted the highest thread 
+	// Whenever any fields in this Dword are set then PLIC will defer the
+	// processing of external interrupts.  Note that PLIC will store the
+	// XIRR directly into the xXirrValue field so that another XIRR will
+	// not be presented until this one clears.  The layout of the low
+	// 4-bytes of this Dword is upto SLIC - PLIC just checks whether the
+	// entire Dword is zero or not.  A non-zero value in the low order
+	// 2-bytes will result in SLIC being granted the highest thread
 	// priority upon return.  A 0 will return to SLIC as medium priority.
 	u64	xPlicDeferIntsArea;	// Entire Dword
 
-	// Used to pass the real SRR0/1 from PLIC to SLIC as well as to 
+	// Used to pass the real SRR0/1 from PLIC to SLIC as well as to
 	// pass the target SRR0/1 from SLIC to PLIC on a SetAsrAndRfid.
 	u64     xSavedSrr0;             // Saved SRR0                   x10-x17
 	u64     xSavedSrr1;             // Saved SRR1                   x18-x1F
@@ -100,7 +100,7 @@ struct ItLpPaca
 	volatile u32  xSavedDecr;	// Saved Decr Value             x3C-x3F
 	volatile u64  xEmulatedTimeBase;// Emulated TB for this thread  x40-x47
 	volatile u64  xCurPLICLatency;	// Unaccounted PLIC latency     x48-x4F
-	u64     xTotPLICLatency;        // Accumulated PLIC latency     x50-x57   
+	u64     xTotPLICLatency;        // Accumulated PLIC latency     x50-x57
 	u64     xWaitStateCycles;       // Wait cycles for this proc    x58-x5F
 	u64     xEndOfQuantum;          // TB at end of quantum         x60-x67
 	u64     xPDCSavedSPRG1;         // Saved SPRG1 for PMC int      x68-x6F
@@ -114,14 +114,14 @@ struct ItLpPaca
 //=============================================================================
 // CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors
 //=============================================================================
-	// This is the xYieldCount.  An "odd" value (low bit on) means that 
-	// the processor is yielded (either because of an OS yield or a PLIC 
-	// preempt).  An even value implies that the processor is currently 
+	// This is the xYieldCount.  An "odd" value (low bit on) means that
+	// the processor is yielded (either because of an OS yield or a PLIC
+	// preempt).  An even value implies that the processor is currently
 	// executing.
-	// NOTE: This value will ALWAYS be zero for dedicated processors and 
+	// NOTE: This value will ALWAYS be zero for dedicated processors and
 	// will NEVER be zero for shared processors (ie, initialized to a 1).
 	volatile u32 xYieldCount;	// PLIC increments each dispatchx00-x03
-	u8	xRsvd3_0[124];		// Reserved                     x04-x7F         
+	u8	xRsvd3_0[124];		// Reserved                     x04-x7F
 
 //=============================================================================
 // CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data
@@ -131,4 +131,4 @@ struct ItLpPaca
 
 };
 
-#endif /* _ITLPPACA_H */
+#endif /* _ASM_LPPACA_H */

include/asm-ppc64/paca.h

@@ -18,7 +18,7 @@
 
 #include	<linux/config.h>
 #include	<asm/types.h>
-#include	<asm/iSeries/ItLpPaca.h>
+#include	<asm/lppaca.h>
 #include	<asm/iSeries/ItLpRegSave.h>
 #include	<asm/mmu.h>