Commit 68e952d5 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux

Pull clock subsystem fixes from Mike Turquette.

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mturquette/linux:
  clk: fixup argument order when setting VCO parameters
  clk: socfpga: Fix incorrect sdmmc clock name
  clk: armada-370: fix tclk frequencies
  clk: nomadik: set all timers to use 2.4 MHz TIMCLK
parents 6920a1bd 2f9f64bc
...@@ -27,6 +27,14 @@ ...@@ -27,6 +27,14 @@
*/ */
#define SRC_CR 0x00U #define SRC_CR 0x00U
#define SRC_CR_T0_ENSEL BIT(15)
#define SRC_CR_T1_ENSEL BIT(17)
#define SRC_CR_T2_ENSEL BIT(19)
#define SRC_CR_T3_ENSEL BIT(21)
#define SRC_CR_T4_ENSEL BIT(23)
#define SRC_CR_T5_ENSEL BIT(25)
#define SRC_CR_T6_ENSEL BIT(27)
#define SRC_CR_T7_ENSEL BIT(29)
#define SRC_XTALCR 0x0CU #define SRC_XTALCR 0x0CU
#define SRC_XTALCR_XTALTIMEN BIT(20) #define SRC_XTALCR_XTALTIMEN BIT(20)
#define SRC_XTALCR_SXTALDIS BIT(19) #define SRC_XTALCR_SXTALDIS BIT(19)
...@@ -543,6 +551,19 @@ void __init nomadik_clk_init(void) ...@@ -543,6 +551,19 @@ void __init nomadik_clk_init(void)
__func__, np->name); __func__, np->name);
return; return;
} }
/* Set all timers to use the 2.4 MHz TIMCLK */
val = readl(src_base + SRC_CR);
val |= SRC_CR_T0_ENSEL;
val |= SRC_CR_T1_ENSEL;
val |= SRC_CR_T2_ENSEL;
val |= SRC_CR_T3_ENSEL;
val |= SRC_CR_T4_ENSEL;
val |= SRC_CR_T5_ENSEL;
val |= SRC_CR_T6_ENSEL;
val |= SRC_CR_T7_ENSEL;
writel(val, src_base + SRC_CR);
val = readl(src_base + SRC_XTALCR); val = readl(src_base + SRC_XTALCR);
pr_info("SXTALO is %s\n", pr_info("SXTALO is %s\n",
(val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled"); (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
......
...@@ -39,8 +39,8 @@ static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = { ...@@ -39,8 +39,8 @@ static const struct coreclk_ratio a370_coreclk_ratios[] __initconst = {
}; };
static const u32 a370_tclk_freqs[] __initconst = { static const u32 a370_tclk_freqs[] __initconst = {
16600000, 166000000,
20000000, 200000000,
}; };
static u32 __init a370_get_tclk_freq(void __iomem *sar) static u32 __init a370_get_tclk_freq(void __iomem *sar)
......
...@@ -49,7 +49,7 @@ ...@@ -49,7 +49,7 @@
#define SOCFPGA_L4_SP_CLK "l4_sp_clk" #define SOCFPGA_L4_SP_CLK "l4_sp_clk"
#define SOCFPGA_NAND_CLK "nand_clk" #define SOCFPGA_NAND_CLK "nand_clk"
#define SOCFPGA_NAND_X_CLK "nand_x_clk" #define SOCFPGA_NAND_X_CLK "nand_x_clk"
#define SOCFPGA_MMC_CLK "mmc_clk" #define SOCFPGA_MMC_CLK "sdmmc_clk"
#define SOCFPGA_DB_CLK "gpio_db_clk" #define SOCFPGA_DB_CLK "gpio_db_clk"
#define div_mask(width) ((1 << (width)) - 1) #define div_mask(width) ((1 << (width)) - 1)
......
...@@ -107,7 +107,7 @@ static int icst_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -107,7 +107,7 @@ static int icst_set_rate(struct clk_hw *hw, unsigned long rate,
vco = icst_hz_to_vco(icst->params, rate); vco = icst_hz_to_vco(icst->params, rate);
icst->rate = icst_hz(icst->params, vco); icst->rate = icst_hz(icst->params, vco);
vco_set(icst->vcoreg, icst->lockreg, vco); vco_set(icst->lockreg, icst->vcoreg, vco);
return 0; return 0;
} }
......
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