Commit 68f02444 authored by Ben Skeggs's avatar Ben Skeggs

drm/nouveau/nvdec/gm107: rename from gp102 implementation

NVDEC is available from GM107, and we currently only have a stub
implementation anyway, let's make it explicit.
Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 3a900a5d
...@@ -11,5 +11,5 @@ struct nvkm_nvdec { ...@@ -11,5 +11,5 @@ struct nvkm_nvdec {
struct nvkm_falcon falcon; struct nvkm_falcon falcon;
}; };
int gp102_nvdec_new(struct nvkm_device *, int, struct nvkm_nvdec **); int gm107_nvdec_new(struct nvkm_device *, int, struct nvkm_nvdec **);
#endif #endif
...@@ -2227,7 +2227,7 @@ nv132_chipset = { ...@@ -2227,7 +2227,7 @@ nv132_chipset = {
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
.gr = gp102_gr_new, .gr = gp102_gr_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = gp102_sec2_new, .sec2 = gp102_sec2_new,
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
...@@ -2264,7 +2264,7 @@ nv134_chipset = { ...@@ -2264,7 +2264,7 @@ nv134_chipset = {
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
.gr = gp104_gr_new, .gr = gp104_gr_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = gp102_sec2_new, .sec2 = gp102_sec2_new,
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
...@@ -2301,7 +2301,7 @@ nv136_chipset = { ...@@ -2301,7 +2301,7 @@ nv136_chipset = {
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
.gr = gp104_gr_new, .gr = gp104_gr_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = gp102_sec2_new, .sec2 = gp102_sec2_new,
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
...@@ -2338,7 +2338,7 @@ nv137_chipset = { ...@@ -2338,7 +2338,7 @@ nv137_chipset = {
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
.gr = gp107_gr_new, .gr = gp107_gr_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = gp102_sec2_new, .sec2 = gp102_sec2_new,
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
...@@ -2375,7 +2375,7 @@ nv138_chipset = { ...@@ -2375,7 +2375,7 @@ nv138_chipset = {
.dma = gf119_dma_new, .dma = gf119_dma_new,
.fifo = gp100_fifo_new, .fifo = gp100_fifo_new,
.gr = gp108_gr_new, .gr = gp108_gr_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = gp108_sec2_new, .sec2 = gp108_sec2_new,
.sw = gf100_sw_new, .sw = gf100_sw_new,
}; };
...@@ -2443,7 +2443,7 @@ nv140_chipset = { ...@@ -2443,7 +2443,7 @@ nv140_chipset = {
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = gv100_fifo_new, .fifo = gv100_fifo_new,
.gr = gv100_gr_new, .gr = gv100_gr_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = gp108_sec2_new, .sec2 = gp108_sec2_new,
}; };
...@@ -2478,7 +2478,7 @@ nv162_chipset = { ...@@ -2478,7 +2478,7 @@ nv162_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
}; };
...@@ -2513,7 +2513,7 @@ nv164_chipset = { ...@@ -2513,7 +2513,7 @@ nv164_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
}; };
...@@ -2548,7 +2548,7 @@ nv166_chipset = { ...@@ -2548,7 +2548,7 @@ nv166_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
}; };
...@@ -2583,7 +2583,7 @@ nv167_chipset = { ...@@ -2583,7 +2583,7 @@ nv167_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
}; };
...@@ -2618,7 +2618,7 @@ nv168_chipset = { ...@@ -2618,7 +2618,7 @@ nv168_chipset = {
.disp = tu102_disp_new, .disp = tu102_disp_new,
.dma = gv100_dma_new, .dma = gv100_dma_new,
.fifo = tu102_fifo_new, .fifo = tu102_fifo_new,
.nvdec[0] = gp102_nvdec_new, .nvdec[0] = gm107_nvdec_new,
.sec2 = tu102_sec2_new, .sec2 = tu102_sec2_new,
}; };
......
# SPDX-License-Identifier: MIT # SPDX-License-Identifier: MIT
nvkm-y += nvkm/engine/nvdec/base.o nvkm-y += nvkm/engine/nvdec/base.o
nvkm-y += nvkm/engine/nvdec/gp102.o nvkm-y += nvkm/engine/nvdec/gm107.o
...@@ -22,7 +22,7 @@ ...@@ -22,7 +22,7 @@
#include "priv.h" #include "priv.h"
static const struct nvkm_falcon_func static const struct nvkm_falcon_func
gp102_nvdec_flcn = { gm107_nvdec_flcn = {
.load_imem = nvkm_falcon_v1_load_imem, .load_imem = nvkm_falcon_v1_load_imem,
.load_dmem = nvkm_falcon_v1_load_dmem, .load_dmem = nvkm_falcon_v1_load_dmem,
.read_dmem = nvkm_falcon_v1_read_dmem, .read_dmem = nvkm_falcon_v1_read_dmem,
...@@ -36,26 +36,26 @@ gp102_nvdec_flcn = { ...@@ -36,26 +36,26 @@ gp102_nvdec_flcn = {
}; };
static const struct nvkm_nvdec_func static const struct nvkm_nvdec_func
gp102_nvdec = { gm107_nvdec = {
.flcn = &gp102_nvdec_flcn, .flcn = &gm107_nvdec_flcn,
}; };
static int static int
gp102_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver, gm107_nvdec_nofw(struct nvkm_nvdec *nvdec, int ver,
const struct nvkm_nvdec_fwif *fwif) const struct nvkm_nvdec_fwif *fwif)
{ {
return 0; return 0;
} }
static const struct nvkm_nvdec_fwif static const struct nvkm_nvdec_fwif
gp102_nvdec_fwif[] = { gm107_nvdec_fwif[] = {
{ -1, gp102_nvdec_nofw, &gp102_nvdec }, { -1, gm107_nvdec_nofw, &gm107_nvdec },
{} {}
}; };
int int
gp102_nvdec_new(struct nvkm_device *device, int index, gm107_nvdec_new(struct nvkm_device *device, int index,
struct nvkm_nvdec **pnvdec) struct nvkm_nvdec **pnvdec)
{ {
return nvkm_nvdec_new_(gp102_nvdec_fwif, device, index, pnvdec); return nvkm_nvdec_new_(gm107_nvdec_fwif, device, index, pnvdec);
} }
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment