Commit 6bbb049e authored by Dave Jones's avatar Dave Jones

[PATCH] wd33c93 sync up with 2.4

parent 9f58fa60
...@@ -1419,12 +1419,32 @@ DB(DB_INTR,printk("} ")) ...@@ -1419,12 +1419,32 @@ DB(DB_INTR,printk("} "))
static void reset_wd33c93(struct Scsi_Host *instance) void reset_wd33c93(struct Scsi_Host *instance)
{ {
struct WD33C93_hostdata *hostdata = (struct WD33C93_hostdata *)instance->hostdata; struct WD33C93_hostdata *hostdata = (struct WD33C93_hostdata *)instance->hostdata;
const wd33c93_regs regs = hostdata->regs; const wd33c93_regs regs = hostdata->regs;
uchar sr; uchar sr;
#ifdef CONFIG_SGI_IP22
{
int busycount = 0;
extern void sgiwd93_reset(unsigned long);
/* wait 'til the chip gets some time for us */
while ((READ_AUX_STAT() & ASR_BSY) && busycount++ < 100)
udelay (10);
/*
* there are scsi devices out there, which manage to lock up
* the wd33c93 in a busy condition. In this state it won't
* accept the reset command. The only way to solve this is to
* give the chip a hardware reset (if possible). The code below
* does this for the SGI Indy, where this is possible
*/
/* still busy ? */
if (READ_AUX_STAT() & ASR_BSY)
sgiwd93_reset(instance->base); /* yeah, give it the hard one */
}
#endif
write_wd33c93(regs, WD_OWN_ID, OWNID_EAF | OWNID_RAF | write_wd33c93(regs, WD_OWN_ID, OWNID_EAF | OWNID_RAF |
instance->this_id | hostdata->clock_freq); instance->this_id | hostdata->clock_freq);
write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED); write_wd33c93(regs, WD_CONTROL, CTRL_IDI | CTRL_EDI | CTRL_POLLED);
......
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