Commit 6d86415e authored by Andi Kleen's avatar Andi Kleen Committed by Linus Torvalds

[PATCH] Hammer aperture driver for 2.5.38

Add an AGP driver for the AGP aperture in the northbridge of the AMD Hammer.
The AGP driver works for both 32bit and 64bit kernels.

It also adds some hooks to the AGP driver to allow the x86-64 GART based
IOMMU code to share the aperture with AGP. The hooks are intentionally kept
minimalistic. In addition it needs some Config.in hackery, because AGP cannot
be modular in this case, because the IOMMU needs to control its startup and
it runs early when PCI is initialized.

The original AGP driver was done by Dave Jones, I added the IOMMU support.
parent a790a5cb
dep_tristate '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP
if [ "$CONFIG_GART_IOMMU" = "y" ]; then
dep_bool '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP
else
dep_tristate '/dev/agpgart (AGP Support)' CONFIG_AGP $CONFIG_DRM_AGP
fi
if [ "$CONFIG_AGP" != "n" ]; then
bool ' Intel 440LX/BX/GX and I815/I820/I830M/I830MP/I840/I845/I850/I860 support' CONFIG_AGP_INTEL
bool ' Intel I810/I815/I830M (on-board) support' CONFIG_AGP_I810
......@@ -7,6 +12,9 @@ if [ "$CONFIG_AGP" != "n" ]; then
bool ' Generic SiS support' CONFIG_AGP_SIS
bool ' ALI chipset support' CONFIG_AGP_ALI
bool ' Serverworks LE/HE support' CONFIG_AGP_SWORKS
if [ "$CONFIG_GART_IOMMU" != "y" ]; then
bool ' AMD 8151 support' CONFIG_AGP_AMD_8151
fi
if [ "$CONFIG_IA64" = "y" ]; then
bool ' Intel 460GX support' CONFIG_AGP_I460
bool ' HP ZX1 AGP support' CONFIG_AGP_HP_ZX1
......
......@@ -16,6 +16,7 @@ agpgart-$(CONFIG_AGP_ALI) += ali-agp.o
agpgart-$(CONFIG_AGP_SWORKS) += sworks-agp.o
agpgart-$(CONFIG_AGP_I460) += i460-agp.o
agpgart-$(CONFIG_AGP_HP_ZX1) += hp-agp.o
agpgart-$(CONFIG_AGP_AMD_8151) += k8-agp.o
agpgart-objs := $(agpgart-y)
obj-$(CONFIG_AGP) += agpgart.o
......
......@@ -50,6 +50,9 @@ EXPORT_SYMBOL(agp_backend_release);
struct agp_bridge_data agp_bridge = { type: NOT_SUPPORTED };
static int agp_try_unsupported __initdata = 0;
int agp_memory_reserved;
__u32 *agp_gatt_table;
int agp_backend_acquire(void)
{
if (agp_bridge.type == NOT_SUPPORTED)
......@@ -243,7 +246,7 @@ static int agp_return_size(void)
/* Routine to copy over information structure */
void agp_copy_info(agp_kern_info * info)
int agp_copy_info(agp_kern_info * info)
{
unsigned long page_mask = 0;
int i;
......@@ -251,7 +254,7 @@ void agp_copy_info(agp_kern_info * info)
memset(info, 0, sizeof(agp_kern_info));
if (agp_bridge.type == NOT_SUPPORTED) {
info->chipset = agp_bridge.type;
return;
return -EIO;
}
info->version.major = agp_bridge.version->major;
info->version.minor = agp_bridge.version->minor;
......@@ -268,6 +271,7 @@ void agp_copy_info(agp_kern_info * info)
page_mask |= agp_bridge.mask_memory(page_mask, i);
info->page_mask = ~page_mask;
return 0;
}
/* End - Routine to copy over information structure */
......@@ -518,6 +522,7 @@ int agp_generic_create_gatt_table(void)
SetPageReserved(page);
agp_bridge.gatt_table_real = (unsigned long *) table;
agp_gatt_table = (void *)table;
CACHE_FLUSH();
agp_bridge.gatt_table = ioremap_nocache(virt_to_phys(table),
(PAGE_SIZE * (1 << page_order)));
......@@ -625,6 +630,9 @@ int agp_generic_insert_memory(agp_memory * mem, off_t pg_start, int type)
break;
}
num_entries -= agp_memory_reserved/PAGE_SIZE;
if (num_entries < 0) num_entries = 0;
if (type != 0 || mem->type != 0) {
/* The generic routines know nothing of memory types */
return -EINVAL;
......@@ -824,6 +832,17 @@ static struct {
},
#endif /* CONFIG_AGP_ALI */
#ifdef CONFIG_AGP_AMD_8151
{
.device_id = PCI_DEVICE_ID_AMD_8151_0,
.vendor_id = PCI_VENDOR_ID_AMD,
.chipset = AMD_8151,
.vendor_name = "AMD",
.chipset_name = "8151",
.chipset_setup = amd_8151_setup
},
#endif /* CONFIG_AGP_AMD */
#ifdef CONFIG_AGP_AMD
{
.device_id = PCI_DEVICE_ID_AMD_FE_GATE_7006,
......@@ -858,7 +877,6 @@ static struct {
.chipset_setup = amd_irongate_setup,
},
#endif /* CONFIG_AGP_AMD */
#ifdef CONFIG_AGP_INTEL
{
.device_id = PCI_DEVICE_ID_INTEL_82443LX_0,
......@@ -1632,7 +1650,7 @@ static struct pci_driver agp_pci_driver = {
.probe = agp_probe,
};
static int __init agp_init(void)
int __init agp_init(void)
{
int ret_val;
......@@ -1658,5 +1676,7 @@ static void __exit agp_cleanup(void)
}
}
#ifndef CONFIG_GART_IOMMU
module_init(agp_init);
module_exit(agp_cleanup);
#endif
......@@ -49,6 +49,7 @@ void agp_free_key(int key);
/* chipset specific init routines. */
int __init ali_generic_setup (struct pci_dev *pdev);
int __init amd_irongate_setup (struct pci_dev *pdev);
int __init amd_8151_setup (struct pci_dev *pdev);
int __init hp_zx1_setup (struct pci_dev *pdev);
int __init intel_i460_setup (struct pci_dev *pdev);
int __init intel_generic_setup (struct pci_dev *pdev);
......@@ -319,6 +320,22 @@ struct agp_bridge_data {
#define AMD_TLBFLUSH 0x0c /* In mmio region (32-bit register) */
#define AMD_CACHEENTRY 0x10 /* In mmio region (32-bit register) */
#define AMD_8151_APSIZE 0xb4
#define AMD_8151_GARTBLOCK 0xb8
#define AMD_X86_64_GARTAPERTURECTL 0x90
#define AMD_X86_64_GARTAPERTUREBASE 0x94
#define AMD_X86_64_GARTTABLEBASE 0x98
#define AMD_X86_64_GARTCACHECTL 0x9c
#define AMD_X86_64_GARTEN 1<<0
#define AMD_8151_VMAPERTURE 0x10
#define AMD_8151_AGP_CTL 0xb0
#define AMD_8151_APERTURESIZE 0xb4
#define AMD_8151_GARTPTR 0xb8
#define AMD_8151_GTLBEN 1<<7
#define AMD_8151_APEREN 1<<8
/* ALi registers */
#define ALI_APBASE 0x10
#define ALI_AGPCTRL 0xb8
......
This diff is collapsed.
......@@ -66,6 +66,7 @@ enum chipset_type {
AMD_IRONGATE,
AMD_761,
AMD_762,
AMD_8151,
ALI_M1541,
ALI_M1621,
ALI_M1631,
......@@ -161,7 +162,7 @@ extern agp_memory *agp_allocate_memory(size_t, u32);
*
*/
extern void agp_copy_info(agp_kern_info *);
extern int agp_copy_info(agp_kern_info *);
/*
* agp_copy_info :
......@@ -257,7 +258,7 @@ typedef struct {
void (*enable)(u32);
int (*acquire)(void);
void (*release)(void);
void (*copy_info)(agp_kern_info *);
int (*copy_info)(agp_kern_info *);
} drm_agp_t;
extern const drm_agp_t *drm_agp_p;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment