Commit 702e7a56 authored by Paulo Zanoni's avatar Paulo Zanoni Committed by Daniel Vetter

drm/i915: convert PIPECONF to use transcoder instead of pipe

Because the PIPECONF register is actually part of the CPU transcoder,
not the CPU pipe.

Ideally we would also rename PIPECONF to TRANSCONF to remind people
that they should use the transcoder instead of the pipe, but let's
keep it like this for now since most Gens still name it PIPECONF.
Signed-off-by: default avatarPaulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent e28d54cb
...@@ -122,7 +122,10 @@ static int ...@@ -122,7 +122,10 @@ static int
i915_pipe_enabled(struct drm_device *dev, int pipe) i915_pipe_enabled(struct drm_device *dev, int pipe)
{ {
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private; drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
return I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE; enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
} }
/* Called from drm generic code, passed a 'crtc', which /* Called from drm generic code, passed a 'crtc', which
......
...@@ -2721,7 +2721,7 @@ ...@@ -2721,7 +2721,7 @@
#define PIPE_12BPC (3 << 5) #define PIPE_12BPC (3 << 5)
#define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC) #define PIPESRC(pipe) _PIPE(pipe, _PIPEASRC, _PIPEBSRC)
#define PIPECONF(pipe) _PIPE(pipe, _PIPEACONF, _PIPEBCONF) #define PIPECONF(tran) _TRANSCODER(tran, _PIPEACONF, _PIPEBCONF)
#define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL) #define PIPEDSL(pipe) _PIPE(pipe, _PIPEADSL, _PIPEBDSL)
#define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH) #define PIPEFRAME(pipe) _PIPE(pipe, _PIPEAFRAMEHIGH, _PIPEBFRAMEHIGH)
#define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL) #define PIPEFRAMEPIXEL(pipe) _PIPE(pipe, _PIPEAFRAMEPIXEL, _PIPEBFRAMEPIXEL)
......
...@@ -1018,9 +1018,11 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe) ...@@ -1018,9 +1018,11 @@ void intel_wait_for_vblank(struct drm_device *dev, int pipe)
void intel_wait_for_pipe_off(struct drm_device *dev, int pipe) void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
{ {
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
if (INTEL_INFO(dev)->gen >= 4) { if (INTEL_INFO(dev)->gen >= 4) {
int reg = PIPECONF(pipe); int reg = PIPECONF(cpu_transcoder);
/* Wait for the Pipe State to go off */ /* Wait for the Pipe State to go off */
if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0, if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
...@@ -1233,12 +1235,14 @@ void assert_pipe(struct drm_i915_private *dev_priv, ...@@ -1233,12 +1235,14 @@ void assert_pipe(struct drm_i915_private *dev_priv,
int reg; int reg;
u32 val; u32 val;
bool cur_state; bool cur_state;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
/* if we need the pipe A quirk it must be always on */ /* if we need the pipe A quirk it must be always on */
if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE) if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
state = true; state = true;
reg = PIPECONF(pipe); reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg); val = I915_READ(reg);
cur_state = !!(val & PIPECONF_ENABLE); cur_state = !!(val & PIPECONF_ENABLE);
WARN(cur_state != state, WARN(cur_state != state,
...@@ -1756,6 +1760,8 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv, ...@@ -1756,6 +1760,8 @@ static void intel_disable_transcoder(struct drm_i915_private *dev_priv,
static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
bool pch_port) bool pch_port)
{ {
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
int reg; int reg;
u32 val; u32 val;
...@@ -1775,7 +1781,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, ...@@ -1775,7 +1781,7 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
/* FIXME: assert CPU port conditions for SNB+ */ /* FIXME: assert CPU port conditions for SNB+ */
} }
reg = PIPECONF(pipe); reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg); val = I915_READ(reg);
if (val & PIPECONF_ENABLE) if (val & PIPECONF_ENABLE)
return; return;
...@@ -1799,6 +1805,8 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, ...@@ -1799,6 +1805,8 @@ static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
static void intel_disable_pipe(struct drm_i915_private *dev_priv, static void intel_disable_pipe(struct drm_i915_private *dev_priv,
enum pipe pipe) enum pipe pipe)
{ {
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
int reg; int reg;
u32 val; u32 val;
...@@ -1812,7 +1820,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv, ...@@ -1812,7 +1820,7 @@ static void intel_disable_pipe(struct drm_i915_private *dev_priv,
if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE)) if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
return; return;
reg = PIPECONF(pipe); reg = PIPECONF(cpu_transcoder);
val = I915_READ(reg); val = I915_READ(reg);
if ((val & PIPECONF_ENABLE) == 0) if ((val & PIPECONF_ENABLE) == 0)
return; return;
...@@ -4898,10 +4906,10 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc, ...@@ -4898,10 +4906,10 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
{ {
struct drm_i915_private *dev_priv = crtc->dev->dev_private; struct drm_i915_private *dev_priv = crtc->dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
int pipe = intel_crtc->pipe; enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
uint32_t val; uint32_t val;
val = I915_READ(PIPECONF(pipe)); val = I915_READ(PIPECONF(cpu_transcoder));
val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK); val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
if (dither) if (dither)
...@@ -4913,8 +4921,8 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc, ...@@ -4913,8 +4921,8 @@ static void haswell_set_pipeconf(struct drm_crtc *crtc,
else else
val |= PIPECONF_PROGRESSIVE; val |= PIPECONF_PROGRESSIVE;
I915_WRITE(PIPECONF(pipe), val); I915_WRITE(PIPECONF(cpu_transcoder), val);
POSTING_READ(PIPECONF(pipe)); POSTING_READ(PIPECONF(cpu_transcoder));
} }
static bool ironlake_compute_clocks(struct drm_crtc *crtc, static bool ironlake_compute_clocks(struct drm_crtc *crtc,
...@@ -5388,7 +5396,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc, ...@@ -5388,7 +5396,7 @@ static int haswell_crtc_mode_set(struct drm_crtc *crtc,
WARN(num_connectors != 1, "%d connectors attached to pipe %c\n", WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
num_connectors, pipe_name(pipe)); num_connectors, pipe_name(pipe));
WARN_ON(I915_READ(PIPECONF(pipe)) & WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
(PIPECONF_ENABLE | I965_PIPECONF_ACTIVE)); (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE); WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
...@@ -8562,7 +8570,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc) ...@@ -8562,7 +8570,7 @@ static void intel_sanitize_crtc(struct intel_crtc *crtc)
u32 reg; u32 reg;
/* Clear any frame start delays used for debugging left by the BIOS */ /* Clear any frame start delays used for debugging left by the BIOS */
reg = PIPECONF(crtc->pipe); reg = PIPECONF(crtc->cpu_transcoder);
I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK); I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
/* We need to sanitize the plane -> pipe mapping first because this will /* We need to sanitize the plane -> pipe mapping first because this will
...@@ -8718,7 +8726,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev) ...@@ -8718,7 +8726,7 @@ void intel_modeset_setup_hw_state(struct drm_device *dev)
for_each_pipe(pipe) { for_each_pipe(pipe) {
crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]); crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
tmp = I915_READ(PIPECONF(pipe)); tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
if (tmp & PIPECONF_ENABLE) if (tmp & PIPECONF_ENABLE)
crtc->active = true; crtc->active = true;
else else
...@@ -8912,6 +8920,7 @@ intel_display_capture_error_state(struct drm_device *dev) ...@@ -8912,6 +8920,7 @@ intel_display_capture_error_state(struct drm_device *dev)
{ {
drm_i915_private_t *dev_priv = dev->dev_private; drm_i915_private_t *dev_priv = dev->dev_private;
struct intel_display_error_state *error; struct intel_display_error_state *error;
enum transcoder cpu_transcoder;
int i; int i;
error = kmalloc(sizeof(*error), GFP_ATOMIC); error = kmalloc(sizeof(*error), GFP_ATOMIC);
...@@ -8919,6 +8928,8 @@ intel_display_capture_error_state(struct drm_device *dev) ...@@ -8919,6 +8928,8 @@ intel_display_capture_error_state(struct drm_device *dev)
return NULL; return NULL;
for_each_pipe(i) { for_each_pipe(i) {
cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
error->cursor[i].control = I915_READ(CURCNTR(i)); error->cursor[i].control = I915_READ(CURCNTR(i));
error->cursor[i].position = I915_READ(CURPOS(i)); error->cursor[i].position = I915_READ(CURPOS(i));
error->cursor[i].base = I915_READ(CURBASE(i)); error->cursor[i].base = I915_READ(CURBASE(i));
...@@ -8933,7 +8944,7 @@ intel_display_capture_error_state(struct drm_device *dev) ...@@ -8933,7 +8944,7 @@ intel_display_capture_error_state(struct drm_device *dev)
error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i)); error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
} }
error->pipe[i].conf = I915_READ(PIPECONF(i)); error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
error->pipe[i].source = I915_READ(PIPESRC(i)); error->pipe[i].source = I915_READ(PIPESRC(i));
error->pipe[i].htotal = I915_READ(HTOTAL(i)); error->pipe[i].htotal = I915_READ(HTOTAL(i));
error->pipe[i].hblank = I915_READ(HBLANK(i)); error->pipe[i].hblank = I915_READ(HBLANK(i));
......
...@@ -424,6 +424,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, ...@@ -424,6 +424,8 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
struct intel_framebuffer *intel_fb; struct intel_framebuffer *intel_fb;
struct drm_i915_gem_object *obj, *old_obj; struct drm_i915_gem_object *obj, *old_obj;
int pipe = intel_plane->pipe; int pipe = intel_plane->pipe;
enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
pipe);
int ret = 0; int ret = 0;
int x = src_x >> 16, y = src_y >> 16; int x = src_x >> 16, y = src_y >> 16;
int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay; int primary_w = crtc->mode.hdisplay, primary_h = crtc->mode.vdisplay;
...@@ -438,7 +440,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc, ...@@ -438,7 +440,7 @@ intel_update_plane(struct drm_plane *plane, struct drm_crtc *crtc,
src_h = src_h >> 16; src_h = src_h >> 16;
/* Pipe must be running... */ /* Pipe must be running... */
if (!(I915_READ(PIPECONF(pipe)) & PIPECONF_ENABLE)) if (!(I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE))
return -EINVAL; return -EINVAL;
if (crtc_x >= primary_w || crtc_y >= primary_h) if (crtc_x >= primary_w || crtc_y >= primary_h)
......
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