Commit 7077f4cc authored by Ralph Sennhauser's avatar Ralph Sennhauser Committed by Linus Walleij

gpio: mvebu: checkpatch: block comment fixes

Fix issues in block comments reported by checkpatch.
Signed-off-by: default avatarRalph Sennhauser <ralph.sennhauser@gmail.com>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
parent 6798d727
...@@ -62,9 +62,11 @@ ...@@ -62,9 +62,11 @@
#define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18) #define GPIO_EDGE_MASK_MV78200_OFF(cpu) ((cpu) ? 0x30 : 0x18)
#define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C) #define GPIO_LEVEL_MASK_MV78200_OFF(cpu) ((cpu) ? 0x34 : 0x1C)
/* The Armada XP has per-CPU registers for interrupt cause, interrupt /*
* The Armada XP has per-CPU registers for interrupt cause, interrupt
* mask and interrupt level mask. Those are relative to the * mask and interrupt level mask. Those are relative to the
* percpu_membase. */ * percpu_membase.
*/
#define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4) #define GPIO_EDGE_CAUSE_ARMADAXP_OFF(cpu) ((cpu) * 0x4)
#define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4) #define GPIO_EDGE_MASK_ARMADAXP_OFF(cpu) (0x10 + (cpu) * 0x4)
#define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4) #define GPIO_LEVEL_MASK_ARMADAXP_OFF(cpu) (0x20 + (cpu) * 0x4)
...@@ -239,8 +241,10 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin) ...@@ -239,8 +241,10 @@ static int mvebu_gpio_direction_input(struct gpio_chip *chip, unsigned pin)
int ret; int ret;
u32 u; u32 u;
/* Check with the pinctrl driver whether this pin is usable as /*
* an input GPIO */ * Check with the pinctrl driver whether this pin is usable as
* an input GPIO
*/
ret = pinctrl_gpio_direction_input(chip->base + pin); ret = pinctrl_gpio_direction_input(chip->base + pin);
if (ret) if (ret)
return ret; return ret;
...@@ -262,8 +266,10 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin, ...@@ -262,8 +266,10 @@ static int mvebu_gpio_direction_output(struct gpio_chip *chip, unsigned pin,
int ret; int ret;
u32 u; u32 u;
/* Check with the pinctrl driver whether this pin is usable as /*
* an output GPIO */ * Check with the pinctrl driver whether this pin is usable as
* an output GPIO
*/
ret = pinctrl_gpio_direction_output(chip->base + pin); ret = pinctrl_gpio_direction_output(chip->base + pin);
if (ret) if (ret)
return ret; return ret;
...@@ -712,8 +718,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev) ...@@ -712,8 +718,10 @@ static int mvebu_gpio_probe(struct platform_device *pdev)
if (IS_ERR(mvchip->membase)) if (IS_ERR(mvchip->membase))
return PTR_ERR(mvchip->membase); return PTR_ERR(mvchip->membase);
/* The Armada XP has a second range of registers for the /*
* per-CPU registers */ * The Armada XP has a second range of registers for the
* per-CPU registers
*/
if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) { if (soc_variant == MVEBU_GPIO_SOC_VARIANT_ARMADAXP) {
res = platform_get_resource(pdev, IORESOURCE_MEM, 1); res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev, mvchip->percpu_membase = devm_ioremap_resource(&pdev->dev,
......
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