Commit 70c4fa22 authored by Thomas Gleixner's avatar Thomas Gleixner

arm: msm: Use proper irq accessor functions

Signed-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
parent 8c04a176
...@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -275,14 +275,14 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
if (flow_type & IRQ_TYPE_EDGE_BOTH) { if (flow_type & IRQ_TYPE_EDGE_BOTH) {
bits |= BIT(INTR_DECT_CTL); bits |= BIT(INTR_DECT_CTL);
irq_desc[irq].handle_irq = handle_edge_irq; __irq_set_handler_locked(d->irq, handle_edge_irq);
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
__set_bit(gpio, msm_gpio.dual_edge_irqs); __set_bit(gpio, msm_gpio.dual_edge_irqs);
else else
__clear_bit(gpio, msm_gpio.dual_edge_irqs); __clear_bit(gpio, msm_gpio.dual_edge_irqs);
} else { } else {
bits &= ~BIT(INTR_DECT_CTL); bits &= ~BIT(INTR_DECT_CTL);
irq_desc[irq].handle_irq = handle_level_irq; __irq_set_handler_locked(d->irq, handle_level_irq);
__clear_bit(gpio, msm_gpio.dual_edge_irqs); __clear_bit(gpio, msm_gpio.dual_edge_irqs);
} }
......
...@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -293,10 +293,10 @@ static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int flow_type)
val = readl(msm_chip->regs.int_edge); val = readl(msm_chip->regs.int_edge);
if (flow_type & IRQ_TYPE_EDGE_BOTH) { if (flow_type & IRQ_TYPE_EDGE_BOTH) {
writel(val | mask, msm_chip->regs.int_edge); writel(val | mask, msm_chip->regs.int_edge);
irq_desc[d->irq].handle_irq = handle_edge_irq; __irq_set_handler_locked(d->irq, handle_edge_irq);
} else { } else {
writel(val & ~mask, msm_chip->regs.int_edge); writel(val & ~mask, msm_chip->regs.int_edge);
irq_desc[d->irq].handle_irq = handle_level_irq; __irq_set_handler_locked(d->irq, handle_level_irq);
} }
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
msm_chip->both_edge_detect |= mask; msm_chip->both_edge_detect |= mask;
......
...@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -313,11 +313,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
type = msm_irq_shadow_reg[index].int_type; type = msm_irq_shadow_reg[index].int_type;
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
type |= b; type |= b;
irq_desc[d->irq].handle_irq = handle_edge_irq; __irq_set_handler_locked(d->irq, handle_edge_irq);
} }
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
type &= ~b; type &= ~b;
irq_desc[d->irq].handle_irq = handle_level_irq; __irq_set_handler_locked(d->irq, handle_level_irq);
} }
writel(type, treg); writel(type, treg);
msm_irq_shadow_reg[index].int_type = type; msm_irq_shadow_reg[index].int_type = type;
......
...@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -100,11 +100,11 @@ static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
writel(readl(treg) | b, treg); writel(readl(treg) | b, treg);
irq_desc[d->irq].handle_irq = handle_edge_irq; __irq_set_handler_locked(d->irq, handle_edge_irq);
} }
if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) { if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
writel(readl(treg) & (~b), treg); writel(readl(treg) & (~b), treg);
irq_desc[d->irq].handle_irq = handle_level_irq; __irq_set_handler_locked(d->irq, handle_level_irq);
} }
return 0; return 0;
} }
......
...@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type) ...@@ -105,10 +105,10 @@ static int sirc_irq_set_type(struct irq_data *d, unsigned int flow_type)
val = readl(sirc_regs.int_type); val = readl(sirc_regs.int_type);
if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
val |= mask; val |= mask;
irq_desc[d->irq].handle_irq = handle_edge_irq; __irq_set_handler_locked(d->irq, handle_edge_irq);
} else { } else {
val &= ~mask; val &= ~mask;
irq_desc[d->irq].handle_irq = handle_level_irq; __irq_set_handler_locked(d->irq, handle_level_irq);
} }
writel(val, sirc_regs.int_type); writel(val, sirc_regs.int_type);
......
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