Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux

arch/arm/mach-iop3xx/Kconfig

@@ -25,6 +25,13 @@ config ARCH_IQ80331
 	  Say Y here if you want to run your kernel on the Intel IQ80331
 	  evaluation kit for the IOP331 chipset.
 
+config MACH_IQ80332
+	bool "Enable support for IQ80332"
+	select ARCH_IOP331
+	help
+	  Say Y here if you want to run your kernel on the Intel IQ80332
+	  evaluation kit for the IOP332 chipset
+
 config ARCH_EP80219
     bool "Enable support for EP80219"
     select ARCH_IOP321
@@ -41,10 +48,16 @@ config ARCH_IOP331
 	bool
 	default ARCH_IQ80331
 	help
-	  The IQ80331 uses the IOP331 variant.
+	  The IQ80331, IQ80332, and IQ80333 uses the IOP331 variant.
 
 comment "IOP3xx Chipset Features"
 
-endmenu
+config IOP331_STEPD
+	bool "Chip stepping D of the IOP80331 processor or IOP80333"
+	depends on (ARCH_IOP331)
+	help
+		  Say Y here if you have StepD of the IOP80331 or IOP8033
+		  based platforms.
 
+endmenu
 endif

arch/arm/mach-iop3xx/Makefile

@@ -19,3 +19,5 @@ obj-$(CONFIG_ARCH_IQ80321) += iq80321-mm.o iq80321-pci.o
 obj-$(CONFIG_ARCH_IQ31244) += iq31244-mm.o iq31244-pci.o
 
 obj-$(CONFIG_ARCH_IQ80331) += iq80331-mm.o iq80331-pci.o
+
+obj-$(CONFIG_MACH_IQ80332) += iq80332-mm.o iq80332-pci.o

arch/arm/mach-iop3xx/iop321-pci.c

@@ -197,14 +197,6 @@ struct pci_bus *iop321_scan_bus(int nr, struct pci_sys_data *sys)
 
 void iop321_init(void)
 {
-#if CONFIG_ARCH_EP80219
-    *IOP321_ATUCR = 0x2;
-    *IOP321_OIOWTVR = 0x90000000;
-    *IOP321_IABAR0  = 0x00000004;
-    *IOP321_IABAR2  = 0xa000000c;
-    *IOP321_IALR2   = 0xe0000000;
-#endif
-
 	DBG("PCI:  Intel 80321 PCI init code.\n");
 	DBG("\tATU: IOP321_ATUCMD=0x%04x\n", *IOP321_ATUCMD);
 	DBG("\tATU: IOP321_OMWTVR0=0x%04x, IOP321_OIOWTVR=0x%04x\n",

arch/arm/mach-iop3xx/iop321-setup.c

@@ -3,6 +3,7 @@
  *
  * Author: Nicolas Pitre <nico@cam.org>
  * Copyright (C) 2001 MontaVista Software, Inc.
+ * Copyright (C) 2004 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -40,10 +41,10 @@ static struct map_desc iop321_std_desc[] __initdata = {
  /* virtual     physical      length      type */
 
  /* mem mapped registers */
- { IOP321_VIRT_MEM_BASE,  IOP321_PHY_MEM_BASE,   0x00002000,  MT_DEVICE },
+ { IOP321_VIRT_MEM_BASE,  IOP321_PHYS_MEM_BASE,   0x00002000,  MT_DEVICE },
 
  /* PCI IO space */
- { 0xfe000000,  0x90000000,   0x00020000,  MT_DEVICE }
+ { IOP321_PCI_LOWER_IO_VA,  IOP321_PCI_LOWER_IO_PA,   IOP321_PCI_IO_WINDOW_SIZE,  MT_DEVICE }
 };
 
 #ifdef CONFIG_ARCH_IQ80321
@@ -71,6 +72,60 @@ static struct uart_port iop321_serial_ports[] = {
 	}
 };
 
+static struct resource iop32x_i2c_0_resources[] = {
+	[0] = {
+		.start = 0xfffff680,
+		.end = 0xfffff698,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_IOP321_I2C_0,
+		.end = IRQ_IOP321_I2C_0,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
+static struct resource iop32x_i2c_1_resources[] = {
+	[0] = {
+		.start = 0xfffff6a0,
+		.end = 0xfffff6b8,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_IOP321_I2C_1,
+		.end = IRQ_IOP321_I2C_1,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
+static struct platform_device iop32x_i2c_0_controller = {
+	.name = "IOP3xx-I2C",
+	.id = 0,
+	.num_resources = 2,
+	.resource = iop32x_i2c_0_resources
+};
+
+static struct platform_device iop32x_i2c_1_controller = {
+	.name = "IOP3xx-I2C",
+	.id = 1,
+	.num_resources = 2,
+	.resource = iop32x_i2c_1_resources
+};
+
+static struct platform_device *iop32x_devices[] __initdata = {
+	&iop32x_i2c_0_controller,
+	&iop32x_i2c_1_controller
+};
+
+void __init iop32x_init(void)
+{
+	if(iop_is_321())
+	{
+		platform_add_devices(iop32x_devices,
+				ARRAY_SIZE(iop32x_devices));
+	}
+}
+
 void __init iop321_map_io(void)
 {
 	iotable_init(iop321_std_desc, ARRAY_SIZE(iop321_std_desc));
@@ -97,6 +152,7 @@ MACHINE_START(IQ80321, "Intel IQ80321")
 	INITIRQ(iop321_init_irq)
 	.timer		= &iop321_timer,
     BOOT_PARAMS(0xa0000100)
+	INIT_MACHINE(iop32x_init)
 MACHINE_END
 #elif defined(CONFIG_ARCH_IQ31244)
 MACHINE_START(IQ31244, "Intel IQ31244")
@@ -106,6 +162,7 @@ MACHINE_START(IQ31244, "Intel IQ31244")
     INITIRQ(iop321_init_irq)
 	.timer		= &iop321_timer,
     BOOT_PARAMS(0xa0000100)
+	INIT_MACHINE(iop32x_init)
 MACHINE_END
 #else
 #error No machine descriptor defined for this IOP3XX implementation

arch/arm/mach-iop3xx/iop331-setup.c

@@ -12,6 +12,7 @@
 #include <linux/mm.h>
 #include <linux/init.h>
 #include <linux/config.h>
+#include <linux/init.h>
 #include <linux/major.h>
 #include <linux/fs.h>
 #include <linux/device.h>
@@ -42,13 +43,13 @@ static struct map_desc iop331_std_desc[] __initdata = {
  { IOP331_VIRT_MEM_BASE,  IOP331_PHYS_MEM_BASE,   0x00002000,  MT_DEVICE },
 
  /* PCI IO space */
- { 0xfe000000,  0x90000000,   0x00020000,  MT_DEVICE }
+ { IOP331_PCI_LOWER_IO_VA,  IOP331_PCI_LOWER_IO_PA,   IOP331_PCI_IO_WINDOW_SIZE,  MT_DEVICE }
 };
 
 static struct uart_port iop331_serial_ports[] = {
 	{
-		.membase	= (char*)(IQ80331_UART0_VIRT),
-		.mapbase	= (IQ80331_UART0_PHYS),
+		.membase	= (char*)(IOP331_UART0_VIRT),
+		.mapbase	= (IOP331_UART0_PHYS),
 		.irq		= IRQ_IOP331_UART0,
 		.flags		= UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
@@ -58,8 +59,8 @@ static struct uart_port iop331_serial_ports[] = {
 		.type		= PORT_XSCALE,
 		.fifosize	= 32
 	} , {
-		.membase	= (char*)(IQ80331_UART1_VIRT),
-		.mapbase	= (IQ80331_UART1_PHYS),
+		.membase	= (char*)(IOP331_UART1_VIRT),
+		.mapbase	= (IOP331_UART1_PHYS),
 		.irq		= IRQ_IOP331_UART1,
 		.flags		= UPF_SKIP_TEST,
 		.iotype		= UPIO_MEM,
@@ -71,6 +72,60 @@ static struct uart_port iop331_serial_ports[] = {
 	}
 };
 
+static struct resource iop33x_i2c_0_resources[] = {
+	[0] = {
+		.start = 0xfffff680,
+		.end = 0xfffff698,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_IOP331_I2C_0,
+		.end = IRQ_IOP331_I2C_0,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
+static struct resource iop33x_i2c_1_resources[] = {
+	[0] = {
+		.start = 0xfffff6a0,
+		.end = 0xfffff6b8,
+		.flags = IORESOURCE_MEM,
+	},
+	[1] = {
+		.start = IRQ_IOP331_I2C_1,
+		.end = IRQ_IOP331_I2C_1,
+		.flags = IORESOURCE_IRQ
+	}
+};
+
+static struct platform_device iop33x_i2c_0_controller = {
+	.name = "IOP3xx-I2C",
+	.id = 0,
+	.num_resources = 2,
+	.resource = iop33x_i2c_0_resources
+};
+
+static struct platform_device iop33x_i2c_1_controller = {
+	.name = "IOP3xx-I2C",
+	.id = 1,
+	.num_resources = 2,
+	.resource = iop33x_i2c_1_resources
+};
+
+static struct platform_device *iop33x_devices[] __initdata = {
+	&iop33x_i2c_0_controller,
+	&iop33x_i2c_1_controller
+};
+
+void __init iop33x_init(void)
+{
+	if(iop_is_331())
+	{
+		platform_add_devices(iop33x_devices,
+				ARRAY_SIZE(iop33x_devices));
+	}
+}
+
 void __init iop331_map_io(void)
 {
 	iotable_init(iop331_std_desc, ARRAY_SIZE(iop331_std_desc));
@@ -78,22 +133,43 @@ void __init iop331_map_io(void)
 	early_serial_setup(&iop331_serial_ports[1]);
 }
 
-#ifdef CONFIG_ARCH_IQ80331
+#ifdef CONFIG_ARCH_IOP331
 extern void iop331_init_irq(void);
 extern struct sys_timer iop331_timer;
+#endif
+
+#ifdef CONFIG_ARCH_IQ80331
 extern void iq80331_map_io(void);
 #endif
 
+#ifdef CONFIG_MACH_IQ80332
+extern void iq80332_map_io(void);
+#endif
+
 #if defined(CONFIG_ARCH_IQ80331)
 MACHINE_START(IQ80331, "Intel IQ80331")
     MAINTAINER("Intel Corp.")
     BOOT_MEM(PHYS_OFFSET, 0xfefff000, 0xfffff000) // virtual, physical
-    //BOOT_MEM(PHYS_OFFSET, IQ80331_UART0_VIRT, IQ80331_UART0_PHYS)
+    //BOOT_MEM(PHYS_OFFSET, IOP331_UART0_VIRT, IOP331_UART0_PHYS)
     MAPIO(iq80331_map_io)
     INITIRQ(iop331_init_irq)
-    .timer		= &iop331_timer,
+	.timer		= &iop331_timer,
     BOOT_PARAMS(0x0100)
+	INIT_MACHINE(iop33x_init)
 MACHINE_END
+
+#elif defined(CONFIG_MACH_IQ80332)
+MACHINE_START(IQ80332, "Intel IQ80332")
+    MAINTAINER("Intel Corp.")
+    BOOT_MEM(PHYS_OFFSET, 0xfefff000, 0xfffff000) // virtual, physical
+    //BOOT_MEM(PHYS_OFFSET, IOP331_UART0_VIRT, IOP331_UART0_PHYS)
+    MAPIO(iq80332_map_io)
+    INITIRQ(iop331_init_irq)
+	.timer		= &iop331_timer,
+    BOOT_PARAMS(0x0100)
+	INIT_MACHINE(iop33x_init)
+MACHINE_END
+
 #else
 #error No machine descriptor defined for this IOP3XX implementation
 #endif

arch/arm/mach-iop3xx/iq31244-pci.c

@@ -5,6 +5,7 @@
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -77,28 +78,28 @@ static int iq31244_setup(int nr, struct pci_sys_data *sys)
 
 	memset(res, 0, sizeof(struct resource) * 2);
 
-	res[0].start = IQ31244_PCI_IO_BASE + 0x6e000000;
-	res[0].end   = IQ31244_PCI_IO_BASE + IQ31244_PCI_IO_SIZE - 1 + IQ31244_PCI_IO_OFFSET;
+	res[0].start = IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_OFFSET;
+	res[0].end   = IOP321_PCI_UPPER_IO_BA + IOP321_PCI_IO_OFFSET;
 	res[0].name  = "IQ31244 PCI I/O Space";
 	res[0].flags = IORESOURCE_IO;
 
-	res[1].start = IQ31244_PCI_MEM_BASE;
-	res[1].end   = IQ31244_PCI_MEM_BASE + IQ31244_PCI_MEM_SIZE;
+	res[1].start = IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_OFFSET;
+	res[1].end   = IOP321_PCI_UPPER_MEM_BA + IOP321_PCI_MEM_OFFSET;
 	res[1].name  = "IQ31244 PCI Memory Space";
 	res[1].flags = IORESOURCE_MEM;
 
 	request_resource(&ioport_resource, &res[0]);
 	request_resource(&iomem_resource, &res[1]);
 
+	sys->mem_offset = IOP321_PCI_MEM_OFFSET;
+	sys->io_offset  = IOP321_PCI_IO_OFFSET;
+
 	sys->resource[0] = &res[0];
 	sys->resource[1] = &res[1];
 	sys->resource[2] = NULL;
-	sys->io_offset   = IQ31244_PCI_IO_OFFSET;
-	sys->mem_offset = IQ80321_PCI_MEM_BASE -
-		(*IOP321_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
 
-	iop3xx_pcibios_min_io = IQ31244_PCI_IO_BASE;
-	iop3xx_pcibios_min_mem = IQ31244_PCI_MEM_BASE;
+	iop3xx_pcibios_min_io = IOP321_PCI_LOWER_IO_VA;
+	iop3xx_pcibios_min_mem = IOP321_PCI_LOWER_MEM_VA;
 
 	return 1;
 }
@@ -106,9 +107,6 @@ static int iq31244_setup(int nr, struct pci_sys_data *sys)
 static void iq31244_preinit(void)
 {
 	iop321_init();
-	/* setting up the second translation window */
-	*IOP321_OMWTVR1 = IQ31244_PCI_MEM_BASE + 0x04000000;
-	*IOP321_OUMWTVR1 = 0x0;
 }
 
 static struct hw_pci iq31244_pci __initdata = {

arch/arm/mach-iop3xx/iq80321-pci.c

@@ -5,6 +5,7 @@
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -71,44 +72,28 @@ static int iq80321_setup(int nr, struct pci_sys_data *sys)
 
 	memset(res, 0, sizeof(struct resource) * 2);
 
-	res[0].start = IQ80321_PCI_IO_BASE + IQ80321_PCI_IO_OFFSET;
-	res[0].end   = IQ80321_PCI_IO_BASE + IQ80321_PCI_IO_SIZE - 1 + IQ80321_PCI_IO_OFFSET;
+	res[0].start = IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_OFFSET;
+	res[0].end   = IOP321_PCI_UPPER_IO_BA + IOP321_PCI_IO_OFFSET;
 	res[0].name  = "IQ80321 PCI I/O Space";
 	res[0].flags = IORESOURCE_IO;
 
-	res[1].start = IQ80321_PCI_MEM_BASE;
-	res[1].end   = IQ80321_PCI_MEM_BASE + IQ80321_PCI_MEM_SIZE;
+	res[1].start = IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_OFFSET;
+	res[1].end   = IOP321_PCI_UPPER_MEM_BA + IOP321_PCI_MEM_OFFSET;
 	res[1].name  = "IQ80321 PCI Memory Space";
 	res[1].flags = IORESOURCE_MEM;
 
 	request_resource(&ioport_resource, &res[0]);
 	request_resource(&iomem_resource, &res[1]);
 
-	/*
-	 * Since the IQ80321 is a slave card on a PCI backplane,
-	 * it uses BAR1 to reserve a portion of PCI memory space for
-	 * use with the private devices on the secondary bus
-	 * (GigE and PCI-X slot). We read BAR1 and configure
-	 * our outbound translation windows to target that
-	 * address range and assign all devices in that
-	 * address range. W/O this, certain BIOSes will fail
-	 * to boot as the IQ80321 claims addresses that are
-	 * in use by other devices.
-	 *
-	 * Note that the same cannot be done  with I/O space,
-	 * so hopefully the host will stick to the lower 64K for
-	 * PCI I/O and leave us alone.
-	 */
-	sys->mem_offset = IQ80321_PCI_MEM_BASE -
-		(*IOP321_IABAR1 & PCI_BASE_ADDRESS_MEM_MASK);
+	sys->mem_offset = IOP321_PCI_MEM_OFFSET;
+	sys->io_offset  = IOP321_PCI_IO_OFFSET;
 
 	sys->resource[0] = &res[0];
 	sys->resource[1] = &res[1];
 	sys->resource[2] = NULL;
-	sys->io_offset   = IQ80321_PCI_IO_OFFSET;
 
-	iop3xx_pcibios_min_io = IQ80321_PCI_IO_BASE;
-	iop3xx_pcibios_min_mem = IQ80321_PCI_MEM_BASE;
+	iop3xx_pcibios_min_io = IOP321_PCI_LOWER_IO_VA;
+	iop3xx_pcibios_min_mem = IOP321_PCI_LOWER_MEM_VA;
 
 	return 1;
 }

arch/arm/mach-iop3xx/iq80332-mm.c

+/*
+ * linux/arch/arm/mach-iop3xx/mm.c
+ *
+ * Low level memory initialization for iq80332 platform
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ *
+ */
+
+#include <linux/mm.h>
+#include <linux/init.h>
+
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/page.h>
+
+#include <asm/mach/map.h>
+#include <asm/mach-types.h>
+
+
+/*
+ * IQ80332 specific IO mappings
+ *
+ * We use RedBoot's setup for the onboard devices.
+ */
+
+void __init iq80332_map_io(void)
+{
+	iop331_map_io();
+}

arch/arm/mach-iop3xx/iq80332-pci.c

+/*
+ * arch/arm/mach-iop3xx/iq80332-pci.c
+ *
+ * PCI support for the Intel IQ80332 reference board
+ *
+ * Author: Dave Jiang <dave.jiang@intel.com>
+ * Copyright (C) 2004 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/init.h>
+
+#include <asm/hardware.h>
+#include <asm/irq.h>
+#include <asm/mach/pci.h>
+#include <asm/mach-types.h>
+
+/*
+ * The following macro is used to lookup irqs in a standard table
+ * format for those systems that do not already have PCI
+ * interrupts properly routed.  We assume 1 <= pin <= 4
+ */
+#define PCI_IRQ_TABLE_LOOKUP(minid,maxid)	\
+({ int _ctl_ = -1;				\
+   unsigned int _idsel = idsel - minid;		\
+   if (_idsel <= maxid)				\
+      _ctl_ = pci_irq_table[_idsel][pin-1];	\
+   _ctl_; })
+
+#define INTA	IRQ_IQ80332_INTA
+#define INTB	IRQ_IQ80332_INTB
+#define INTC	IRQ_IQ80332_INTC
+#define INTD	IRQ_IQ80332_INTD
+
+//#define INTE	IRQ_IQ80332_I82544
+
+static inline int __init
+iq80332_map_irq(struct pci_dev *dev, u8 idsel, u8 pin)
+{
+	static int pci_irq_table[][8] = {
+		/*
+		 * PCI IDSEL/INTPIN->INTLINE
+		 * A       B       C       D
+		 */
+		{-1,   -1,   -1,   -1},
+		{-1,   -1,   -1,   -1},
+		{-1,   -1,   -1,   -1},
+		{INTA, INTB, INTC, INTD}, /* PCI-X Slot */
+		{-1,   -1,   -1,   -1},
+		{INTC, INTC, INTC, INTC}, /* GigE  */
+		{-1,   -1,   -1,   -1},
+		{-1,   -1,   -1,   -1},
+	};
+
+	BUG_ON(pin < 1 || pin > 4);
+
+	return PCI_IRQ_TABLE_LOOKUP(1, 7);
+}
+
+static int iq80332_setup(int nr, struct pci_sys_data *sys)
+{
+	struct resource *res;
+
+	if(nr != 0)
+		return 0;
+
+	res = kmalloc(sizeof(struct resource) * 2, GFP_KERNEL);
+	if (!res)
+		panic("PCI: unable to alloc resources");
+
+	memset(res, 0, sizeof(struct resource) * 2);
+
+	res[0].start = IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_OFFSET;
+	res[0].end   = IOP331_PCI_UPPER_IO_BA + IOP331_PCI_IO_OFFSET;
+	res[0].name  = "IQ80332 PCI I/O Space";
+	res[0].flags = IORESOURCE_IO;
+
+	res[1].start = IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_OFFSET;
+	res[1].end   = IOP331_PCI_UPPER_MEM_BA + IOP331_PCI_MEM_OFFSET;
+	res[1].name  = "IQ80332 PCI Memory Space";
+	res[1].flags = IORESOURCE_MEM;
+
+	request_resource(&ioport_resource, &res[0]);
+	request_resource(&iomem_resource, &res[1]);
+
+	sys->mem_offset = IOP331_PCI_MEM_OFFSET;
+	sys->io_offset  = IOP331_PCI_IO_OFFSET;
+
+	sys->resource[0] = &res[0];
+	sys->resource[1] = &res[1];
+	sys->resource[2] = NULL;
+
+	iop3xx_pcibios_min_io = IOP331_PCI_LOWER_IO_VA;
+	iop3xx_pcibios_min_mem = IOP331_PCI_LOWER_MEM_VA;
+
+	return 1;
+}
+
+static void iq80332_preinit(void)
+{
+	iop331_init();
+}
+
+static struct hw_pci iq80332_pci __initdata = {
+	.swizzle	= pci_std_swizzle,
+	.nr_controllers = 1,
+	.setup		= iq80332_setup,
+	.scan		= iop331_scan_bus,
+	.preinit	= iq80332_preinit,
+	.map_irq	= iq80332_map_irq
+};
+
+static int __init iq80332_pci_init(void)
+{
+	if (machine_is_iq80332())
+		pci_common_init(&iq80332_pci);
+	return 0;
+}
+
+subsys_initcall(iq80332_pci_init);
+
+
+
+

arch/arm/mach-ixp4xx/common.c

@@ -279,3 +279,40 @@ struct sys_timer ixp4xx_timer = {
 	.init		= ixp4xx_timer_init,
 	.offset		= ixp4xx_gettimeoffset,
 };
+
+static struct resource ixp46x_i2c_resources[] = {
+	[0] = {
+		.start 	= 0xc8011000,
+		.end	= 0xc801101c,
+		.flags	= IORESOURCE_MEM,
+	},
+	[1] = {
+		.start 	= IRQ_IXP4XX_I2C,
+		.end	= IRQ_IXP4XX_I2C,
+		.flags	= IORESOURCE_IRQ
+	}
+};
+
+/*
+ * I2C controller. The IXP46x uses the same block as the IOP3xx, so
+ * we just use the same device name.
+ */
+static struct platform_device ixp46x_i2c_controller = {
+	.name		= "IOP3xx-I2C",
+	.id		= 0,
+	.num_resources	= 2,
+	.resource	= &ixp46x_i2c_resources
+};
+
+static struct platform_device *ixp46x_devices[] __initdata = {
+	&ixp46x_i2c_controller
+};
+
+void __init ixp4xx_sys_init(void)
+{
+	if (cpu_is_ixp46x()) {
+		platform_add_devices(ixp46x_devices,
+				ARRAY_SIZE(ixp46x_devices));
+	}
+}
+

arch/arm/mach-ixp4xx/coyote-setup.c

@@ -89,7 +89,8 @@ static void __init coyote_init(void)
 	*IXP4XX_EXP_CS0 |= IXP4XX_FLASH_WRITABLE;
 	*IXP4XX_EXP_CS1 = *IXP4XX_EXP_CS0;
 
-	platform_add_devices(&coyote_devices, ARRAY_SIZE(coyote_devices));
+	ixp4xx_sys_init();
+	platform_add_devices(coyote_devices, ARRAY_SIZE(coyote_devices));
 }
 
 #ifdef CONFIG_ARCH_ADI_COYOTE

arch/arm/mach-ixp4xx/ixdp425-setup.c

@@ -108,6 +108,8 @@ static struct platform_device *ixdp425_devices[] __initdata = {
 
 static void __init ixdp425_init(void)
 {
+	ixp4xx_sys_init();
+
 	/*
 	 * IXP465 has 32MB window
 	 */
@@ -115,7 +117,7 @@ static void __init ixdp425_init(void)
 		ixdp425_flash_resource.end += IXDP425_FLASH_SIZE;
 	}
 
-	platform_add_devices(&ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
+	platform_add_devices(ixdp425_devices, ARRAY_SIZE(ixdp425_devices));
 }
 
 MACHINE_START(IXDP425, "Intel IXDP425 Development Platform")

arch/arm/mach-ixp4xx/prpmc1100-setup.c

@@ -79,7 +79,9 @@ static struct platform_device *prpmc1100_devices[] __initdata = {
 
 static void __init prpmc1100_init(void)
 {
-	platform_add_devices(&prpmc1100_devices, ARRAY_SIZE(prpmc1100_devices));
+	ixp4xx_sys_init();
+
+	platform_add_devices(prpmc1100_devices, ARRAY_SIZE(prpmc1100_devices));
 }
 
 MACHINE_START(PRPMC1100, "Motorola PrPMC1100")

arch/arm/mm/proc-xscale.S

@@ -754,8 +754,8 @@ __8032x_proc_info:
 
 	.type	__8033x_proc_info,#object
 __8033x_proc_info:
-	.long	0x69054090
-	.long	0xffffffb0
+	.long	0x69054010
+	.long	0xffffff30
 	.long   PMD_TYPE_SECT | \
 		PMD_SECT_BUFFERABLE | \
 		PMD_SECT_CACHEABLE | \

include/asm-arm/arch-iop3xx/entry-macro.S

@@ -43,16 +43,11 @@
 		cmp	\irqstat, #0
 		beq	1001f
 		clz	\irqnr, \irqstat
-/*
- *		mov	\base, #31
- *		subs	\irqnr,\base,\irqnr
- */
-        	rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
+		rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
 		add	\irqnr,\irqnr,#IRQ_IOP331_XINT8
 		b	1001f
-1002:		clz     \irqnr, \irqstat
-		mov     \base, #31
-		subs    \irqnr,\base,\irqnr
+1002:	clz     \irqnr, \irqstat
+		rsbs    \irqnr,\irqnr,#31   @ recommend by RMK
 		add     \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
 1001:
 		.endm

include/asm-arm/arch-iop3xx/hardware.h

@@ -52,5 +52,6 @@ extern unsigned int processor_id;
 #include "iq80321.h"
 #include "iq31244.h"
 #include "iq80331.h"
+#include "iq80332.h"
 
 #endif  /* _ASM_ARCH_HARDWARE_H */

include/asm-arm/arch-iop3xx/iop321.h

@@ -5,6 +5,7 @@
  *
  * Author: Rory Bolt <rorybolt@pacbell.net>
  * Copyright (C) 2002 Rory Bolt
+ * Copyright (C) 2004 Intel Corp.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -30,21 +31,30 @@
 /*
  * IOP321 I/O and Mem space regions for PCI autoconfiguration
  */
-#define IOP321_PCI_LOWER_IO             0x90000000
-#define IOP321_PCI_UPPER_IO             0x9000ffff
-#define IOP321_PCI_LOWER_MEM            0x80000000
-#define IOP321_PCI_UPPER_MEM            0x83ffffff
-
-#define IOP321_PCI_WINDOW_SIZE          64 * 0x100000
+#define IOP321_PCI_IO_WINDOW_SIZE   0x10000
+#define IOP321_PCI_LOWER_IO_PA      0x90000000
+#define IOP321_PCI_LOWER_IO_VA      0xfe000000
+#define IOP321_PCI_LOWER_IO_BA      (*IOP321_OIOWTVR)
+#define IOP321_PCI_UPPER_IO_PA      (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_IO_VA      (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_IO_BA      (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
+#define IOP321_PCI_IO_OFFSET        (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
+
+#define IOP321_PCI_MEM_WINDOW_SIZE  (~*IOP321_IALR1 + 1)
+#define IOP321_PCI_LOWER_MEM_PA     0x80000000
+#define IOP321_PCI_LOWER_MEM_VA     0x80000000
+#define IOP321_PCI_LOWER_MEM_BA     (*IOP321_OMWTVR0)
+#define IOP321_PCI_UPPER_MEM_PA     (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_MEM_VA     (IOP321_PCI_LOWER_MEM_VA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_UPPER_MEM_BA     (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
+#define IOP321_PCI_MEM_OFFSET       (IOP321_PCI_LOWER_MEM_VA - IOP321_PCI_LOWER_MEM_BA)
 
 
 /*
  * IOP321 chipset registers
  */
 #define IOP321_VIRT_MEM_BASE 0xfeffe000  /* chip virtual mem address*/
-//#define IOP321_VIRT_MEM_BASE 0xfff00000  /* chip virtual mem address*/
-
-#define IOP321_PHY_MEM_BASE  0xffffe000  /* chip physical memory address */
+#define IOP321_PHYS_MEM_BASE 0xffffe000  /* chip physical memory address */
 #define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
 
 /* Reserved 0x00000000 through 0x000000FF */

include/asm-arm/arch-iop3xx/iop331-irqs.h

@@ -91,6 +91,7 @@
 #define NR_IRQS			NR_IOP331_IRQS
 
 
+#if defined(CONFIG_ARCH_IQ80331)
 /*
  * Interrupts available on the IQ80331 board
  */
@@ -110,4 +111,26 @@
 #define	IRQ_IQ80331_INTC	IRQ_IOP331_XINT2
 #define	IRQ_IQ80331_INTD	IRQ_IOP331_XINT3
 
+#elif defined(CONFIG_MACH_IQ80332)
+/*
+ * Interrupts available on the IQ80332 board
+ */
+
+/*
+ * On board devices
+ */
+#define	IRQ_IQ80332_I82544	IRQ_IOP331_XINT0
+#define IRQ_IQ80332_UART0	IRQ_IOP331_UART0
+#define IRQ_IQ80332_UART1	IRQ_IOP331_UART1
+
+/*
+ * PCI interrupts
+ */
+#define	IRQ_IQ80332_INTA	IRQ_IOP331_XINT0
+#define	IRQ_IQ80332_INTB	IRQ_IOP331_XINT1
+#define	IRQ_IQ80332_INTC	IRQ_IOP331_XINT2
+#define	IRQ_IQ80332_INTD	IRQ_IOP331_XINT3
+
+#endif
+
 #endif // _IOP331_IRQ_H_

include/asm-arm/arch-iop3xx/iq31244.h

@@ -7,8 +7,6 @@
 #ifndef _IQ31244_H_
 #define _IQ31244_H_
 
-#define IQ31244_RAMBASE		0xa0000000
-
 #define	IQ31244_FLASHBASE	0xf0000000	/* Flash */
 #define	IQ31244_FLASHSIZE	0x00800000
 #define	IQ31244_FLASHWIDTH	2
@@ -19,16 +17,6 @@
 #define IQ31244_ROTARY_SW	0xfe8d0000	/* Rotary Switch */
 #define IQ31244_BATT_STAT	0xfe8f0000	/* Battery Status */
 
-/*
- * IQ31244 PCI I/O and Mem space regions
- */
-#define IQ31244_PCI_IO_BASE	0x90000000
-#define IQ31244_PCI_IO_SIZE	0x00010000
-#define IQ31244_PCI_MEM_BASE	0x80000000
-//#define IQ31244_PCI_MEM_SIZE	0x04000000
-#define IQ31244_PCI_MEM_SIZE	0x08000000
-#define	IQ31244_PCI_IO_OFFSET	0x6e000000
-
 #ifndef __ASSEMBLY__
 extern void iq31244_map_io(void);
 #endif

include/asm-arm/arch-iop3xx/iq80321.h

@@ -7,8 +7,6 @@
 #ifndef _IQ80321_H_
 #define _IQ80321_H_
 
-#define IQ80321_RAMBASE		0xa0000000
-
 #define	IQ80321_FLASHBASE	0xf0000000	/* Flash */
 #define	IQ80321_FLASHSIZE	0x00800000
 #define	IQ80321_FLASHWIDTH	1
@@ -19,15 +17,6 @@
 #define IQ80321_ROTARY_SW	0xfe8d0000	/* Rotary Switch */
 #define IQ80321_BATT_STAT	0xfe8f0000	/* Battery Status */
 
-/*
- * IQ80321 PCI I/O and Mem space regions
- */
-#define IQ80321_PCI_IO_BASE	0x90000000
-#define IQ80321_PCI_IO_SIZE	0x00010000
-#define IQ80321_PCI_MEM_BASE	0x80000000
-#define IQ80321_PCI_MEM_SIZE	0x04000000
-#define	IQ80321_PCI_IO_OFFSET	0x6e000000
-
 #ifndef __ASSEMBLY__
 extern void iq80321_map_io(void);
 #endif

include/asm-arm/arch-iop3xx/iq80332.h

+/*
+ * linux/include/asm/arch-iop3xx/iq80332.h
+ *
+ * Intel IQ80332 evaluation board registers
+ */
+
+#ifndef _IQ80332_H_
+#define _IQ80332_H_
+
+#define	IQ80332_FLASHBASE	0xc0000000	/* Flash */
+#define	IQ80332_FLASHSIZE	0x00800000
+#define	IQ80332_FLASHWIDTH	1
+
+#define IQ80332_7SEG_1		0xce840000	/* 7-Segment MSB */
+#define IQ80332_7SEG_0		0xce850000	/* 7-Segment LSB (WO) */
+#define IQ80332_ROTARY_SW	0xce8d0000	/* Rotary Switch */
+#define IQ80332_BATT_STAT	0xce8f0000	/* Battery Status */
+
+#ifndef __ASSEMBLY__
+extern void iq80332_map_io(void);
+#endif
+
+#endif	// _IQ80332_H_

include/asm-arm/arch-iop3xx/timex.h

@@ -10,7 +10,7 @@
 
 #define CLOCK_TICK_RATE IOP321_TICK_RATE
 
-#elif defined(CONFIG_ARCH_IQ80331)
+#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
 
 #define CLOCK_TICK_RATE IOP331_TICK_RATE
 

include/asm-arm/arch-iop3xx/uncompress.h

@@ -9,8 +9,10 @@
 
 #ifdef CONFIG_ARCH_IOP321
 #define UTYPE unsigned char *
-#else
+#elif defined(CONFIG_ARCH_IOP331)
 #define UTYPE u32 *
+#else
+#error "Missing IOP3xx arch type def"
 #endif
 
 static volatile UTYPE uart_base;
@@ -42,8 +44,8 @@ static __inline__ void __arch_decomp_setup(unsigned long arch_id)
 			uart_base = (volatile UTYPE)IQ80321_UART;
 		else if(machine_is_iq31244())
 			uart_base = (volatile UTYPE)IQ31244_UART;
-		else if(machine_is_iq80331())
-			uart_base = (volatile UTYPE)IQ80331_UART0_PHYS;
+		else if(machine_is_iq80331() || machine_is_iq80332())
+			uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
 		else
 			uart_base = (volatile UTYPE)0xfe800000;
 }

include/asm-arm/arch-ixp4xx/irqs.h

@@ -48,14 +48,6 @@
 #define IRQ_IXP4XX_GPIO12	29
 #define IRQ_IXP4XX_SW_INT1	30
 #define IRQ_IXP4XX_SW_INT2	31
-
-#ifndef	CONFIG_CPU_IXP46X
-#define NR_IRQS			32
-#else
-
-/*
- * IXP465 adds new sources
- */
 #define IRQ_IXP4XX_USB_HOST	32
 #define IRQ_IXP4XX_I2C		33
 #define IRQ_IXP4XX_SSP		34
@@ -67,6 +59,12 @@
 #define IRQ_IXP4XX_MCU_ECC	61
 #define IRQ_IXP4XX_EXP_PE	62
 
+/*
+ * Only first 32 sources are valid if running on IXP42x systems
+ */
+#ifndef	CONFIG_CPU_IXP46X
+#define NR_IRQS			32
+#else
 #define NR_IRQS			64
 #endif
 

include/asm-arm/arch-ixp4xx/platform.h

@@ -60,6 +60,7 @@ struct sys_timer;
  */
 extern void ixp4xx_map_io(void);
 extern void ixp4xx_init_irq(void);
+extern void ixp4xx_sys_init(void);
 extern struct sys_timer ixp4xx_timer;
 extern void ixp4xx_pci_preinit(void);
 struct pci_sys_data;