Commit 71e11a3f authored by Alexander Lobakin's avatar Alexander Lobakin Committed by David S. Miller

net: qed: address kernel-doc warnings

Get rid of the kernel-doc warnings when building with W=1+ by
rewriting the problematic doc comments according to the
recommended format and style.

Note that this only fixes problems found in C source files,
headers aren't in scope for now.
Signed-off-by: default avatarAlexander Lobakin <alobakin@marvell.com>
Signed-off-by: default avatarIgor Russkikh <irusskikh@marvell.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 365cd2ce
...@@ -996,14 +996,17 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn, ...@@ -996,14 +996,17 @@ bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
} while (0) } while (0)
/** /**
* @brief qed_dmae_to_grc - is an internal function - writes from host to * qed_dmae_to_grc() - Internal function for writing from host to
* wide-bus registers (split registers are not supported yet) * wide-bus registers (split registers are not supported yet).
* *
* @param p_hwfn - HW device data * @p_hwfn: HW device data.
* @param p_ptt - ptt window used for writing the registers. * @p_ptt: PTT window used for writing the registers.
* @param p_data - pointer to source data. * @p_data: Pointer to source data.
* @param addr - Destination register address. * @addr: Destination register address.
* @param len_in_dwords - data length in DWARDS (u32) * @len_in_dwords: Data length in dwords (u32).
*
* Return: Length of the written data in dwords (u32) or -1 on invalid
* input.
*/ */
static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn, static int qed_dmae_to_grc(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, struct qed_ptt *p_ptt,
......
...@@ -816,11 +816,12 @@ static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn, ...@@ -816,11 +816,12 @@ static inline u16 qed_attn_update_idx(struct qed_hwfn *p_hwfn,
} }
/** /**
* @brief qed_int_assertion - handles asserted attention bits * qed_int_assertion() - Handle asserted attention bits.
* *
* @param p_hwfn * @p_hwfn: HW device data.
* @param asserted_bits newly asserted bits * @asserted_bits: Newly asserted bits.
* @return int *
* Return: Zero value.
*/ */
static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits) static int qed_int_assertion(struct qed_hwfn *p_hwfn, u16 asserted_bits)
{ {
...@@ -880,16 +881,17 @@ static void qed_int_attn_print(struct qed_hwfn *p_hwfn, ...@@ -880,16 +881,17 @@ static void qed_int_attn_print(struct qed_hwfn *p_hwfn,
} }
/** /**
* @brief qed_int_deassertion_aeu_bit - handles the effects of a single * qed_int_deassertion_aeu_bit() - Handles the effects of a single
* cause of the attention * cause of the attention.
* *
* @param p_hwfn * @p_hwfn: HW device data.
* @param p_aeu - descriptor of an AEU bit which caused the attention * @p_aeu: Descriptor of an AEU bit which caused the attention.
* @param aeu_en_reg - register offset of the AEU enable reg. which configured * @aeu_en_reg: Register offset of the AEU enable reg. which configured
* this bit to this group. * this bit to this group.
* @param bit_index - index of this bit in the aeu_en_reg * @p_bit_name: AEU bit description for logging purposes.
* @bitmask: Index of this bit in the aeu_en_reg.
* *
* @return int * Return: Zero on success, negative errno otherwise.
*/ */
static int static int
qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
...@@ -938,12 +940,12 @@ qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn, ...@@ -938,12 +940,12 @@ qed_int_deassertion_aeu_bit(struct qed_hwfn *p_hwfn,
} }
/** /**
* @brief qed_int_deassertion_parity - handle a single parity AEU source * qed_int_deassertion_parity() - Handle a single parity AEU source.
* *
* @param p_hwfn * @p_hwfn: HW device data.
* @param p_aeu - descriptor of an AEU bit which caused the parity * @p_aeu: Descriptor of an AEU bit which caused the parity.
* @param aeu_en_reg - address of the AEU enable register * @aeu_en_reg: Address of the AEU enable register.
* @param bit_index * @bit_index: Index (0-31) of an AEU bit.
*/ */
static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
struct aeu_invert_reg_bit *p_aeu, struct aeu_invert_reg_bit *p_aeu,
...@@ -976,12 +978,13 @@ static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn, ...@@ -976,12 +978,13 @@ static void qed_int_deassertion_parity(struct qed_hwfn *p_hwfn,
} }
/** /**
* @brief - handles deassertion of previously asserted attentions. * qed_int_deassertion() - Handle deassertion of previously asserted
* attentions.
* *
* @param p_hwfn * @p_hwfn: HW device data.
* @param deasserted_bits - newly deasserted bits * @deasserted_bits: newly deasserted bits.
* @return int
* *
* Return: Zero value.
*/ */
static int qed_int_deassertion(struct qed_hwfn *p_hwfn, static int qed_int_deassertion(struct qed_hwfn *p_hwfn,
u16 deasserted_bits) u16 deasserted_bits)
...@@ -2241,9 +2244,9 @@ int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt) ...@@ -2241,9 +2244,9 @@ int qed_int_igu_read_cam(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
} }
/** /**
* @brief Initialize igu runtime registers * qed_int_igu_init_rt() - Initialize IGU runtime registers.
* *
* @param p_hwfn * @p_hwfn: HW device data.
*/ */
void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn) void qed_int_igu_init_rt(struct qed_hwfn *p_hwfn)
{ {
......
...@@ -642,18 +642,18 @@ void qed_spq_return_entry(struct qed_hwfn *p_hwfn, struct qed_spq_entry *p_ent) ...@@ -642,18 +642,18 @@ void qed_spq_return_entry(struct qed_hwfn *p_hwfn, struct qed_spq_entry *p_ent)
} }
/** /**
* @brief qed_spq_add_entry - adds a new entry to the pending * qed_spq_add_entry() - Add a new entry to the pending list.
* list. Should be used while lock is being held. * Should be used while lock is being held.
* *
* Addes an entry to the pending list is there is room (en empty * @p_hwfn: HW device data.
* @p_ent: An entry to add.
* @priority: Desired priority.
*
* Adds an entry to the pending list is there is room (an empty
* element is available in the free_pool), or else places the * element is available in the free_pool), or else places the
* entry in the unlimited_pending pool. * entry in the unlimited_pending pool.
* *
* @param p_hwfn * Return: zero on success, -EINVAL on invalid @priority.
* @param p_ent
* @param priority
*
* @return int
*/ */
static int qed_spq_add_entry(struct qed_hwfn *p_hwfn, static int qed_spq_add_entry(struct qed_hwfn *p_hwfn,
struct qed_spq_entry *p_ent, struct qed_spq_entry *p_ent,
......
...@@ -823,16 +823,17 @@ static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn, ...@@ -823,16 +823,17 @@ static int qed_iov_enable_vf_access(struct qed_hwfn *p_hwfn,
} }
/** /**
* @brief qed_iov_config_perm_table - configure the permission * qed_iov_config_perm_table() - Configure the permission zone table.
* zone table. *
* In E4, queue zone permission table size is 320x9. There * @p_hwfn: HW device data.
* are 320 VF queues for single engine device (256 for dual * @p_ptt: PTT window for writing the registers.
* engine device), and each entry has the following format: * @vf: VF info data.
* {Valid, VF[7:0]} * @enable: The actual permision for this VF.
* @param p_hwfn *
* @param p_ptt * In E4, queue zone permission table size is 320x9. There
* @param vf * are 320 VF queues for single engine device (256 for dual
* @param enable * engine device), and each entry has the following format:
* {Valid, VF[7:0]}
*/ */
static void qed_iov_config_perm_table(struct qed_hwfn *p_hwfn, static void qed_iov_config_perm_table(struct qed_hwfn *p_hwfn,
struct qed_ptt *p_ptt, struct qed_ptt *p_ptt,
......
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