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Commit 750ee785 authored by Olof Johansson's avatar Olof Johansson
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Merge tag 'qcom-arm64-for-5.3' of... 

Merge tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into arm/dt

Qualcomm ARM64 Updates for v5.3

* Switch to use second gen PON on PM8998
* Add PSCI cupidle states for MSM8996, MSM8998,and SDM845
* Add MSM8996 UFS phy reset controller
* Add propre cpu capacity scaling on MSM8996
* Fixups for APR domain, legacy clocks, and PSCI entry latency on MSM8996
* Enable SMMUs on MSM8996
* Add Dragonboard 845C
* Add Q6V5, GPU, GMU, and AOSS QMP node on SDM845
* Fixup CPU topology on SDM845
* Change USB1 to be peripheral on SDM845 MTP
* Add PCIe Phy, RC nodes, ANOC1 SMMU, and RPMPD node on MSM8998
* Update coresight bindings for MSM8916
* Update idle state names and entry-method on MSM8916
* Add PCIe, RPMPD, LPASS, Q6, TCSR, TuringCC, PSCI cpuidle states,
  and CDSP on QCS404
* Add reset-cells property to QCS404 GCC node
* Fixup s3 max voltage, l3 min voltage, drive strength typo, and
  s3 supply definition on QCS404-evb
* Fixup ADC outputs and VADC calibration on PMS405

* tag 'qcom-arm64-for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: (39 commits)
  arm64: dts: qcom: qcs404-evb: fix vdd_apc supply
  arm64: dts: qcom: pm8998: Use qcom,pm8998-pon binding for second gen pon
  arm64: dts: qcom: msm8996: Enable SMMUs
  arm64: dts: qcom: msm8996: Correct apr-domain property
  arm64: dts: qcom: Add Dragonboard 845c
  arm64: dts: qcom: qcs404-evb: Enable PCIe
  arm64: dts: qcom: qcs404: Add PCIe related nodes
  arm64: dts: qcom: msm8998: Add PCIe PHY and RC nodes
  arm64: dts: qcom: msm8998: Add ANOC1 SMMU node
  arm64: dts: qcom: msm8996: Stop using legacy clock names
  arm64: dts: msm8996: fix PSCI entry-latency-us
  arm64: dts: qcom: msm8998: Add PSCI cpuidle low power states
  arm64: dts: qcom: sdm845: Add Q6V5 MSS node
  arm64: dts: qcom: Add AOSS QMP node
  arm64: dts: qcom-qcs404: Add reset-cells to GCC node
  arm64: dts: qcom-msm8916: Update coresight DT bindings
  arm64: dts: qcom: msm8998: Add rpmpd node
  arm64: dts: qcom: qcs404: Add rpmpd node
  arm64: dts: qcom: qcs404: Move lpass and q6 into soc
  arm64: dts: qcom: qcs404: Fully describe the CDSP
  ...
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parents 0914acd8 2410fd45
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Showing with 1392 additions and 142 deletions
arch/arm64/boot/dts/qcom/Makefile
View file @ 750ee785
......@@ -7,6 +7,7 @@ dtb-$(CONFIG_ARCH_QCOM) += msm8992-bullhead-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8994-angler-rev-101.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8996-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += msm8998-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-db845c.dtb
dtb-$(CONFIG_ARCH_QCOM) += sdm845-mtp.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-1000.dtb
dtb-$(CONFIG_ARCH_QCOM) += qcs404-evb-4000.dtb
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 750ee785
......@@ -102,7 +102,7 @@ CPU0: cpu@0 {
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
......@@ -114,7 +114,7 @@ CPU1: cpu@1 {
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
......@@ -126,7 +126,7 @@ CPU2: cpu@2 {
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
......@@ -138,7 +138,7 @@ CPU3: cpu@3 {
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SPC>;
cpu-idle-states = <&CPU_SLEEP_0>;
clocks = <&apcs>;
operating-points-v2 = <&cpu_opp_table>;
#cooling-cells = <2>;
......@@ -150,8 +150,11 @@ L2_0: l2-cache {
};
idle-states {
CPU_SPC: spc {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x40000002>;
entry-latency-us = <130>;
exit-latency-us = <150>;
......@@ -1164,7 +1167,7 @@ tpiu_in: endpoint {
};
funnel@821000 {
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x821000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
......@@ -1277,7 +1280,7 @@ etr_in: endpoint {
};
funnel@841000 { /* APSS funnel only 4 inputs are used */
compatible = "arm,coresight-funnel", "arm,primecell";
compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
reg = <0x841000 0x1000>;
clocks = <&rpmcc RPM_QDSS_CLK>, <&rpmcc RPM_QDSS_A_CLK>;
......
arch/arm64/boot/dts/qcom/msm8996.dtsi
View file @ 750ee785
......@@ -94,6 +94,8 @@ CPU0: cpu@0 {
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "cache";
......@@ -106,6 +108,8 @@ CPU1: cpu@1 {
compatible = "qcom,kryo";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_0>;
};
......@@ -114,6 +118,8 @@ CPU2: cpu@100 {
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "cache";
......@@ -126,6 +132,8 @@ CPU3: cpu@101 {
compatible = "qcom,kryo";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0>;
capacity-dmips-mhz = <1024>;
next-level-cache = <&L2_1>;
};
......@@ -150,6 +158,19 @@ core1 {
};
};
};
idle-states {
entry-method = "psci";
CPU_SLEEP_0: cpu-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "standalone-power-collapse";
arm,psci-suspend-param = <0x00000004>;
entry-latency-us = <130>;
exit-latency-us = <80>;
min-residency-us = <300>;
};
};
};
thermal-zones {
......@@ -846,10 +867,11 @@ ufsphy: phy@627000 {
clock-names = "ref_clk_src", "ref_clk";
clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
<&gcc GCC_UFS_CLKREF_CLK>;
resets = <&ufshc 0>;
status = "disabled";
};
ufshc@624000 {
ufshc: ufshc@624000 {
compatible = "qcom,ufshc";
reg = <0x624000 0x2500>;
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
......@@ -905,6 +927,7 @@ ufshc@624000 {
<0 0>;
lanes-per-direction = <1>;
#reset-cells = <1>;
status = "disabled";
ufs_variant {
......@@ -1154,7 +1177,6 @@ vfe_smmu: arm,smmu@da0000 {
clock-names = "iface",
"bus";
#iommu-cells = <1>;
status = "disabled";
};
camss: camss@a00000 {
......@@ -1307,8 +1329,6 @@ adreno_smmu: arm,smmu@b40000 {
clock-names = "iface", "bus";
power-domains = <&mmcc GPU_GDSC>;
status = "disabled";
};
mdp_smmu: arm,smmu@d00000 {
......@@ -1325,8 +1345,6 @@ mdp_smmu: arm,smmu@d00000 {
clock-names = "iface", "bus";
power-domains = <&mmcc MDSS_GDSC>;
status = "disabled";
};
lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
......@@ -1353,7 +1371,6 @@ lpass_q6_smmu: arm,smmu-lpass_q6@1600000 {
clocks = <&gcc GCC_HLOS1_VOTE_LPASS_CORE_SMMU_CLK>,
<&gcc GCC_HLOS1_VOTE_LPASS_ADSP_SMMU_CLK>;
clock-names = "iface", "bus";
status = "disabled";
};
agnoc@0 {
......@@ -1674,7 +1691,7 @@ mdss: mdss@900000 {
#interrupt-cells = <1>;
clocks = <&mmcc MDSS_AHB_CLK>;
clock-names = "iface_clk";
clock-names = "iface";
#address-cells = <1>;
#size-cells = <1>;
......@@ -1693,11 +1710,11 @@ mdp: mdp@901000 {
<&mmcc MDSS_MDP_CLK>,
<&mmcc SMMU_MDP_AXI_CLK>,
<&mmcc MDSS_VSYNC_CLK>;
clock-names = "iface_clk",
"bus_clk",
"core_clk",
"iommu_clk",
"vsync_clk";
clock-names = "iface",
"bus",
"core",
"iommu",
"vsync";
iommus = <&mdp_smmu 0>;
......@@ -1732,11 +1749,11 @@ hdmi: hdmi-tx@9a0000 {
<&mmcc MDSS_HDMI_AHB_CLK>,
<&mmcc MDSS_EXTPCLK_CLK>;
clock-names =
"mdp_core_clk",
"iface_clk",
"core_clk",
"alt_iface_clk",
"extp_clk";
"mdp_core",
"iface",
"core",
"alt_iface",
"extp";
phys = <&hdmi_phy>;
phy-names = "hdmi_phy";
......@@ -1773,8 +1790,8 @@ hdmi_phy: hdmi-phy@9a0600 {
clocks = <&mmcc MDSS_AHB_CLK>,
<&gcc GCC_HDMI_CLKREF_CLK>;
clock-names = "iface_clk",
"ref_clk";
clock-names = "iface",
"ref";
};
};
};
......@@ -1814,7 +1831,7 @@ apr {
power-domains = <&gcc HLOS1_VOTE_LPASS_ADSP_GDSC>;
compatible = "qcom,apr-v2";
qcom,smd-channels = "apr_audio_svc";
reg = <APR_DOMAIN_ADSP>;
qcom,apr-domain = <APR_DOMAIN_ADSP>;
#address-cells = <1>;
#size-cells = <0>;
......
arch/arm64/boot/dts/qcom/msm8998.dtsi
View file @ 750ee785
......@@ -4,6 +4,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8998.h>
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/power/qcom-rpmpd.h>
#include <dt-bindings/gpio/gpio.h>
/ {
......@@ -78,6 +79,7 @@ CPU0: cpu@0 {
compatible = "arm,armv8";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
......@@ -96,6 +98,7 @@ CPU1: cpu@1 {
compatible = "arm,armv8";
reg = <0x0 0x1>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_1: l1-icache {
compatible = "arm,arch-cache";
......@@ -110,6 +113,7 @@ CPU2: cpu@2 {
compatible = "arm,armv8";
reg = <0x0 0x2>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_2: l1-icache {
compatible = "arm,arch-cache";
......@@ -124,6 +128,7 @@ CPU3: cpu@3 {
compatible = "arm,armv8";
reg = <0x0 0x3>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>;
next-level-cache = <&L2_0>;
L1_I_3: l1-icache {
compatible = "arm,arch-cache";
......@@ -138,6 +143,7 @@ CPU4: cpu@100 {
compatible = "arm,armv8";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
......@@ -156,6 +162,7 @@ CPU5: cpu@101 {
compatible = "arm,armv8";
reg = <0x0 0x101>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_101: l1-icache {
compatible = "arm,arch-cache";
......@@ -170,6 +177,7 @@ CPU6: cpu@102 {
compatible = "arm,armv8";
reg = <0x0 0x102>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_102: l1-icache {
compatible = "arm,arch-cache";
......@@ -184,6 +192,7 @@ CPU7: cpu@103 {
compatible = "arm,armv8";
reg = <0x0 0x103>;
enable-method = "psci";
cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>;
next-level-cache = <&L2_1>;
L1_I_103: l1-icache {
compatible = "arm,arch-cache";
......@@ -230,6 +239,48 @@ core3 {
};
};
};
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-retention";
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <81>;
exit-latency-us = <86>;
min-residency-us = <200>;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <273>;
exit-latency-us = <612>;
min-residency-us = <1000>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-retention";
arm,psci-suspend-param = <0x00000002>;
entry-latency-us = <79>;
exit-latency-us = <82>;
min-residency-us = <200>;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-power-collapse";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <336>;
exit-latency-us = <525>;
min-residency-us = <1000>;
local-timer-stop;
};
};
};
firmware {
......@@ -264,6 +315,56 @@ rpmcc: clock-controller {
compatible = "qcom,rpmcc-msm8998", "qcom,rpmcc";
#clock-cells = <1>;
};
rpmpd: power-controller {
compatible = "qcom,msm8998-rpmpd";
#power-domain-cells = <1>;
operating-points-v2 = <&rpmpd_opp_table>;
rpmpd_opp_table: opp-table {
compatible = "operating-points-v2";
rpmpd_opp_ret: opp1 {
opp-level = <16>;
};
rpmpd_opp_ret_plus: opp2 {
opp-level = <32>;
};
rpmpd_opp_min_svs: opp3 {
opp-level = <48>;
};
rpmpd_opp_low_svs: opp4 {
opp-level = <64>;
};
rpmpd_opp_svs: opp5 {
opp-level = <128>;
};
rpmpd_opp_svs_plus: opp6 {
opp-level = <192>;
};
rpmpd_opp_nom: opp7 {
opp-level = <256>;
};
rpmpd_opp_nom_plus: opp8 {
opp-level = <320>;
};
rpmpd_opp_turbo: opp9 {
opp-level = <384>;
};
rpmpd_opp_turbo_plus: opp10 {
opp-level = <512>;
};
};
};
};
};
......@@ -758,6 +859,90 @@ tsens1: thermal@10ae000 {
#thermal-sensor-cells = <1>;
};
anoc1_smmu: iommu@1680000 {
compatible = "qcom,msm8998-smmu-v2", "qcom,smmu-v2";
reg = <0x01680000 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <0>;
interrupts =
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>;
};
pcie0: pci@1c00000 {
compatible = "qcom,pcie-msm8996";
reg = <0x01c00000 0x2000>,
<0x1b000000 0xf1d>,
<0x1b000f20 0xa8>,
<0x1b100000 0x100000>;
reg-names = "parf", "dbi", "elbi", "config";
device_type = "pci";
linux,pci-domain = <0>;
bus-range = <0x00 0xff>;
#address-cells = <3>;
#size-cells = <2>;
num-lanes = <1>;
phys = <&pciephy>;
phy-names = "pciephy";
ranges = <0x01000000 0x0 0x1b200000 0x1b200000 0x0 0x100000>,
<0x02000000 0x0 0x1b300000 0x1b300000 0x0 0xd00000>;
#interrupt-cells = <1>;
interrupts = <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "msi";
interrupt-map-mask = <0 0 0 0x7>;
interrupt-map = <0 0 0 1 &intc 0 135 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 2 &intc 0 136 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 3 &intc 0 138 IRQ_TYPE_LEVEL_HIGH>,
<0 0 0 4 &intc 0 139 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_0_AUX_CLK>;
clock-names = "pipe", "bus_master", "bus_slave", "cfg", "aux";
power-domains = <&gcc PCIE_0_GDSC>;
iommu-map = <0x100 &anoc1_smmu 0x1480 1>;
perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
};
phy@1c06000 {
compatible = "qcom,msm8998-qmp-pcie-phy";
reg = <0x01c06000 0x18c>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
<&gcc GCC_PCIE_CLKREF_CLK>;
clock-names = "aux", "cfg_ahb", "ref";
resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
reset-names = "phy", "common";
vdda-phy-supply = <&vreg_l1a_0p875>;
vdda-pll-supply = <&vreg_l2a_1p2>;
pciephy: lane@1c06800 {
reg = <0x01c06200 0x128>, <0x01c06400 0x1fc>, <0x01c06800 0x20c>;
#phy-cells = <0>;
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
clock-names = "pipe0";
clock-output-names = "pcie_0_pipe_clk_src";
#clock-cells = <0>;
};
};
tcsr_mutex_regs: syscon@1f40000 {
compatible = "syscon";
reg = <0x1f40000 0x20000>;
......
arch/arm64/boot/dts/qcom/pm8998.dtsi
View file @ 750ee785
......@@ -39,7 +39,7 @@ pm8998_lsid0: pmic@0 {
#size-cells = <0>;
pm8998_pon: pon@800 {
compatible = "qcom,pm8916-pon";
compatible = "qcom,pm8998-pon";
reg = <0x800>;
mode-bootloader = <0x2>;
......
arch/arm64/boot/dts/qcom/pms405.dtsi
View file @ 750ee785
......@@ -98,7 +98,7 @@ vref_1p25 {
qcom,pre-scaling = <1 1>;
};
vph_pwr {
pon_1: vph_pwr {
reg = <ADC5_VPH_PWR>;
qcom,pre-scaling = <1 3>;
};
......@@ -108,18 +108,24 @@ die_temp {
qcom,pre-scaling = <1 1>;
};
xo_therm_100k_pu {
reg = <ADC5_XO_THERM_100K_PU>;
pa_therm1: thermistor1 {
reg = <ADC5_AMUX_THM1_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
amux_thm1_100k_pu {
reg = <ADC5_AMUX_THM1_100K_PU>;
pa_therm3: thermistor3 {
reg = <ADC5_AMUX_THM3_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
amux_thm3_100k_pu {
reg = <ADC5_AMUX_THM3_100K_PU>;
xo_therm: xo_temp {
reg = <ADC5_XO_THERM_100K_PU>;
qcom,ratiometric;
qcom,hw-settle-time = <200>;
qcom,pre-scaling = <1 1>;
};
};
......
arch/arm64/boot/dts/qcom/qcs404-evb.dtsi
View file @ 750ee785
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2018, Linaro Limited
#include <dt-bindings/gpio/gpio.h>
#include "qcs404.dtsi"
#include "pms405.dtsi"
......@@ -56,18 +57,41 @@ &blsp2_dma {
qcom,controlled-remotely;
};
&gcc {
protected-clocks = <GCC_BIMC_CDSP_CLK>,
<GCC_CDSP_CFG_AHB_CLK>,
<GCC_CDSP_BIMC_CLK_SRC>,
<GCC_CDSP_TBU_CLK>;
};
&pms405_spmi_regulators {
vdd_s3-supply = <&pms405_s3>;
vdd_s3-supply = <&vph_pwr>;
pms405_s3: s3 {
regulator-always-on;
regulator-boot-on;
regulator-name = "vdd_apc";
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1352000>;
regulator-max-microvolt = <1384000>;
};
};
&pcie {
status = "ok";
perst-gpio = <&tlmm 43 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
pinctrl-0 = <&perst_state>;
};
&pcie_phy {
status = "ok";
vdda-vp-supply = <&vreg_l3_1p05>;
vdda-vph-supply = <&vreg_l5_1p8>;
};
&remoteproc_adsp {
status = "ok";
};
......@@ -118,7 +142,7 @@ vreg_l2_1p275: l2 {
};
vreg_l3_1p05: l3 {
regulator-min-microvolt = <1050000>;
regulator-min-microvolt = <1048000>;
regulator-max-microvolt = <1160000>;
};
......@@ -184,6 +208,15 @@ &sdcc1 {
};
&tlmm {
perst_state: perst {
pins = "gpio43";
function = "gpio";
drive-strength = <2>;
bias-disable;
output-low;
};
sdc1_on: sdc1-on {
clk {
pins = "sdc1_clk";
......@@ -200,7 +233,7 @@ cmd {
data {
pins = "sdc1_data";
bias-pull-up;
dreive-strength = <10>;
drive-strength = <10>;
};
rclk {
......@@ -225,7 +258,7 @@ cmd {
data {
pins = "sdc1_data";
bias-pull-up;
dreive-strength = <2>;
drive-strength = <2>;
};
rclk {
......
arch/arm64/boot/dts/qcom/qcs404.dtsi
View file @ 750ee785
This diff is collapsed.
arch/arm64/boot/dts/qcom/sdm845-db845c.dts 0 → 100644
View file @ 750ee785
This diff is collapsed.
arch/arm64/boot/dts/qcom/sdm845-mtp.dts
View file @ 750ee785
......@@ -404,8 +404,8 @@ &usb_1 {
};
&usb_1_dwc3 {
/* Until we have Type C hooked up we'll force this as host. */
dr_mode = "host";
/* Until we have Type C hooked up we'll force this as peripheral. */
dr_mode = "peripheral";
};
&usb_1_hsphy {
......
arch/arm64/boot/dts/qcom/sdm845.dtsi
View file @ 750ee785
......@@ -190,6 +190,9 @@ CPU0: cpu@0 {
compatible = "qcom,kryo385";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
......@@ -208,6 +211,9 @@ CPU1: cpu@100 {
compatible = "qcom,kryo385";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
......@@ -223,6 +229,9 @@ CPU2: cpu@200 {
compatible = "qcom,kryo385";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
......@@ -238,6 +247,9 @@ CPU3: cpu@300 {
compatible = "qcom,kryo385";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-idle-states = <&LITTLE_CPU_SLEEP_0
&LITTLE_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
capacity-dmips-mhz = <607>;
qcom,freq-domain = <&cpufreq_hw 0>;
#cooling-cells = <2>;
......@@ -254,6 +266,9 @@ CPU4: cpu@400 {
reg = <0x0 0x400>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_400>;
......@@ -269,6 +284,9 @@ CPU5: cpu@500 {
reg = <0x0 0x500>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_500>;
......@@ -284,6 +302,9 @@ CPU6: cpu@600 {
reg = <0x0 0x600>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_600>;
......@@ -299,6 +320,9 @@ CPU7: cpu@700 {
reg = <0x0 0x700>;
enable-method = "psci";
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&BIG_CPU_SLEEP_0
&BIG_CPU_SLEEP_1
&CLUSTER_SLEEP_0>;
qcom,freq-domain = <&cpufreq_hw 1>;
#cooling-cells = <2>;
next-level-cache = <&L2_700>;
......@@ -325,26 +349,78 @@ core2 {
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
core4 {
cpu = <&CPU4>;
};
core1 {
core5 {
cpu = <&CPU5>;
};
core2 {
core6 {
cpu = <&CPU6>;
};
core3 {
core7 {
cpu = <&CPU7>;
};
};
};
idle-states {
entry-method = "psci";
LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
compatible = "arm,idle-state";
idle-state-name = "little-power-down";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <350>;
exit-latency-us = <461>;
min-residency-us = <1890>;
local-timer-stop;
};
LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
compatible = "arm,idle-state";
idle-state-name = "little-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <360>;
exit-latency-us = <531>;
min-residency-us = <3934>;
local-timer-stop;
};
BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
compatible = "arm,idle-state";
idle-state-name = "big-power-down";
arm,psci-suspend-param = <0x40000003>;
entry-latency-us = <264>;
exit-latency-us = <621>;
min-residency-us = <952>;
local-timer-stop;
};
BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
compatible = "arm,idle-state";
idle-state-name = "big-rail-power-down";
arm,psci-suspend-param = <0x40000004>;
entry-latency-us = <702>;
exit-latency-us = <1061>;
min-residency-us = <4488>;
local-timer-stop;
};
CLUSTER_SLEEP_0: cluster-sleep-0 {
compatible = "arm,idle-state";
idle-state-name = "cluster-power-down";
arm,psci-suspend-param = <0x400000F4>;
entry-latency-us = <3263>;
exit-latency-us = <6562>;
min-residency-us = <9987>;
local-timer-stop;
};
};
};
pmu {
......@@ -1671,6 +1747,64 @@ pinmux {
};
};
mss_pil: remoteproc@4080000 {
compatible = "qcom,sdm845-mss-pil";
reg = <0 0x04080000 0 0x408>, <0 0x04180000 0 0x48>;
reg-names = "qdsp6", "rmb";
interrupts-extended =
<&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
<&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "wdog", "fatal", "ready",
"handover", "stop-ack",
"shutdown-ack";
clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
<&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
<&gcc GCC_BOOT_ROM_AHB_CLK>,
<&gcc GCC_MSS_GPLL0_DIV_CLK_SRC>,
<&gcc GCC_MSS_SNOC_AXI_CLK>,
<&gcc GCC_MSS_MFAB_AXIS_CLK>,
<&gcc GCC_PRNG_AHB_CLK>,
<&rpmhcc RPMH_CXO_CLK>;
clock-names = "iface", "bus", "mem", "gpll0_mss",
"snoc_axi", "mnoc_axi", "prng", "xo";
qcom,smem-states = <&modem_smp2p_out 0>;
qcom,smem-state-names = "stop";
resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
<&pdc_reset PDC_MODEM_SYNC_RESET>;
reset-names = "mss_restart", "pdc_reset";
qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
power-domains = <&aoss_qmp 2>,
<&rpmhpd SDM845_CX>,
<&rpmhpd SDM845_MX>,
<&rpmhpd SDM845_MSS>;
power-domain-names = "load_state", "cx", "mx", "mss";
mba {
memory-region = <&mba_region>;
};
mpss {
memory-region = <&mpss_region>;
};
glink-edge {
interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
label = "modem";
qcom,remote-pid = <1>;
mboxes = <&apss_shared 12>;
};
};
gpucc: clock-controller@5090000 {
compatible = "qcom,sdm845-gpucc";
reg = <0 0x05090000 0 0x9000>;
......@@ -2106,6 +2240,133 @@ dsi1_phy: dsi-phy@ae96400 {
};
};
gpu@5000000 {
compatible = "qcom,adreno-630.2", "qcom,adreno";
#stream-id-cells = <16>;
reg = <0 0x5000000 0 0x40000>, <0 0x509e000 0 0x10>;
reg-names = "kgsl_3d0_reg_memory", "cx_mem";
/*
* Look ma, no clocks! The GPU clocks and power are
* controlled entirely by the GMU
*/
interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
iommus = <&adreno_smmu 0>;
operating-points-v2 = <&gpu_opp_table>;
qcom,gmu = <&gmu>;
zap-shader {
memory-region = <&gpu_mem>;
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-710000000 {
opp-hz = /bits/ 64 <710000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
};
opp-675000000 {
opp-hz = /bits/ 64 <675000000>;
opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
};
opp-596000000 {
opp-hz = /bits/ 64 <596000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
};
opp-520000000 {
opp-hz = /bits/ 64 <520000000>;
opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
};
opp-414000000 {
opp-hz = /bits/ 64 <414000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
};
opp-342000000 {
opp-hz = /bits/ 64 <342000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
opp-257000000 {
opp-hz = /bits/ 64 <257000000>;
opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
};
};
};
adreno_smmu: iommu@5040000 {
compatible = "qcom,sdm845-smmu-v2", "qcom,smmu-v2";
reg = <0 0x5040000 0 0x10000>;
#iommu-cells = <1>;
#global-interrupts = <2>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
<&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "bus", "iface";
power-domains = <&gpucc GPU_CX_GDSC>;
};
gmu: gmu@506a000 {
compatible="qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
reg = <0 0x506a000 0 0x30000>,
<0 0xb280000 0 0x10000>,
<0 0xb480000 0 0x10000>;
reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hfi", "gmu";
clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
<&gpucc GPU_CC_CXO_CLK>,
<&gcc GCC_DDRSS_GPU_AXI_CLK>,
<&gcc GCC_GPU_MEMNOC_GFX_CLK>;
clock-names = "gmu", "cxo", "axi", "memnoc";
power-domains = <&gpucc GPU_CX_GDSC>,
<&gpucc GPU_GX_GDSC>;
power-domain-names = "cx", "gx";
iommus = <&adreno_smmu 5>;
operating-points-v2 = <&gmu_opp_table>;
gmu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-400000000 {
opp-hz = /bits/ 64 <400000000>;
opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
};
opp-200000000 {
opp-hz = /bits/ 64 <200000000>;
opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
};
};
};
dispcc: clock-controller@af00000 {
compatible = "qcom,sdm845-dispcc";
reg = <0 0x0af00000 0 0x10000>;
......@@ -2142,6 +2403,16 @@ aoss_reset: reset-controller@c2a0000 {
#reset-cells = <1>;
};
aoss_qmp: qmp@c300000 {
compatible = "qcom,sdm845-aoss-qmp";
reg = <0 0x0c300000 0 0x100000>;
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
mboxes = <&apss_shared 0>;
#clock-cells = <0>;
#power-domain-cells = <1>;
};
spmi_bus: spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0 0x0c440000 0 0x1100>,
......
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