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Commit 78376535 authored by Juston Li's avatar Juston Li Committed by Greg Kroah-Hartman
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staging: sm750fb: use tabs for indentation 

Replace spaces with tabs for indentation to fix the checkpatch.pl error
ERROR: code indent should use tabs where possible
WARNING: please, no spaces at the start of a line
Signed-off-by: default avatarJuston Li <juston.h.li@gmail.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 32491f56
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 881 additions and 881 deletions
drivers/staging/sm750fb/ddk750_display.c
View file @ 78376535
...@@ -24,7 +24,7 @@ static void setDisplayControl(int ctrl, int dispState) ...@@ -24,7 +24,7 @@ static void setDisplayControl(int ctrl, int dispState)
/* Timing should be enabled first before enabling the plane /* Timing should be enabled first before enabling the plane
* because changing at the same time does not guarantee that * because changing at the same time does not guarantee that
* the plane will also enabled or disabled. * the plane will also enabled or disabled.
*/ */
ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg, ulDisplayCtrlReg = FIELD_SET(ulDisplayCtrlReg,
PANEL_DISPLAY_CTRL, TIMING, ENABLE); PANEL_DISPLAY_CTRL, TIMING, ENABLE);
POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg); POKE32(PANEL_DISPLAY_CTRL, ulDisplayCtrlReg);
...@@ -135,8 +135,8 @@ static void waitNextVerticalSync(int ctrl, int delay) ...@@ -135,8 +135,8 @@ static void waitNextVerticalSync(int ctrl, int delay)
if(!ctrl){ if(!ctrl){
/* primary controller */ /* primary controller */
/* Do not wait when the Primary PLL is off or display control is already off. /* Do not wait when the Primary PLL is off or display control is already off.
This will prevent the software to wait forever. */ This will prevent the software to wait forever. */
if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) == if ((FIELD_GET(PEEK32(PANEL_PLL_CTRL), PANEL_PLL_CTRL, POWER) ==
PANEL_PLL_CTRL_POWER_OFF) || PANEL_PLL_CTRL_POWER_OFF) ||
(FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) == (FIELD_GET(PEEK32(PANEL_DISPLAY_CTRL), PANEL_DISPLAY_CTRL, TIMING) ==
...@@ -145,26 +145,26 @@ static void waitNextVerticalSync(int ctrl, int delay) ...@@ -145,26 +145,26 @@ static void waitNextVerticalSync(int ctrl, int delay)
return; return;
} }
while (delay-- > 0) while (delay-- > 0)
{ {
/* Wait for end of vsync. */ /* Wait for end of vsync. */
do do
{ {
status = FIELD_GET(PEEK32(SYSTEM_CTRL), status = FIELD_GET(PEEK32(SYSTEM_CTRL),
SYSTEM_CTRL, SYSTEM_CTRL,
PANEL_VSYNC); PANEL_VSYNC);
} }
while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE); while (status == SYSTEM_CTRL_PANEL_VSYNC_ACTIVE);
/* Wait for start of vsync. */ /* Wait for start of vsync. */
do do
{ {
status = FIELD_GET(PEEK32(SYSTEM_CTRL), status = FIELD_GET(PEEK32(SYSTEM_CTRL),
SYSTEM_CTRL, SYSTEM_CTRL,
PANEL_VSYNC); PANEL_VSYNC);
} }
while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE); while (status == SYSTEM_CTRL_PANEL_VSYNC_INACTIVE);
} }
}else{ }else{
...@@ -275,33 +275,33 @@ void ddk750_setLogicalDispOut(disp_output_t output) ...@@ -275,33 +275,33 @@ void ddk750_setLogicalDispOut(disp_output_t output)
int ddk750_initDVIDisp(void) int ddk750_initDVIDisp(void)
{ {
/* Initialize DVI. If the dviInit fail and the VendorID or the DeviceID are /* Initialize DVI. If the dviInit fail and the VendorID or the DeviceID are
not zeroed, then set the failure flag. If it is zeroe, it might mean not zeroed, then set the failure flag. If it is zeroe, it might mean
that the system is in Dual CRT Monitor configuration. */ that the system is in Dual CRT Monitor configuration. */
/* De-skew enabled with default 111b value. /* De-skew enabled with default 111b value.
This will fix some artifacts problem in some mode on board 2.2. This will fix some artifacts problem in some mode on board 2.2.
Somehow this fix does not affect board 2.1. Somehow this fix does not affect board 2.1.
*/ */
if ((dviInit(1, /* Select Rising Edge */ if ((dviInit(1, /* Select Rising Edge */
1, /* Select 24-bit bus */ 1, /* Select 24-bit bus */
0, /* Select Single Edge clock */ 0, /* Select Single Edge clock */
1, /* Enable HSync as is */ 1, /* Enable HSync as is */
1, /* Enable VSync as is */ 1, /* Enable VSync as is */
1, /* Enable De-skew */ 1, /* Enable De-skew */
7, /* Set the de-skew setting to maximum setup */ 7, /* Set the de-skew setting to maximum setup */
1, /* Enable continuous Sync */ 1, /* Enable continuous Sync */
1, /* Enable PLL Filter */ 1, /* Enable PLL Filter */
4 /* Use the recommended value for PLL Filter value */ 4 /* Use the recommended value for PLL Filter value */
) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000)) ) != 0) && (dviGetVendorID() != 0x0000) && (dviGetDeviceID() != 0x0000))
{ {
return (-1); return (-1);
} }
/* TODO: Initialize other display component */ /* TODO: Initialize other display component */
/* Success */ /* Success */
return 0; return 0;
} }
drivers/staging/sm750fb/ddk750_display.h
View file @ 78376535
...@@ -8,7 +8,7 @@ ...@@ -8,7 +8,7 @@
#define PNL_2_OFFSET 0 #define PNL_2_OFFSET 0
#define PNL_2_MASK (3 << PNL_2_OFFSET) #define PNL_2_MASK (3 << PNL_2_OFFSET)
#define PNL_2_USAGE (PNL_2_MASK << 16) #define PNL_2_USAGE (PNL_2_MASK << 16)
#define PNL_2_PRI ((0 << PNL_2_OFFSET)|PNL_2_USAGE) #define PNL_2_PRI ((0 << PNL_2_OFFSET)|PNL_2_USAGE)
#define PNL_2_SEC ((2 << PNL_2_OFFSET)|PNL_2_USAGE) #define PNL_2_SEC ((2 << PNL_2_OFFSET)|PNL_2_USAGE)
......
drivers/staging/sm750fb/ddk750_dvi.c
View file @ 78376535
...@@ -12,35 +12,35 @@ ...@@ -12,35 +12,35 @@
static dvi_ctrl_device_t g_dcftSupportedDviController[] = static dvi_ctrl_device_t g_dcftSupportedDviController[] =
{ {
#ifdef DVI_CTRL_SII164 #ifdef DVI_CTRL_SII164
{ {
.pfnInit = sii164InitChip, .pfnInit = sii164InitChip,
.pfnGetVendorId = sii164GetVendorID, .pfnGetVendorId = sii164GetVendorID,
.pfnGetDeviceId = sii164GetDeviceID, .pfnGetDeviceId = sii164GetDeviceID,
#ifdef SII164_FULL_FUNCTIONS #ifdef SII164_FULL_FUNCTIONS
.pfnResetChip = sii164ResetChip, .pfnResetChip = sii164ResetChip,
.pfnGetChipString = sii164GetChipString, .pfnGetChipString = sii164GetChipString,
.pfnSetPower = sii164SetPower, .pfnSetPower = sii164SetPower,
.pfnEnableHotPlugDetection = sii164EnableHotPlugDetection, .pfnEnableHotPlugDetection = sii164EnableHotPlugDetection,
.pfnIsConnected = sii164IsConnected, .pfnIsConnected = sii164IsConnected,
.pfnCheckInterrupt = sii164CheckInterrupt, .pfnCheckInterrupt = sii164CheckInterrupt,
.pfnClearInterrupt = sii164ClearInterrupt, .pfnClearInterrupt = sii164ClearInterrupt,
#endif #endif
}, },
#endif #endif
}; };
int dviInit( int dviInit(
unsigned char edgeSelect, unsigned char edgeSelect,
unsigned char busSelect, unsigned char busSelect,
unsigned char dualEdgeClkSelect, unsigned char dualEdgeClkSelect,
unsigned char hsyncEnable, unsigned char hsyncEnable,
unsigned char vsyncEnable, unsigned char vsyncEnable,
unsigned char deskewEnable, unsigned char deskewEnable,
unsigned char deskewSetting, unsigned char deskewSetting,
unsigned char continuousSyncEnable, unsigned char continuousSyncEnable,
unsigned char pllFilterEnable, unsigned char pllFilterEnable,
unsigned char pllFilterValue unsigned char pllFilterValue
) )
{ {
dvi_ctrl_device_t *pCurrentDviCtrl; dvi_ctrl_device_t *pCurrentDviCtrl;
...@@ -48,8 +48,8 @@ int dviInit( ...@@ -48,8 +48,8 @@ int dviInit(
if(pCurrentDviCtrl->pfnInit != NULL) if(pCurrentDviCtrl->pfnInit != NULL)
{ {
return pCurrentDviCtrl->pfnInit(edgeSelect, busSelect, dualEdgeClkSelect, hsyncEnable, return pCurrentDviCtrl->pfnInit(edgeSelect, busSelect, dualEdgeClkSelect, hsyncEnable,
vsyncEnable, deskewEnable, deskewSetting, continuousSyncEnable, vsyncEnable, deskewEnable, deskewSetting, continuousSyncEnable,
pllFilterEnable, pllFilterValue); pllFilterEnable, pllFilterValue);
} }
return -1; /* error */ return -1; /* error */
} }
...@@ -64,13 +64,13 @@ int dviInit( ...@@ -64,13 +64,13 @@ int dviInit(
*/ */
unsigned short dviGetVendorID(void) unsigned short dviGetVendorID(void)
{ {
dvi_ctrl_device_t *pCurrentDviCtrl; dvi_ctrl_device_t *pCurrentDviCtrl;
pCurrentDviCtrl = g_dcftSupportedDviController; pCurrentDviCtrl = g_dcftSupportedDviController;
if (pCurrentDviCtrl != (dvi_ctrl_device_t *)0) if (pCurrentDviCtrl != (dvi_ctrl_device_t *)0)
return pCurrentDviCtrl->pfnGetVendorId(); return pCurrentDviCtrl->pfnGetVendorId();
return 0x0000; return 0x0000;
} }
...@@ -83,13 +83,13 @@ unsigned short dviGetVendorID(void) ...@@ -83,13 +83,13 @@ unsigned short dviGetVendorID(void)
*/ */
unsigned short dviGetDeviceID(void) unsigned short dviGetDeviceID(void)
{ {
dvi_ctrl_device_t *pCurrentDviCtrl; dvi_ctrl_device_t *pCurrentDviCtrl;
pCurrentDviCtrl = g_dcftSupportedDviController; pCurrentDviCtrl = g_dcftSupportedDviController;
if (pCurrentDviCtrl != (dvi_ctrl_device_t *)0) if (pCurrentDviCtrl != (dvi_ctrl_device_t *)0)
return pCurrentDviCtrl->pfnGetDeviceId(); return pCurrentDviCtrl->pfnGetDeviceId();
return 0x0000; return 0x0000;
} }
#endif #endif
......
drivers/staging/sm750fb/ddk750_help.h
View file @ 78376535
...@@ -12,8 +12,8 @@ ...@@ -12,8 +12,8 @@
#if 0 #if 0
/* if 718 big endian turned on,be aware that don't use this driver for general use,only for ppc big-endian */ /* if 718 big endian turned on,be aware that don't use this driver for general use,only for ppc big-endian */
#warning "big endian on target cpu and enable nature big endian support of 718 capability !" #warning "big endian on target cpu and enable nature big endian support of 718 capability !"
#define PEEK32(addr) __raw_readl(mmio750 + addr) #define PEEK32(addr) __raw_readl(mmio750 + addr)
#define POKE32(addr, data) __raw_writel(data, mmio750 + addr) #define POKE32(addr, data) __raw_writel(data, mmio750 + addr)
#else /* software control endianness */ #else /* software control endianness */
#define PEEK32(addr) readl(addr + mmio750) #define PEEK32(addr) readl(addr + mmio750)
#define POKE32(addr, data) writel(data, addr + mmio750) #define POKE32(addr, data) writel(data, addr + mmio750)
......
drivers/staging/sm750fb/ddk750_hwi2c.c
View file @ 78376535
...@@ -10,70 +10,70 @@ ...@@ -10,70 +10,70 @@
int hwI2CInit( int hwI2CInit(
unsigned char busSpeedMode unsigned char busSpeedMode
) )
{ {
unsigned int value; unsigned int value;
/* Enable GPIO 30 & 31 as IIC clock & data */ /* Enable GPIO 30 & 31 as IIC clock & data */
value = PEEK32(GPIO_MUX); value = PEEK32(GPIO_MUX);
value = FIELD_SET(value, GPIO_MUX, 30, I2C) | value = FIELD_SET(value, GPIO_MUX, 30, I2C) |
FIELD_SET(0, GPIO_MUX, 31, I2C); FIELD_SET(0, GPIO_MUX, 31, I2C);
POKE32(GPIO_MUX, value); POKE32(GPIO_MUX, value);
/* Enable Hardware I2C power. /* Enable Hardware I2C power.
TODO: Check if we need to enable GPIO power? TODO: Check if we need to enable GPIO power?
*/ */
enableI2C(1); enableI2C(1);
/* Enable the I2C Controller and set the bus speed mode */ /* Enable the I2C Controller and set the bus speed mode */
value = PEEK32(I2C_CTRL); value = PEEK32(I2C_CTRL);
if (busSpeedMode == 0) if (busSpeedMode == 0)
value = FIELD_SET(value, I2C_CTRL, MODE, STANDARD); value = FIELD_SET(value, I2C_CTRL, MODE, STANDARD);
else else
value = FIELD_SET(value, I2C_CTRL, MODE, FAST); value = FIELD_SET(value, I2C_CTRL, MODE, FAST);
value = FIELD_SET(value, I2C_CTRL, EN, ENABLE); value = FIELD_SET(value, I2C_CTRL, EN, ENABLE);
POKE32(I2C_CTRL, value); POKE32(I2C_CTRL, value);
return 0; return 0;
} }
void hwI2CClose(void) void hwI2CClose(void)
{ {
unsigned int value; unsigned int value;
/* Disable I2C controller */ /* Disable I2C controller */
value = PEEK32(I2C_CTRL); value = PEEK32(I2C_CTRL);
value = FIELD_SET(value, I2C_CTRL, EN, DISABLE); value = FIELD_SET(value, I2C_CTRL, EN, DISABLE);
POKE32(I2C_CTRL, value); POKE32(I2C_CTRL, value);
/* Disable I2C Power */ /* Disable I2C Power */
enableI2C(0); enableI2C(0);
/* Set GPIO 30 & 31 back as GPIO pins */ /* Set GPIO 30 & 31 back as GPIO pins */
value = PEEK32(GPIO_MUX); value = PEEK32(GPIO_MUX);
value = FIELD_SET(value, GPIO_MUX, 30, GPIO); value = FIELD_SET(value, GPIO_MUX, 30, GPIO);
value = FIELD_SET(value, GPIO_MUX, 31, GPIO); value = FIELD_SET(value, GPIO_MUX, 31, GPIO);
POKE32(GPIO_MUX, value); POKE32(GPIO_MUX, value);
} }
static long hwI2CWaitTXDone(void) static long hwI2CWaitTXDone(void)
{ {
unsigned int timeout; unsigned int timeout;
/* Wait until the transfer is completed. */ /* Wait until the transfer is completed. */
timeout = HWI2C_WAIT_TIMEOUT; timeout = HWI2C_WAIT_TIMEOUT;
while ((FIELD_GET(PEEK32(I2C_STATUS), I2C_STATUS, TX) != I2C_STATUS_TX_COMPLETED) && while ((FIELD_GET(PEEK32(I2C_STATUS), I2C_STATUS, TX) != I2C_STATUS_TX_COMPLETED) &&
(timeout != 0)) (timeout != 0))
timeout--; timeout--;
if (timeout == 0) if (timeout == 0)
return (-1); return (-1);
return 0; return 0;
} }
...@@ -91,53 +91,53 @@ static long hwI2CWaitTXDone(void) ...@@ -91,53 +91,53 @@ static long hwI2CWaitTXDone(void)
* Total number of bytes those are actually written. * Total number of bytes those are actually written.
*/ */
static unsigned int hwI2CWriteData( static unsigned int hwI2CWriteData(
unsigned char deviceAddress, unsigned char deviceAddress,
unsigned int length, unsigned int length,
unsigned char *pBuffer unsigned char *pBuffer
) )
{ {
unsigned char count, i; unsigned char count, i;
unsigned int totalBytes = 0; unsigned int totalBytes = 0;
/* Set the Device Address */ /* Set the Device Address */
POKE32(I2C_SLAVE_ADDRESS, deviceAddress & ~0x01); POKE32(I2C_SLAVE_ADDRESS, deviceAddress & ~0x01);
/* Write data. /* Write data.
* Note: * Note:
* Only 16 byte can be accessed per i2c start instruction. * Only 16 byte can be accessed per i2c start instruction.
*/ */
do do
{ {
/* Reset I2C by writing 0 to I2C_RESET register to clear the previous status. */ /* Reset I2C by writing 0 to I2C_RESET register to clear the previous status. */
POKE32(I2C_RESET, 0); POKE32(I2C_RESET, 0);
/* Set the number of bytes to be written */ /* Set the number of bytes to be written */
if (length < MAX_HWI2C_FIFO) if (length < MAX_HWI2C_FIFO)
count = length - 1; count = length - 1;
else else
count = MAX_HWI2C_FIFO - 1; count = MAX_HWI2C_FIFO - 1;
POKE32(I2C_BYTE_COUNT, count); POKE32(I2C_BYTE_COUNT, count);
/* Move the data to the I2C data register */ /* Move the data to the I2C data register */
for (i = 0; i <= count; i++) for (i = 0; i <= count; i++)
POKE32(I2C_DATA0 + i, *pBuffer++); POKE32(I2C_DATA0 + i, *pBuffer++);
/* Start the I2C */ /* Start the I2C */
POKE32(I2C_CTRL, FIELD_SET(PEEK32(I2C_CTRL), I2C_CTRL, CTRL, START)); POKE32(I2C_CTRL, FIELD_SET(PEEK32(I2C_CTRL), I2C_CTRL, CTRL, START));
/* Wait until the transfer is completed. */ /* Wait until the transfer is completed. */
if (hwI2CWaitTXDone() != 0) if (hwI2CWaitTXDone() != 0)
break; break;
/* Substract length */ /* Substract length */
length -= (count + 1); length -= (count + 1);
/* Total byte written */ /* Total byte written */
totalBytes += (count + 1); totalBytes += (count + 1);
} while (length > 0); } while (length > 0);
return totalBytes; return totalBytes;
} }
...@@ -158,53 +158,53 @@ static unsigned int hwI2CWriteData( ...@@ -158,53 +158,53 @@ static unsigned int hwI2CWriteData(
* Total number of actual bytes read from the slave device * Total number of actual bytes read from the slave device
*/ */
static unsigned int hwI2CReadData( static unsigned int hwI2CReadData(
unsigned char deviceAddress, unsigned char deviceAddress,
unsigned int length, unsigned int length,
unsigned char *pBuffer unsigned char *pBuffer
) )
{ {
unsigned char count, i; unsigned char count, i;
unsigned int totalBytes = 0; unsigned int totalBytes = 0;
/* Set the Device Address */ /* Set the Device Address */
POKE32(I2C_SLAVE_ADDRESS, deviceAddress | 0x01); POKE32(I2C_SLAVE_ADDRESS, deviceAddress | 0x01);
/* Read data and save them to the buffer. /* Read data and save them to the buffer.
* Note: * Note:
* Only 16 byte can be accessed per i2c start instruction. * Only 16 byte can be accessed per i2c start instruction.
*/ */
do do
{ {
/* Reset I2C by writing 0 to I2C_RESET register to clear all the status. */ /* Reset I2C by writing 0 to I2C_RESET register to clear all the status. */
POKE32(I2C_RESET, 0); POKE32(I2C_RESET, 0);
/* Set the number of bytes to be read */ /* Set the number of bytes to be read */
if (length <= MAX_HWI2C_FIFO) if (length <= MAX_HWI2C_FIFO)
count = length - 1; count = length - 1;
else else
count = MAX_HWI2C_FIFO - 1; count = MAX_HWI2C_FIFO - 1;
POKE32(I2C_BYTE_COUNT, count); POKE32(I2C_BYTE_COUNT, count);
/* Start the I2C */ /* Start the I2C */
POKE32(I2C_CTRL, FIELD_SET(PEEK32(I2C_CTRL), I2C_CTRL, CTRL, START)); POKE32(I2C_CTRL, FIELD_SET(PEEK32(I2C_CTRL), I2C_CTRL, CTRL, START));
/* Wait until transaction done. */ /* Wait until transaction done. */
if (hwI2CWaitTXDone() != 0) if (hwI2CWaitTXDone() != 0)
break; break;
/* Save the data to the given buffer */ /* Save the data to the given buffer */
for (i = 0; i <= count; i++) for (i = 0; i <= count; i++)
*pBuffer++ = PEEK32(I2C_DATA0 + i); *pBuffer++ = PEEK32(I2C_DATA0 + i);
/* Substract length by 16 */ /* Substract length by 16 */
length -= (count + 1); length -= (count + 1);
/* Number of bytes read. */ /* Number of bytes read. */
totalBytes += (count + 1); totalBytes += (count + 1);
} while (length > 0); } while (length > 0);
return totalBytes; return totalBytes;
} }
...@@ -222,16 +222,16 @@ static unsigned int hwI2CReadData( ...@@ -222,16 +222,16 @@ static unsigned int hwI2CReadData(
* Register value * Register value
*/ */
unsigned char hwI2CReadReg( unsigned char hwI2CReadReg(
unsigned char deviceAddress, unsigned char deviceAddress,
unsigned char registerIndex unsigned char registerIndex
) )
{ {
unsigned char value = (0xFF); unsigned char value = (0xFF);
if (hwI2CWriteData(deviceAddress, 1, &registerIndex) == 1) if (hwI2CWriteData(deviceAddress, 1, &registerIndex) == 1)
hwI2CReadData(deviceAddress, 1, &value); hwI2CReadData(deviceAddress, 1, &value);
return value; return value;
} }
...@@ -252,19 +252,19 @@ unsigned char hwI2CReadReg( ...@@ -252,19 +252,19 @@ unsigned char hwI2CReadReg(
* -1 - Fail * -1 - Fail
*/ */
int hwI2CWriteReg( int hwI2CWriteReg(
unsigned char deviceAddress, unsigned char deviceAddress,
unsigned char registerIndex, unsigned char registerIndex,
unsigned char data unsigned char data
) )
{ {
unsigned char value[2]; unsigned char value[2];
value[0] = registerIndex; value[0] = registerIndex;
value[1] = data; value[1] = data;
if (hwI2CWriteData(deviceAddress, 2, value) == 2) if (hwI2CWriteData(deviceAddress, 2, value) == 2)
return 0; return 0;
return (-1); return (-1);
} }
......
drivers/staging/sm750fb/ddk750_mode.c
View file @ 78376535
...@@ -20,54 +20,54 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam, ...@@ -20,54 +20,54 @@ static unsigned long displayControlAdjust_SM750LE(mode_parameter_t *pModeParam,
x = pModeParam->horizontal_display_end; x = pModeParam->horizontal_display_end;
y = pModeParam->vertical_display_end; y = pModeParam->vertical_display_end;
/* SM750LE has to set up the top-left and bottom-right /* SM750LE has to set up the top-left and bottom-right
registers as well. registers as well.
Note that normal SM750/SM718 only use those two register for Note that normal SM750/SM718 only use those two register for
auto-centering mode. auto-centering mode.
*/ */
POKE32(CRT_AUTO_CENTERING_TL, POKE32(CRT_AUTO_CENTERING_TL,
FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, TOP, 0) FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, TOP, 0)
| FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, LEFT, 0)); | FIELD_VALUE(0, CRT_AUTO_CENTERING_TL, LEFT, 0));
POKE32(CRT_AUTO_CENTERING_BR, POKE32(CRT_AUTO_CENTERING_BR,
FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, BOTTOM, y-1) FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, BOTTOM, y-1)
| FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, RIGHT, x-1)); | FIELD_VALUE(0, CRT_AUTO_CENTERING_BR, RIGHT, x-1));
/* Assume common fields in dispControl have been properly set before /* Assume common fields in dispControl have been properly set before
calling this function. calling this function.
This function only sets the extra fields in dispControl. This function only sets the extra fields in dispControl.
*/ */
/* Clear bit 29:27 of display control register */ /* Clear bit 29:27 of display control register */
dispControl &= FIELD_CLEAR(CRT_DISPLAY_CTRL, CLK); dispControl &= FIELD_CLEAR(CRT_DISPLAY_CTRL, CLK);
/* Set bit 29:27 of display control register for the right clock */ /* Set bit 29:27 of display control register for the right clock */
/* Note that SM750LE only need to supported 7 resoluitons. */ /* Note that SM750LE only need to supported 7 resoluitons. */
if ( x == 800 && y == 600 ) if ( x == 800 && y == 600 )
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL41); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL41);
else if (x == 1024 && y == 768) else if (x == 1024 && y == 768)
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL65); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL65);
else if (x == 1152 && y == 864) else if (x == 1152 && y == 864)
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80);
else if (x == 1280 && y == 768) else if (x == 1280 && y == 768)
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL80);
else if (x == 1280 && y == 720) else if (x == 1280 && y == 720)
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL74); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL74);
else if (x == 1280 && y == 960) else if (x == 1280 && y == 960)
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108);
else if (x == 1280 && y == 1024) else if (x == 1280 && y == 1024)
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL108);
else /* default to VGA clock */ else /* default to VGA clock */
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL25); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLK, PLL25);
/* Set bit 25:24 of display controller */ /* Set bit 25:24 of display controller */
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CRTSELECT, CRT); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CRTSELECT, CRT);
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, RGBBIT, 24BIT);
/* Set bit 14 of display controller */ /* Set bit 14 of display controller */
dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLOCK_PHASE, ACTIVE_LOW); dispControl = FIELD_SET(dispControl, CRT_DISPLAY_CTRL, CLOCK_PHASE, ACTIVE_LOW);
POKE32(CRT_DISPLAY_CTRL, dispControl); POKE32(CRT_DISPLAY_CTRL, dispControl);
return dispControl; return dispControl;
} }
...@@ -84,21 +84,21 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) ...@@ -84,21 +84,21 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
{ {
/* programe secondary pixel clock */ /* programe secondary pixel clock */
POKE32(CRT_PLL_CTRL, formatPllReg(pll)); POKE32(CRT_PLL_CTRL, formatPllReg(pll));
POKE32(CRT_HORIZONTAL_TOTAL, POKE32(CRT_HORIZONTAL_TOTAL,
FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1) FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1)
| FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1)); | FIELD_VALUE(0, CRT_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1));
POKE32(CRT_HORIZONTAL_SYNC, POKE32(CRT_HORIZONTAL_SYNC,
FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width) FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width)
| FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1)); | FIELD_VALUE(0, CRT_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1));
POKE32(CRT_VERTICAL_TOTAL, POKE32(CRT_VERTICAL_TOTAL,
FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1) FIELD_VALUE(0, CRT_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1)
| FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1)); | FIELD_VALUE(0, CRT_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1));
POKE32(CRT_VERTICAL_SYNC, POKE32(CRT_VERTICAL_SYNC,
FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) FIELD_VALUE(0, CRT_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
| FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); | FIELD_VALUE(0, CRT_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| ulTmpValue = FIELD_VALUE(0, CRT_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)|
...@@ -125,39 +125,39 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll) ...@@ -125,39 +125,39 @@ static int programModeRegisters(mode_parameter_t *pModeParam, pll_value_t *pll)
unsigned int ulReservedBits; unsigned int ulReservedBits;
POKE32(PANEL_PLL_CTRL, formatPllReg(pll)); POKE32(PANEL_PLL_CTRL, formatPllReg(pll));
POKE32(PANEL_HORIZONTAL_TOTAL, POKE32(PANEL_HORIZONTAL_TOTAL,
FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1) FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, TOTAL, pModeParam->horizontal_total - 1)
| FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1)); | FIELD_VALUE(0, PANEL_HORIZONTAL_TOTAL, DISPLAY_END, pModeParam->horizontal_display_end - 1));
POKE32(PANEL_HORIZONTAL_SYNC, POKE32(PANEL_HORIZONTAL_SYNC,
FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width) FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, WIDTH, pModeParam->horizontal_sync_width)
| FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1)); | FIELD_VALUE(0, PANEL_HORIZONTAL_SYNC, START, pModeParam->horizontal_sync_start - 1));
POKE32(PANEL_VERTICAL_TOTAL, POKE32(PANEL_VERTICAL_TOTAL,
FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1) FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, TOTAL, pModeParam->vertical_total - 1)
| FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1)); | FIELD_VALUE(0, PANEL_VERTICAL_TOTAL, DISPLAY_END, pModeParam->vertical_display_end - 1));
POKE32(PANEL_VERTICAL_SYNC, POKE32(PANEL_VERTICAL_SYNC,
FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height) FIELD_VALUE(0, PANEL_VERTICAL_SYNC, HEIGHT, pModeParam->vertical_sync_height)
| FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1)); | FIELD_VALUE(0, PANEL_VERTICAL_SYNC, START, pModeParam->vertical_sync_start - 1));
ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)| ulTmpValue = FIELD_VALUE(0, PANEL_DISPLAY_CTRL, VSYNC_PHASE, pModeParam->vertical_sync_polarity)|
FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)| FIELD_VALUE(0, PANEL_DISPLAY_CTRL, HSYNC_PHASE, pModeParam->horizontal_sync_polarity)|
FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity)| FIELD_VALUE(0, PANEL_DISPLAY_CTRL, CLOCK_PHASE, pModeParam->clock_phase_polarity)|
FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)| FIELD_SET(0, PANEL_DISPLAY_CTRL, TIMING, ENABLE)|
FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE); FIELD_SET(0, PANEL_DISPLAY_CTRL, PLANE, ENABLE);
ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) | ulReservedBits = FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_1_MASK, ENABLE) |
FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) | FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_2_MASK, ENABLE) |
FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)| FIELD_SET(0, PANEL_DISPLAY_CTRL, RESERVED_3_MASK, ENABLE)|
FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW); FIELD_SET(0, PANEL_DISPLAY_CTRL, VSYNC, ACTIVE_LOW);
ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits) ulReg = (PEEK32(PANEL_DISPLAY_CTRL) & ~ulReservedBits)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE) & FIELD_CLEAR(PANEL_DISPLAY_CTRL, CLOCK_PHASE)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE) & FIELD_CLEAR(PANEL_DISPLAY_CTRL, VSYNC_PHASE)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE) & FIELD_CLEAR(PANEL_DISPLAY_CTRL, HSYNC_PHASE)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING) & FIELD_CLEAR(PANEL_DISPLAY_CTRL, TIMING)
& FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE); & FIELD_CLEAR(PANEL_DISPLAY_CTRL, PLANE);
/* May a hardware bug or just my test chip (not confirmed). /* May a hardware bug or just my test chip (not confirmed).
......
drivers/staging/sm750fb/ddk750_mode.h
View file @ 78376535
...@@ -5,35 +5,35 @@ ...@@ -5,35 +5,35 @@
typedef enum _spolarity_t typedef enum _spolarity_t
{ {
POS = 0, /* positive */ POS = 0, /* positive */
NEG, /* negative */ NEG, /* negative */
} }
spolarity_t; spolarity_t;
typedef struct _mode_parameter_t typedef struct _mode_parameter_t
{ {
/* Horizontal timing. */ /* Horizontal timing. */
unsigned long horizontal_total; unsigned long horizontal_total;
unsigned long horizontal_display_end; unsigned long horizontal_display_end;
unsigned long horizontal_sync_start; unsigned long horizontal_sync_start;
unsigned long horizontal_sync_width; unsigned long horizontal_sync_width;
spolarity_t horizontal_sync_polarity; spolarity_t horizontal_sync_polarity;
/* Vertical timing. */ /* Vertical timing. */
unsigned long vertical_total; unsigned long vertical_total;
unsigned long vertical_display_end; unsigned long vertical_display_end;
unsigned long vertical_sync_start; unsigned long vertical_sync_start;
unsigned long vertical_sync_height; unsigned long vertical_sync_height;
spolarity_t vertical_sync_polarity; spolarity_t vertical_sync_polarity;
/* Refresh timing. */ /* Refresh timing. */
unsigned long pixel_clock; unsigned long pixel_clock;
unsigned long horizontal_frequency; unsigned long horizontal_frequency;
unsigned long vertical_frequency; unsigned long vertical_frequency;
/* Clock Phase. This clock phase only applies to Panel. */ /* Clock Phase. This clock phase only applies to Panel. */
spolarity_t clock_phase_polarity; spolarity_t clock_phase_polarity;
} }
mode_parameter_t; mode_parameter_t;
......
drivers/staging/sm750fb/ddk750_power.c
View file @ 78376535
...@@ -19,7 +19,7 @@ unsigned int getPowerMode(void) ...@@ -19,7 +19,7 @@ unsigned int getPowerMode(void)
{ {
if(getChipType() == SM750LE) if(getChipType() == SM750LE)
return 0; return 0;
return (FIELD_GET(PEEK32(POWER_MODE_CTRL), POWER_MODE_CTRL, MODE)); return (FIELD_GET(PEEK32(POWER_MODE_CTRL), POWER_MODE_CTRL, MODE));
} }
...@@ -29,76 +29,76 @@ unsigned int getPowerMode(void) ...@@ -29,76 +29,76 @@ unsigned int getPowerMode(void)
*/ */
void setPowerMode(unsigned int powerMode) void setPowerMode(unsigned int powerMode)
{ {
unsigned int control_value = 0; unsigned int control_value = 0;
control_value = PEEK32(POWER_MODE_CTRL); control_value = PEEK32(POWER_MODE_CTRL);
if(getChipType() == SM750LE) if(getChipType() == SM750LE)
return; return;
switch (powerMode) switch (powerMode)
{ {
case POWER_MODE_CTRL_MODE_MODE0: case POWER_MODE_CTRL_MODE_MODE0:
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE0); control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE0);
break; break;
case POWER_MODE_CTRL_MODE_MODE1: case POWER_MODE_CTRL_MODE_MODE1:
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE1); control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, MODE1);
break; break;
case POWER_MODE_CTRL_MODE_SLEEP: case POWER_MODE_CTRL_MODE_SLEEP:
control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, SLEEP); control_value = FIELD_SET(control_value, POWER_MODE_CTRL, MODE, SLEEP);
break; break;
default: default:
break; break;
} }
/* Set up other fields in Power Control Register */ /* Set up other fields in Power Control Register */
if (powerMode == POWER_MODE_CTRL_MODE_SLEEP) if (powerMode == POWER_MODE_CTRL_MODE_SLEEP)
{ {
control_value = control_value =
#ifdef VALIDATION_CHIP #ifdef VALIDATION_CHIP
FIELD_SET( control_value, POWER_MODE_CTRL, 336CLK, OFF) | FIELD_SET( control_value, POWER_MODE_CTRL, 336CLK, OFF) |
#endif #endif
FIELD_SET( control_value, POWER_MODE_CTRL, OSC_INPUT, OFF); FIELD_SET( control_value, POWER_MODE_CTRL, OSC_INPUT, OFF);
} }
else else
{ {
control_value = control_value =
#ifdef VALIDATION_CHIP #ifdef VALIDATION_CHIP
FIELD_SET( control_value, POWER_MODE_CTRL, 336CLK, ON) | FIELD_SET( control_value, POWER_MODE_CTRL, 336CLK, ON) |
#endif #endif
FIELD_SET( control_value, POWER_MODE_CTRL, OSC_INPUT, ON); FIELD_SET( control_value, POWER_MODE_CTRL, OSC_INPUT, ON);
} }
/* Program new power mode. */ /* Program new power mode. */
POKE32(POWER_MODE_CTRL, control_value); POKE32(POWER_MODE_CTRL, control_value);
} }
void setCurrentGate(unsigned int gate) void setCurrentGate(unsigned int gate)
{ {
unsigned int gate_reg; unsigned int gate_reg;
unsigned int mode; unsigned int mode;
/* Get current power mode. */ /* Get current power mode. */
mode = getPowerMode(); mode = getPowerMode();
switch (mode) switch (mode)
{ {
case POWER_MODE_CTRL_MODE_MODE0: case POWER_MODE_CTRL_MODE_MODE0:
gate_reg = MODE0_GATE; gate_reg = MODE0_GATE;
break; break;
case POWER_MODE_CTRL_MODE_MODE1: case POWER_MODE_CTRL_MODE_MODE1:
gate_reg = MODE1_GATE; gate_reg = MODE1_GATE;
break; break;
default: default:
gate_reg = MODE0_GATE; gate_reg = MODE0_GATE;
break; break;
} }
POKE32(gate_reg, gate); POKE32(gate_reg, gate);
} }
...@@ -108,21 +108,21 @@ void setCurrentGate(unsigned int gate) ...@@ -108,21 +108,21 @@ void setCurrentGate(unsigned int gate)
*/ */
void enable2DEngine(unsigned int enable) void enable2DEngine(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
{ {
gate = FIELD_SET(gate, CURRENT_GATE, DE, ON); gate = FIELD_SET(gate, CURRENT_GATE, DE, ON);
gate = FIELD_SET(gate, CURRENT_GATE, CSC, ON); gate = FIELD_SET(gate, CURRENT_GATE, CSC, ON);
} }
else else
{ {
gate = FIELD_SET(gate, CURRENT_GATE, DE, OFF); gate = FIELD_SET(gate, CURRENT_GATE, DE, OFF);
gate = FIELD_SET(gate, CURRENT_GATE, CSC, OFF); gate = FIELD_SET(gate, CURRENT_GATE, CSC, OFF);
} }
setCurrentGate(gate); setCurrentGate(gate);
} }
...@@ -131,58 +131,58 @@ void enable2DEngine(unsigned int enable) ...@@ -131,58 +131,58 @@ void enable2DEngine(unsigned int enable)
*/ */
void enableZVPort(unsigned int enable) void enableZVPort(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
/* Enable ZV Port Gate */ /* Enable ZV Port Gate */
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
{ {
gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, ON); gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, ON);
#if 1 #if 1
/* Using Software I2C */ /* Using Software I2C */
gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON); gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON);
#else #else
/* Using Hardware I2C */ /* Using Hardware I2C */
gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON); gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON);
#endif #endif
} }
else else
{ {
/* Disable ZV Port Gate. There is no way to know whether the GPIO pins are being used /* Disable ZV Port Gate. There is no way to know whether the GPIO pins are being used
or not. Therefore, do not disable the GPIO gate. */ or not. Therefore, do not disable the GPIO gate. */
gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, OFF); gate = FIELD_SET(gate, CURRENT_GATE, ZVPORT, OFF);
} }
setCurrentGate(gate); setCurrentGate(gate);
} }
void enableSSP(unsigned int enable) void enableSSP(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
/* Enable SSP Gate */ /* Enable SSP Gate */
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
gate = FIELD_SET(gate, CURRENT_GATE, SSP, ON); gate = FIELD_SET(gate, CURRENT_GATE, SSP, ON);
else else
gate = FIELD_SET(gate, CURRENT_GATE, SSP, OFF); gate = FIELD_SET(gate, CURRENT_GATE, SSP, OFF);
setCurrentGate(gate); setCurrentGate(gate);
} }
void enableDMA(unsigned int enable) void enableDMA(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
/* Enable DMA Gate */ /* Enable DMA Gate */
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
gate = FIELD_SET(gate, CURRENT_GATE, DMA, ON); gate = FIELD_SET(gate, CURRENT_GATE, DMA, ON);
else else
gate = FIELD_SET(gate, CURRENT_GATE, DMA, OFF); gate = FIELD_SET(gate, CURRENT_GATE, DMA, OFF);
setCurrentGate(gate); setCurrentGate(gate);
} }
/* /*
...@@ -190,16 +190,16 @@ void enableDMA(unsigned int enable) ...@@ -190,16 +190,16 @@ void enableDMA(unsigned int enable)
*/ */
void enableGPIO(unsigned int enable) void enableGPIO(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
/* Enable GPIO Gate */ /* Enable GPIO Gate */
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON); gate = FIELD_SET(gate, CURRENT_GATE, GPIO, ON);
else else
gate = FIELD_SET(gate, CURRENT_GATE, GPIO, OFF); gate = FIELD_SET(gate, CURRENT_GATE, GPIO, OFF);
setCurrentGate(gate); setCurrentGate(gate);
} }
/* /*
...@@ -207,16 +207,16 @@ void enableGPIO(unsigned int enable) ...@@ -207,16 +207,16 @@ void enableGPIO(unsigned int enable)
*/ */
void enablePWM(unsigned int enable) void enablePWM(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
/* Enable PWM Gate */ /* Enable PWM Gate */
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
gate = FIELD_SET(gate, CURRENT_GATE, PWM, ON); gate = FIELD_SET(gate, CURRENT_GATE, PWM, ON);
else else
gate = FIELD_SET(gate, CURRENT_GATE, PWM, OFF); gate = FIELD_SET(gate, CURRENT_GATE, PWM, OFF);
setCurrentGate(gate); setCurrentGate(gate);
} }
/* /*
...@@ -224,16 +224,16 @@ void enablePWM(unsigned int enable) ...@@ -224,16 +224,16 @@ void enablePWM(unsigned int enable)
*/ */
void enableI2C(unsigned int enable) void enableI2C(unsigned int enable)
{ {
uint32_t gate; uint32_t gate;
/* Enable I2C Gate */ /* Enable I2C Gate */
gate = PEEK32(CURRENT_GATE); gate = PEEK32(CURRENT_GATE);
if (enable) if (enable)
gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON); gate = FIELD_SET(gate, CURRENT_GATE, I2C, ON);
else else
gate = FIELD_SET(gate, CURRENT_GATE, I2C, OFF); gate = FIELD_SET(gate, CURRENT_GATE, I2C, OFF);
setCurrentGate(gate); setCurrentGate(gate);
} }
drivers/staging/sm750fb/ddk750_power.h
View file @ 78376535
...@@ -3,10 +3,10 @@ ...@@ -3,10 +3,10 @@
typedef enum _DPMS_t typedef enum _DPMS_t
{ {
crtDPMS_ON = 0x0, crtDPMS_ON = 0x0,
crtDPMS_STANDBY = 0x1, crtDPMS_STANDBY = 0x1,
crtDPMS_SUSPEND = 0x2, crtDPMS_SUSPEND = 0x2,
crtDPMS_OFF = 0x3, crtDPMS_OFF = 0x3,
} }
DPMS_t; DPMS_t;
......
drivers/staging/sm750fb/ddk750_reg.h
View file @ 78376535
...@@ -1640,9 +1640,9 @@ ...@@ -1640,9 +1640,9 @@
/* CRT Graphics Control */ /* CRT Graphics Control */
#define CRT_DISPLAY_CTRL 0x080200 #define CRT_DISPLAY_CTRL 0x080200
#define CRT_DISPLAY_CTRL_RESERVED_1_MASK 31:27 #define CRT_DISPLAY_CTRL_RESERVED_1_MASK 31:27
#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0 #define CRT_DISPLAY_CTRL_RESERVED_1_MASK_DISABLE 0
#define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 0x1F #define CRT_DISPLAY_CTRL_RESERVED_1_MASK_ENABLE 0x1F
/* SM750LE definition */ /* SM750LE definition */
#define CRT_DISPLAY_CTRL_DPMS 31:30 #define CRT_DISPLAY_CTRL_DPMS 31:30
...@@ -1664,9 +1664,9 @@ ...@@ -1664,9 +1664,9 @@
#define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0 #define CRT_DISPLAY_CTRL_SHIFT_VGA_DAC_ENABLE 0
#define CRT_DISPLAY_CTRL_RESERVED_2_MASK 25:24 #define CRT_DISPLAY_CTRL_RESERVED_2_MASK 25:24
#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 3 #define CRT_DISPLAY_CTRL_RESERVED_2_MASK_ENABLE 3
#define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0 #define CRT_DISPLAY_CTRL_RESERVED_2_MASK_DISABLE 0
/* SM750LE definition */ /* SM750LE definition */
#define CRT_DISPLAY_CTRL_CRTSELECT 25:25 #define CRT_DISPLAY_CTRL_CRTSELECT 25:25
...@@ -1677,11 +1677,11 @@ ...@@ -1677,11 +1677,11 @@
#define CRT_DISPLAY_CTRL_RGBBIT_12BIT 1 #define CRT_DISPLAY_CTRL_RGBBIT_12BIT 1
#define CRT_DISPLAY_CTRL_RESERVED_3_MASK 15:15 #define CRT_DISPLAY_CTRL_RESERVED_3_MASK 15:15
#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0 #define CRT_DISPLAY_CTRL_RESERVED_3_MASK_DISABLE 0
#define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1 #define CRT_DISPLAY_CTRL_RESERVED_3_MASK_ENABLE 1
#define CRT_DISPLAY_CTRL_RESERVED_4_MASK 9:9 #define CRT_DISPLAY_CTRL_RESERVED_4_MASK 9:9
#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE 0 #define CRT_DISPLAY_CTRL_RESERVED_4_MASK_DISABLE 0
#define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE 1 #define CRT_DISPLAY_CTRL_RESERVED_4_MASK_ENABLE 1
...@@ -1882,7 +1882,7 @@ ...@@ -1882,7 +1882,7 @@
#endif #endif
/* sm750le new register to control panel output */ /* sm750le new register to control panel output */
#define DISPLAY_CONTROL_750LE 0x80288 #define DISPLAY_CONTROL_750LE 0x80288
/* Palette RAM */ /* Palette RAM */
/* Panel Palette register starts at 0x080400 ~ 0x0807FC */ /* Panel Palette register starts at 0x080400 ~ 0x0807FC */
......
drivers/staging/sm750fb/ddk750_sii164.c
View file @ 78376535
This diff is collapsed.
drivers/staging/sm750fb/ddk750_sii164.h
View file @ 78376535
...@@ -6,25 +6,25 @@ ...@@ -6,25 +6,25 @@
/* Hot Plug detection mode structure */ /* Hot Plug detection mode structure */
typedef enum _sii164_hot_plug_mode_t typedef enum _sii164_hot_plug_mode_t
{ {
SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */ SII164_HOTPLUG_DISABLE = 0, /* Disable Hot Plug output bit (always high). */
SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */ SII164_HOTPLUG_USE_MDI, /* Use Monitor Detect Interrupt bit. */
SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */ SII164_HOTPLUG_USE_RSEN, /* Use Receiver Sense detect bit. */
SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */ SII164_HOTPLUG_USE_HTPLG /* Use Hot Plug detect bit. */
} sii164_hot_plug_mode_t; } sii164_hot_plug_mode_t;
/* Silicon Image SiI164 chip prototype */ /* Silicon Image SiI164 chip prototype */
long sii164InitChip( long sii164InitChip(
unsigned char edgeSelect, unsigned char edgeSelect,
unsigned char busSelect, unsigned char busSelect,
unsigned char dualEdgeClkSelect, unsigned char dualEdgeClkSelect,
unsigned char hsyncEnable, unsigned char hsyncEnable,
unsigned char vsyncEnable, unsigned char vsyncEnable,
unsigned char deskewEnable, unsigned char deskewEnable,
unsigned char deskewSetting, unsigned char deskewSetting,
unsigned char continuousSyncEnable, unsigned char continuousSyncEnable,
unsigned char pllFilterEnable, unsigned char pllFilterEnable,
unsigned char pllFilterValue unsigned char pllFilterValue
); );
unsigned short sii164GetVendorID(void); unsigned short sii164GetVendorID(void);
......
drivers/staging/sm750fb/sm750.h
View file @ 78376535
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
#define FB_ACCEL_SMI 0xab #define FB_ACCEL_SMI 0xab
/* please use revision id to distinguish sm750le and sm750*/ /* please use revision id to distinguish sm750le and sm750*/
#define SPC_SM750 0 #define SPC_SM750 0
#define MB(x) ((x)<<20) #define MB(x) ((x)<<20)
#define MHZ(x) ((x) * 1000000) #define MHZ(x) ((x) * 1000000)
...@@ -38,8 +38,8 @@ struct lynx_accel{ ...@@ -38,8 +38,8 @@ struct lynx_accel{
}; };
/* lynx_share stands for a presentation of two frame buffer /* lynx_share stands for a presentation of two frame buffer
that use one smi adaptor , it is similar to a basic class of C++ that use one smi adaptor , it is similar to a basic class of C++
*/ */
struct lynx_share{ struct lynx_share{
/* common members */ /* common members */
...@@ -115,7 +115,7 @@ struct lynxfb_crtc{ ...@@ -115,7 +115,7 @@ struct lynxfb_crtc{
int(*proc_checkMode)(struct lynxfb_crtc*, struct fb_var_screeninfo*); int(*proc_checkMode)(struct lynxfb_crtc*, struct fb_var_screeninfo*);
int(*proc_setColReg)(struct lynxfb_crtc*, ushort, ushort, ushort, ushort); int(*proc_setColReg)(struct lynxfb_crtc*, ushort, ushort, ushort, ushort);
void (*clear)(struct lynxfb_crtc*); void (*clear)(struct lynxfb_crtc*);
/* pan display */ /* pan display */
int (*proc_panDisplay)(struct lynxfb_crtc *, int (*proc_panDisplay)(struct lynxfb_crtc *,
const struct fb_var_screeninfo *, const struct fb_var_screeninfo *,
const struct fb_info *); const struct fb_info *);
...@@ -126,17 +126,17 @@ struct lynxfb_crtc{ ...@@ -126,17 +126,17 @@ struct lynxfb_crtc{
struct lynxfb_output{ struct lynxfb_output{
int dpms; int dpms;
int paths; int paths;
/* which paths(s) this output stands for,for sm750: /* which paths(s) this output stands for,for sm750:
paths=1:means output for panel paths paths=1:means output for panel paths
paths=2:means output for crt paths paths=2:means output for crt paths
paths=3:means output for both panel and crt paths paths=3:means output for both panel and crt paths
*/ */
int *channel; int *channel;
/* which channel these outputs linked with,for sm750: /* which channel these outputs linked with,for sm750:
*channel=0 means primary channel *channel=0 means primary channel
*channel=1 means secondary channel *channel=1 means secondary channel
output->channel ==> &crtc->channel output->channel ==> &crtc->channel
*/ */
void *priv; void *priv;
...@@ -165,7 +165,7 @@ struct lynxfb_par{ ...@@ -165,7 +165,7 @@ struct lynxfb_par{
#define PS_TO_HZ(ps) \ #define PS_TO_HZ(ps) \
({ \ ({ \
unsigned long long hz = 1000*1000*1000*1000ULL; \ unsigned long long hz = 1000*1000*1000*1000ULL; \
do_div(hz, ps); \ do_div(hz, ps); \
(unsigned long)hz;}) (unsigned long)hz;})
......
drivers/staging/sm750fb/sm750_accel.c
View file @ 78376535
This diff is collapsed.
drivers/staging/sm750fb/sm750_accel.h
View file @ 78376535
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
/* notes: below address are the offset value from de_base_address (0x100000)*/ /* notes: below address are the offset value from de_base_address (0x100000)*/
/* for sm718/750/502 de_base is at mmreg_1mb*/ /* for sm718/750/502 de_base is at mmreg_1mb*/
#define DE_BASE_ADDR_TYPE1 0x100000 #define DE_BASE_ADDR_TYPE1 0x100000
/* for sm712,de_base is at mmreg_32kb */ /* for sm712,de_base is at mmreg_32kb */
#define DE_BASE_ADDR_TYPE2 0x8000 #define DE_BASE_ADDR_TYPE2 0x8000
/* for sm722,de_base is at mmreg_0 */ /* for sm722,de_base is at mmreg_0 */
...@@ -26,7 +26,7 @@ ...@@ -26,7 +26,7 @@
#define DE_SOURCE_WRAP_ENABLE 1 #define DE_SOURCE_WRAP_ENABLE 1
#define DE_SOURCE_X_K1 29:16 #define DE_SOURCE_X_K1 29:16
#define DE_SOURCE_Y_K2 15:0 #define DE_SOURCE_Y_K2 15:0
#define DE_SOURCE_X_K1_MONO 20:16 #define DE_SOURCE_X_K1_MONO 20:16
#define DE_DESTINATION 0x4 #define DE_DESTINATION 0x4
#define DE_DESTINATION_WRAP 31:31 #define DE_DESTINATION_WRAP 31:31
......
drivers/staging/sm750fb/sm750_help.h
View file @ 78376535
...@@ -11,9 +11,9 @@ ...@@ -11,9 +11,9 @@
#define GET_FIELD(d, f) (((d) >> _LSB(f)) & RAW_MASK(f)) #define GET_FIELD(d, f) (((d) >> _LSB(f)) & RAW_MASK(f))
#define TEST_FIELD(d, f, v) (GET_FIELD(d, f) == f ## _ ## v) #define TEST_FIELD(d, f, v) (GET_FIELD(d, f) == f ## _ ## v)
#define SET_FIELD(d, f, v) (((d) & ~GET_MASK(f)) | \ #define SET_FIELD(d, f, v) (((d) & ~GET_MASK(f)) | \
(((f ## _ ## v) & RAW_MASK(f)) << _LSB(f))) (((f ## _ ## v) & RAW_MASK(f)) << _LSB(f)))
#define SET_FIELDV(d, f, v) (((d) & ~GET_MASK(f)) | \ #define SET_FIELDV(d, f, v) (((d) & ~GET_MASK(f)) | \
(((v) & RAW_MASK(f)) << _LSB(f))) (((v) & RAW_MASK(f)) << _LSB(f)))
/* Internal macros */ /* Internal macros */
#define _F_START(f) (0 ? f) #define _F_START(f) (0 ? f)
...@@ -26,24 +26,24 @@ ...@@ -26,24 +26,24 @@
/* Global macros */ /* Global macros */
#define FIELD_GET(x, reg, field) \ #define FIELD_GET(x, reg, field) \
( \ ( \
_F_NORMALIZE((x), reg ## _ ## field) \ _F_NORMALIZE((x), reg ## _ ## field) \
) )
#define FIELD_SET(x, reg, field, value) \ #define FIELD_SET(x, reg, field, value) \
( \ ( \
(x & ~_F_MASK(reg ## _ ## field)) \ (x & ~_F_MASK(reg ## _ ## field)) \
| _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \ | _F_DENORMALIZE(reg ## _ ## field ## _ ## value, reg ## _ ## field) \
) )
#define FIELD_VALUE(x, reg, field, value) \ #define FIELD_VALUE(x, reg, field, value) \
( \ ( \
(x & ~_F_MASK(reg ## _ ## field)) \ (x & ~_F_MASK(reg ## _ ## field)) \
| _F_DENORMALIZE(value, reg ## _ ## field) \ | _F_DENORMALIZE(value, reg ## _ ## field) \
) )
#define FIELD_CLEAR(reg, field) \ #define FIELD_CLEAR(reg, field) \
( \ ( \
~ _F_MASK(reg ## _ ## field) \ ~ _F_MASK(reg ## _ ## field) \
) )
/* Field Macros */ /* Field Macros */
...@@ -55,20 +55,20 @@ ...@@ -55,20 +55,20 @@
#define FIELD_DENORMALIZE(field, value) (((value) << FIELD_START(field)) & FIELD_MASK(field)) #define FIELD_DENORMALIZE(field, value) (((value) << FIELD_START(field)) & FIELD_MASK(field))
#define FIELD_INIT(reg, field, value) FIELD_DENORMALIZE(reg ## _ ## field, \ #define FIELD_INIT(reg, field, value) FIELD_DENORMALIZE(reg ## _ ## field, \
reg ## _ ## field ## _ ## value) reg ## _ ## field ## _ ## value)
#define FIELD_INIT_VAL(reg, field, value) \ #define FIELD_INIT_VAL(reg, field, value) \
(FIELD_DENORMALIZE(reg ## _ ## field, value)) (FIELD_DENORMALIZE(reg ## _ ## field, value))
#define FIELD_VAL_SET(x, r, f, v) x = x & ~FIELD_MASK(r ## _ ## f) \ #define FIELD_VAL_SET(x, r, f, v) x = x & ~FIELD_MASK(r ## _ ## f) \
| FIELD_DENORMALIZE(r ## _ ## f, r ## _ ## f ## _ ## v) | FIELD_DENORMALIZE(r ## _ ## f, r ## _ ## f ## _ ## v)
#define RGB(r, g, b) \ #define RGB(r, g, b) \
( \ ( \
(unsigned long) (((r) << 16) | ((g) << 8) | (b)) \ (unsigned long) (((r) << 16) | ((g) << 8) | (b)) \
) )
#define RGB16(r, g, b) \ #define RGB16(r, g, b) \
( \ ( \
(unsigned short) ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | (((b) & 0xF8) >> 3)) \ (unsigned short) ((((r) & 0xF8) << 8) | (((g) & 0xFC) << 3) | (((b) & 0xF8) >> 3)) \
) )
static inline unsigned int absDiff(unsigned int a, unsigned int b) static inline unsigned int absDiff(unsigned int a, unsigned int b)
......
drivers/staging/sm750fb/sm750_hw.h
View file @ 78376535
...@@ -2,8 +2,8 @@ ...@@ -2,8 +2,8 @@
#define LYNX_HW750_H__ #define LYNX_HW750_H__
#define DEFAULT_SM750_CHIP_CLOCK 290 #define DEFAULT_SM750_CHIP_CLOCK 290
#define DEFAULT_SM750LE_CHIP_CLOCK 333 #define DEFAULT_SM750LE_CHIP_CLOCK 333
#ifndef SM750LE_REVISION_ID #ifndef SM750LE_REVISION_ID
#define SM750LE_REVISION_ID (unsigned char)0xfe #define SM750LE_REVISION_ID (unsigned char)0xfe
#endif #endif
...@@ -24,9 +24,9 @@ enum sm750_dataflow{ ...@@ -24,9 +24,9 @@ enum sm750_dataflow{
sm750_simul_sec,/* secondary => all head */ sm750_simul_sec,/* secondary => all head */
sm750_dual_normal,/* primary => panel head and secondary => crt */ sm750_dual_normal,/* primary => panel head and secondary => crt */
sm750_dual_swap,/* primary => crt head and secondary => panel */ sm750_dual_swap,/* primary => crt head and secondary => panel */
}; };
...@@ -61,20 +61,20 @@ struct sm750_state{ ...@@ -61,20 +61,20 @@ struct sm750_state{
int yLCD; int yLCD;
}; };
/* sm750_share stands for a presentation of two frame buffer /* sm750_share stands for a presentation of two frame buffer
that use one sm750 adaptor, it is similar to the super class of lynx_share that use one sm750 adaptor, it is similar to the super class of lynx_share
in C++ in C++
*/ */
struct sm750_share{ struct sm750_share{
/* it's better to put lynx_share struct to the first place of sm750_share */ /* it's better to put lynx_share struct to the first place of sm750_share */
struct lynx_share share; struct lynx_share share;
struct sm750_state state; struct sm750_state state;
int hwCursor; int hwCursor;
/* 0: no hardware cursor /* 0: no hardware cursor
1: primary crtc hw cursor enabled, 1: primary crtc hw cursor enabled,
2: secondary crtc hw cursor enabled 2: secondary crtc hw cursor enabled
3: both ctrc hw cursor enabled 3: both ctrc hw cursor enabled
*/ */
}; };
...@@ -95,7 +95,7 @@ int hw_sm750le_setBLANK(struct lynxfb_output*, int); ...@@ -95,7 +95,7 @@ int hw_sm750le_setBLANK(struct lynxfb_output*, int);
void hw_sm750_crtc_clear(struct lynxfb_crtc*); void hw_sm750_crtc_clear(struct lynxfb_crtc*);
void hw_sm750_output_clear(struct lynxfb_output*); void hw_sm750_output_clear(struct lynxfb_output*);
int hw_sm750_pan_display(struct lynxfb_crtc *crtc, int hw_sm750_pan_display(struct lynxfb_crtc *crtc,
const struct fb_var_screeninfo *var, const struct fb_var_screeninfo *var,
const struct fb_info *info); const struct fb_info *info);
#endif #endif
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