[PATCH] ppc64: fix a bug in iSeries MMU hash management

From: Benjamin Herrenschmidt <benh@kernel.crashing.org>

iSeries HyperVisor is doing some evilery when inserting PTEs that I didn't
properly account for when rewriting that code, causing iSeries box to blow
up regulary.

arch/ppc64/kernel/pSeries_htab.c

@@ -103,7 +103,7 @@ long pSeries_hpte_insert(unsigned long hpte_group, unsigned long va,
 
 	__asm__ __volatile__ ("ptesync" : : : "memory");
 
-	return i;
+	return i | (secondary << 3);
 }
 
 static long pSeries_hpte_remove(unsigned long hpte_group)

arch/ppc64/kernel/pSeries_lpar.c

@@ -379,7 +379,10 @@ long pSeries_lpar_hpte_insert(unsigned long hpte_group,
 	if (lpar_rc != H_Success)
 		return -2;
 
-	return slot;
+	/* Because of iSeries, we have to pass down the secondary
+	 * bucket bit here as well
+	 */
+	return (slot & 7) | (secondary << 3);
 }
 
 static spinlock_t pSeries_lpar_tlbie_lock = SPIN_LOCK_UNLOCKED;

arch/ppc64/mm/hash_low.S

@@ -176,7 +176,6 @@ _GLOBAL(htab_call_hpte_insert1)
 	beq-	htab_pte_insert_failure
 
 	/* Now try secondary slot */
-	ori	r30,r30,_PAGE_SECONDARY
 	
 	/* page number in r5 */
 	rldicl	r5,r31,64-PTE_SHIFT,PTE_SHIFT
@@ -215,8 +214,8 @@ _GLOBAL(htab_call_hpte_remove)
 	b	htab_insert_pte	
 
 htab_pte_insert_ok:
-	/* Insert slot number in PTE */
-	rldimi	r30,r3,12,63-14
+	/* Insert slot number & secondary bit in PTE */
+	rldimi	r30,r3,12,63-15
 		
 	/* Write out the PTE with a normal write
 	 * (maybe add eieio may be good still ?)