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Commit 7a058a90 authored by Ben Skeggs's avatar Ben Skeggs
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drm/nouveau/gr/gp100-: fix attrib cb setup 

Signed-off-by: default avatarBen Skeggs <bskeggs@redhat.com>
parent 17f2d4df
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Inline Side-by-side
Showing with 32 additions and 17 deletions
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgf100.h
View file @ 7a058a90
...@@ -49,6 +49,7 @@ struct gf100_grctx_func { ...@@ -49,6 +49,7 @@ struct gf100_grctx_func {
u32 attrib_nr; u32 attrib_nr;
u32 alpha_nr_max; u32 alpha_nr_max;
u32 alpha_nr; u32 alpha_nr;
u32 gfxp_nr;
/* other patch buffer stuff */ /* other patch buffer stuff */
void (*patch_ltc)(struct gf100_grctx *); void (*patch_ltc)(struct gf100_grctx *);
/* floorsweeping */ /* floorsweeping */
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp100.c
View file @ 7a058a90
...@@ -48,14 +48,17 @@ gp100_grctx_generate_attrib(struct gf100_grctx *info) ...@@ -48,14 +48,17 @@ gp100_grctx_generate_attrib(struct gf100_grctx *info)
const struct gf100_grctx_func *grctx = gr->func->grctx; const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr; const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr; const u32 attrib = grctx->attrib_nr;
const u32 pertpc = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max);
const u32 size = roundup(gr->tpc_total * pertpc, 0x80);
const int s = 12; const int s = 12;
const int b = mmio_vram(info, size, (1 << s), false);
const int max_batches = 0xffff; const int max_batches = 0xffff;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
u32 ao = 0; u32 ao = 0;
u32 bo = ao + grctx->alpha_nr_max * gr->tpc_total; u32 bo = ao + size;
int gpc, ppc, n = 0; int gpc, ppc, b, n = 0;
for (gpc = 0; gpc < gr->gpc_nr; gpc++)
size += grctx->attrib_nr_max * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
size = ((size * 0x20) + 128) & ~127;
b = mmio_vram(info, size, (1 << s), false);
mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b);
...@@ -69,7 +72,7 @@ gp100_grctx_generate_attrib(struct gf100_grctx *info) ...@@ -69,7 +72,7 @@ gp100_grctx_generate_attrib(struct gf100_grctx *info)
for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 bs = attrib * gr->ppc_tpc_max;
const u32 u = 0x418ea0 + (n * 0x04); const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0); const u32 o = PPC_UNIT(gpc, ppc, 0);
if (!(gr->ppc_mask[gpc] & (1 << ppc))) if (!(gr->ppc_mask[gpc] & (1 << ppc)))
...@@ -77,7 +80,7 @@ gp100_grctx_generate_attrib(struct gf100_grctx *info) ...@@ -77,7 +80,7 @@ gp100_grctx_generate_attrib(struct gf100_grctx *info)
mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, o + 0xc0, bs);
mmio_wr32(info, o + 0xf4, bo); mmio_wr32(info, o + 0xf4, bo);
mmio_wr32(info, o + 0xf0, bs); mmio_wr32(info, o + 0xf0, bs);
bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; bo += grctx->attrib_nr_max * gr->ppc_tpc_max;
mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xe4, as);
mmio_wr32(info, o + 0xf8, ao); mmio_wr32(info, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp102.c
View file @ 7a058a90
...@@ -43,14 +43,18 @@ gp102_grctx_generate_attrib(struct gf100_grctx *info) ...@@ -43,14 +43,18 @@ gp102_grctx_generate_attrib(struct gf100_grctx *info)
const struct gf100_grctx_func *grctx = gr->func->grctx; const struct gf100_grctx_func *grctx = gr->func->grctx;
const u32 alpha = grctx->alpha_nr; const u32 alpha = grctx->alpha_nr;
const u32 attrib = grctx->attrib_nr; const u32 attrib = grctx->attrib_nr;
const u32 pertpc = 0x20 * (grctx->attrib_nr_max + grctx->alpha_nr_max); const u32 gfxp = grctx->gfxp_nr;
const u32 size = roundup(gr->tpc_total * pertpc, 0x80);
const int s = 12; const int s = 12;
const int b = mmio_vram(info, size, (1 << s), false);
const int max_batches = 0xffff; const int max_batches = 0xffff;
u32 size = grctx->alpha_nr_max * gr->tpc_total;
u32 ao = 0; u32 ao = 0;
u32 bo = ao + grctx->alpha_nr_max * gr->tpc_total; u32 bo = ao + size;
int gpc, ppc, n = 0; int gpc, ppc, b, n = 0;
for (gpc = 0; gpc < gr->gpc_nr; gpc++)
size += grctx->gfxp_nr * gr->ppc_nr[gpc] * gr->ppc_tpc_max;
size = ((size * 0x20) + 128) & ~127;
b = mmio_vram(info, size, (1 << s), false);
mmio_refn(info, 0x418810, 0x80000000, s, b); mmio_refn(info, 0x418810, 0x80000000, s, b);
mmio_refn(info, 0x419848, 0x10000000, s, b); mmio_refn(info, 0x419848, 0x10000000, s, b);
...@@ -64,17 +68,18 @@ gp102_grctx_generate_attrib(struct gf100_grctx *info) ...@@ -64,17 +68,18 @@ gp102_grctx_generate_attrib(struct gf100_grctx *info)
for (gpc = 0; gpc < gr->gpc_nr; gpc++) { for (gpc = 0; gpc < gr->gpc_nr; gpc++) {
for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) { for (ppc = 0; ppc < gr->ppc_nr[gpc]; ppc++, n++) {
const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc]; const u32 as = alpha * gr->ppc_tpc_nr[gpc][ppc];
const u32 bs = attrib * gr->ppc_tpc_nr[gpc][ppc]; const u32 bs = attrib * gr->ppc_tpc_max;
const u32 gs = gfxp * gr->ppc_tpc_max;
const u32 u = 0x418ea0 + (n * 0x04); const u32 u = 0x418ea0 + (n * 0x04);
const u32 o = PPC_UNIT(gpc, ppc, 0); const u32 o = PPC_UNIT(gpc, ppc, 0);
const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4)); const u32 p = GPC_UNIT(gpc, 0xc44 + (ppc * 4));
if (!(gr->ppc_mask[gpc] & (1 << ppc))) if (!(gr->ppc_mask[gpc] & (1 << ppc)))
continue; continue;
mmio_wr32(info, o + 0xc0, bs); mmio_wr32(info, o + 0xc0, gs);
mmio_wr32(info, p, bs); mmio_wr32(info, p, bs);
mmio_wr32(info, o + 0xf4, bo); mmio_wr32(info, o + 0xf4, bo);
mmio_wr32(info, o + 0xf0, bs); mmio_wr32(info, o + 0xf0, bs);
bo += grctx->attrib_nr_max * gr->ppc_tpc_nr[gpc][ppc]; bo += gs;
mmio_wr32(info, o + 0xe4, as); mmio_wr32(info, o + 0xe4, as);
mmio_wr32(info, o + 0xf8, ao); mmio_wr32(info, o + 0xf8, ao);
ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc]; ao += grctx->alpha_nr_max * gr->ppc_tpc_nr[gpc][ppc];
...@@ -97,10 +102,11 @@ gp102_grctx = { ...@@ -97,10 +102,11 @@ gp102_grctx = {
.pagepool = gp100_grctx_generate_pagepool, .pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000, .pagepool_size = 0x20000,
.attrib = gp102_grctx_generate_attrib, .attrib = gp102_grctx_generate_attrib,
.attrib_nr_max = 0x5d4, .attrib_nr_max = 0x4b0,
.attrib_nr = 0x320, .attrib_nr = 0x320,
.alpha_nr_max = 0xc00, .alpha_nr_max = 0xc00,
.alpha_nr = 0x800, .alpha_nr = 0x800,
.gfxp_nr = 0xba8,
.sm_id = gm107_grctx_generate_sm_id, .sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping, .rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table, .dist_skip_table = gm200_grctx_generate_dist_skip_table,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp104.c
View file @ 7a058a90
...@@ -32,10 +32,11 @@ gp104_grctx = { ...@@ -32,10 +32,11 @@ gp104_grctx = {
.pagepool = gp100_grctx_generate_pagepool, .pagepool = gp100_grctx_generate_pagepool,
.pagepool_size = 0x20000, .pagepool_size = 0x20000,
.attrib = gp102_grctx_generate_attrib, .attrib = gp102_grctx_generate_attrib,
.attrib_nr_max = 0x5d4, .attrib_nr_max = 0x4b0,
.attrib_nr = 0x320, .attrib_nr = 0x320,
.alpha_nr_max = 0xc00, .alpha_nr_max = 0xc00,
.alpha_nr = 0x800, .alpha_nr = 0x800,
.gfxp_nr = 0xba8,
.sm_id = gm107_grctx_generate_sm_id, .sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping, .rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table, .dist_skip_table = gm200_grctx_generate_dist_skip_table,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/ctxgp107.c
View file @ 7a058a90
...@@ -44,6 +44,7 @@ gp107_grctx = { ...@@ -44,6 +44,7 @@ gp107_grctx = {
.attrib_nr = 0x540, .attrib_nr = 0x540,
.alpha_nr_max = 0xc00, .alpha_nr_max = 0xc00,
.alpha_nr = 0x800, .alpha_nr = 0x800,
.gfxp_nr = 0xe94,
.sm_id = gm107_grctx_generate_sm_id, .sm_id = gm107_grctx_generate_sm_id,
.rop_mapping = gf117_grctx_generate_rop_mapping, .rop_mapping = gf117_grctx_generate_rop_mapping,
.dist_skip_table = gm200_grctx_generate_dist_skip_table, .dist_skip_table = gm200_grctx_generate_dist_skip_table,
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.c
View file @ 7a058a90
...@@ -1780,6 +1780,8 @@ gf100_gr_oneinit(struct nvkm_gr *base) ...@@ -1780,6 +1780,8 @@ gf100_gr_oneinit(struct nvkm_gr *base)
if (gr->ppc_tpc_min == 0 || if (gr->ppc_tpc_min == 0 ||
gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j]) gr->ppc_tpc_min > gr->ppc_tpc_nr[i][j])
gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j]; gr->ppc_tpc_min = gr->ppc_tpc_nr[i][j];
if (gr->ppc_tpc_max < gr->ppc_tpc_nr[i][j])
gr->ppc_tpc_max = gr->ppc_tpc_nr[i][j];
} }
} }
......
drivers/gpu/drm/nouveau/nvkm/engine/gr/gf100.h
View file @ 7a058a90
...@@ -106,6 +106,7 @@ struct gf100_gr { ...@@ -106,6 +106,7 @@ struct gf100_gr {
u8 ppc_tpc_mask[GPC_MAX][4]; u8 ppc_tpc_mask[GPC_MAX][4];
u8 ppc_tpc_nr[GPC_MAX][4]; u8 ppc_tpc_nr[GPC_MAX][4];
u8 ppc_tpc_min; u8 ppc_tpc_min;
u8 ppc_tpc_max;
u8 screen_tile_row_offset; u8 screen_tile_row_offset;
u8 tile[TPC_MAX]; u8 tile[TPC_MAX];
......
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