Commit 7a3b1c6e authored by Ard Biesheuvel's avatar Ard Biesheuvel Committed by Herbert Xu

crypto: arm64/aes-neonbs - replace tweak mask literal with composition

Replace the vector load from memory sequence with a simple instruction
sequence to compose the tweak vector directly.
Signed-off-by: default avatarArd Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: default avatarHerbert Xu <herbert@gondor.apana.org.au>
parent 38e73b3d
...@@ -730,11 +730,6 @@ ENDPROC(aesbs_cbc_decrypt) ...@@ -730,11 +730,6 @@ ENDPROC(aesbs_cbc_decrypt)
eor \out\().16b, \out\().16b, \tmp\().16b eor \out\().16b, \out\().16b, \tmp\().16b
.endm .endm
.align 4
.Lxts_mul_x:
CPU_LE( .quad 1, 0x87 )
CPU_BE( .quad 0x87, 1 )
/* /*
* aesbs_xts_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds, * aesbs_xts_encrypt(u8 out[], u8 const in[], u8 const rk[], int rounds,
* int blocks, u8 iv[]) * int blocks, u8 iv[])
...@@ -806,7 +801,9 @@ ENDPROC(__xts_crypt8) ...@@ -806,7 +801,9 @@ ENDPROC(__xts_crypt8)
mov x23, x4 mov x23, x4
mov x24, x5 mov x24, x5
0: ldr q30, .Lxts_mul_x 0: movi v30.2s, #0x1
movi v25.2s, #0x87
uzp1 v30.4s, v30.4s, v25.4s
ld1 {v25.16b}, [x24] ld1 {v25.16b}, [x24]
99: adr x7, \do8 99: adr x7, \do8
......
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