Commit 7bad74d5 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Use czclk_freq in vlv c0 residency calculations

Replace the use of mem_freq/4 with czclk_freq in the vlv c0 residency
calculations.

Also deal with VLV_COUNT_RANGE_HIGH which affects all RCx residency
counters. We have just enough bits to do this without intermediate
divisions.
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 2cc9fab1
...@@ -997,12 +997,16 @@ static bool vlv_c0_above(struct drm_i915_private *dev_priv, ...@@ -997,12 +997,16 @@ static bool vlv_c0_above(struct drm_i915_private *dev_priv,
int threshold) int threshold)
{ {
u64 time, c0; u64 time, c0;
unsigned int mul = 100;
if (old->cz_clock == 0) if (old->cz_clock == 0)
return false; return false;
if (I915_READ(VLV_COUNTER_CONTROL) & VLV_COUNT_RANGE_HIGH)
mul <<= 8;
time = now->cz_clock - old->cz_clock; time = now->cz_clock - old->cz_clock;
time *= threshold * dev_priv->mem_freq; time *= threshold * dev_priv->czclk_freq;
/* Workload can be split between render + media, e.g. SwapBuffers /* Workload can be split between render + media, e.g. SwapBuffers
* being blitted in X after being rendered in mesa. To account for * being blitted in X after being rendered in mesa. To account for
...@@ -1010,7 +1014,7 @@ static bool vlv_c0_above(struct drm_i915_private *dev_priv, ...@@ -1010,7 +1014,7 @@ static bool vlv_c0_above(struct drm_i915_private *dev_priv,
*/ */
c0 = now->render_c0 - old->render_c0; c0 = now->render_c0 - old->render_c0;
c0 += now->media_c0 - old->media_c0; c0 += now->media_c0 - old->media_c0;
c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000; c0 *= mul * VLV_CZ_CLOCK_TO_MILLI_SEC;
return c0 >= time; return c0 >= time;
} }
......
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