Commit 7cef07d5 authored by Shiraz Hashim's avatar Shiraz Hashim Committed by Viresh Kumar

ARM: SPEAr13xx: DT: Add spics gpio controller nodes

SPEAr platform provides a provision to control chipselects of ARM PL022 Prime
Cell spi controller through its system registers, which otherwise remains under
PL022 control which some protocols do not want.

This patch adds spics controller nodes in device tree for various SPEAr13xx
SoCs.

Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: default avatarShiraz Hashim <shiraz.hashim@st.com>
Reviewed-by: default avatarVipin Kumar <vipin.kumar@st.com>
Signed-off-by: default avatarViresh Kumar <viresh.kumar@linaro.org>
parent 53d74fd7
...@@ -17,6 +17,18 @@ / { ...@@ -17,6 +17,18 @@ / {
compatible = "st,spear1310"; compatible = "st,spear1310";
ahb { ahb {
spics: spics@e0700000{
compatible = "st,spear-spics-gpio";
reg = <0xe0700000 0x1000>;
st-spics,peripcfg-reg = <0x3b0>;
st-spics,sw-enable-bit = <12>;
st-spics,cs-value-bit = <11>;
st-spics,cs-enable-mask = <3>;
st-spics,cs-enable-shift = <8>;
gpio-controller;
#gpio-cells = <2>;
};
ahci@b1000000 { ahci@b1000000 {
compatible = "snps,spear-ahci"; compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>; reg = <0xb1000000 0x10000>;
......
...@@ -17,6 +17,20 @@ / { ...@@ -17,6 +17,20 @@ / {
compatible = "st,spear1340"; compatible = "st,spear1340";
ahb { ahb {
spics: spics@e0700000{
compatible = "st,spear-spics-gpio";
reg = <0xe0700000 0x1000>;
st-spics,peripcfg-reg = <0x42c>;
st-spics,sw-enable-bit = <21>;
st-spics,cs-value-bit = <20>;
st-spics,cs-enable-mask = <3>;
st-spics,cs-enable-shift = <18>;
gpio-controller;
#gpio-cells = <2>;
status = "disabled";
};
ahci@b1000000 { ahci@b1000000 {
compatible = "snps,spear-ahci"; compatible = "snps,spear-ahci";
reg = <0xb1000000 0x10000>; reg = <0xb1000000 0x10000>;
......
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