[PATCH] update the dvb front end chips

(Again all DVB is Martin Hunold)

drivers/media/dvb/frontends/Kconfig

 comment "Supported Frontend Modules"
 	depends on DVB
 
-config DVB_ALPS_BSRU6
-	tristate "Alps BSRU6 (QPSK)"
+config DVB_STV0299
+	tristate "STV0299 based DVB-S frontend (QPSK)"
 	depends on DVB_CORE
 	help
 	  A DVB-S tuner module. 
 
-	  Say Y when you want to support this frontend.
+	  Say Y when you want to support frontend based on this 
+	  demodulator.
+
+	  Some examples are the Alps BSRU6, the Philips SU1278 and
+	  the LG TDQB-S00x.
 
 	  If you don't know what tuner module is soldered on your 
 	  DVB adapter simply enable all supported frontends, the 
@@ -29,22 +33,34 @@ config DVB_ALPS_TDLB7
 	help
 	  A DVB-T tuner module. Say Y when you want to support this frontend.
 
-	  This tuner module needs some microcode located in a file called 
+	  This tuner module needs some microcode located in a file called
 	  "Sc_main.mc" in the windows driver. Please pass the module parameter
-	  mcfile="/PATH/FILENAME" when loading alps_tdlb7.
+	  mcfile="/PATH/FILENAME" when loading alps_tdlb7.o.
 
-	  If you don't know what tuner module is soldered on your 
-	  DVB adapter simply enable all supported frontends, the 
+	  If you don't know what tuner module is soldered on your
+	  DVB adapter simply enable all supported frontends, the
 	  right one will get autodetected.
 
+
 config DVB_ALPS_TDMB7
-	tristate "Alps BSRV2 (OFDM)"
+	tristate "Alps TDMB7 (OFDM)"
 	depends on DVB_CORE
 	help
-	  A DVB-S tuner module. Say Y when you want to support this frontend.
+	  A DVB-T tuner module. Say Y when you want to support this frontend.
 
-	  If you don't know what tuner module is soldered on your 
-	  DVB adapter simply enable all supported frontends, the 
+	  If you don't know what tuner module is soldered on your
+	  DVB adapter simply enable all supported frontends, the
+	  right one will get autodetected.
+
+config DVB_ATMEL_AT76C651
+	tristate "Atmel AT76C651 (QAM)"
+	depends on DVB_CORE
+	help
+	  The AT76C651 Demodulator is used in some DVB-C SetTopBoxes. Say Y
+	  when you see this demodulator chip near your tuner module.
+
+	  If you don't know what tuner module is soldered on your
+	  DVB adapter simply enable all supported frontends, the
 	  right one will get autodetected.
 
 config DVB_GRUNDIG_29504_491

drivers/media/dvb/frontends/Makefile

@@ -4,10 +4,11 @@
 
 EXTRA_CFLAGS = -Idrivers/media/dvb/dvb-core/
 
-obj-$(CONFIG_DVB_ALPS_BSRU6) += alps_bsru6.o
+obj-$(CONFIG_DVB_STV0299) += stv0299.o
 obj-$(CONFIG_DVB_ALPS_BSRV2) += alps_bsrv2.o
 obj-$(CONFIG_DVB_ALPS_TDLB7) += alps_tdlb7.o
 obj-$(CONFIG_DVB_ALPS_TDMB7) += alps_tdmb7.o
+obj-$(CONFIG_DVB_ATMEL_AT76C651) += at76c651.o
 obj-$(CONFIG_DVB_GRUNDIG_29504_491) += grundig_29504-491.o
 obj-$(CONFIG_DVB_GRUNDIG_29504_401) += grundig_29504-401.o
 obj-$(CONFIG_DVB_VES1820) += ves1820.o

drivers/media/dvb/frontends/alps_bsrv2.c

@@ -23,7 +23,6 @@
 #include <linux/module.h>
 #include <linux/init.h>
 
-#include "compat.h"
 #include "dvb_frontend.h"
 
 static int debug = 0;
@@ -32,20 +31,20 @@ static int debug = 0;
 
 static
 struct dvb_frontend_info bsrv2_info = {
-	.name			= "Alps BSRV2",
-	.type			= FE_QPSK,
-	.frequency_min		= 950000,
-	.frequency_max		= 2150000,
-	.frequency_stepsize	= 250,           /* kHz for QPSK frontends */
-	.frequency_tolerance	= 29500,
-	.symbol_rate_min	= 1000000,
-	.symbol_rate_max	= 45000000,
-	.notifier_delay		= 50,                /* 1/20 s */
-	.caps			= FE_CAN_INVERSION_AUTO |
-				  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
-				  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
-				  FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
-				  FE_CAN_QPSK
+	name: "Alps BSRV2",
+	type: FE_QPSK,
+	frequency_min: 950000,
+	frequency_max: 2150000,
+	frequency_stepsize: 250,           /* kHz for QPSK frontends */
+	frequency_tolerance: 29500,
+	symbol_rate_min: 1000000,
+	symbol_rate_max: 45000000,
+/*      symbol_rate_tolerance: ???,*/
+	notifier_delay: 50,                /* 1/20 s */
+	caps:   FE_CAN_INVERSION_AUTO |
+		FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+		FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+		FE_CAN_QPSK
 };
 
 
@@ -73,10 +72,10 @@ u8 init_1893_wtab[] =
 
 
 static
-int ves1893_writereg (struct dvb_i2c_bus *i2c, int reg, int data)
+int ves1893_writereg (struct dvb_i2c_bus *i2c, u8 reg, u8 data)
 {
         u8 buf [] = { 0x00, reg, data };
-	struct i2c_msg msg = { .addr = 0x08, .flags = 0, .buf = buf, .len = 3 };
+	struct i2c_msg msg = { addr: 0x08, flags: 0, buf: buf, len: 3 };
 	int err;
 
         if ((err = i2c->xfer (i2c, &msg, 1)) != 1) {
@@ -94,8 +93,8 @@ u8 ves1893_readreg (struct dvb_i2c_bus *i2c, u8 reg)
 	int ret;
 	u8 b0 [] = { 0x00, reg };
 	u8 b1 [] = { 0 };
-	struct i2c_msg msg [] = { { .addr = 0x08, .flags = 0, .buf = b0, .len = 2 },
-			   { .addr = 0x08, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+	struct i2c_msg msg [] = { { addr: 0x08, flags: 0, buf: b0, len: 2 },
+			   { addr: 0x08, flags: I2C_M_RD, buf: b1, len: 1 } };
 
 	ret = i2c->xfer (i2c, msg, 2);
 
@@ -110,7 +109,7 @@ static
 int sp5659_write (struct dvb_i2c_bus *i2c, u8 data [4])
 {
         int ret;
-        struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = 4 };
+        struct i2c_msg msg = { addr: 0x61, flags: 0, buf: data, len: 4 };
 
         ret = i2c->xfer (i2c, &msg, 1);
 
@@ -297,7 +296,7 @@ int ves1893_set_voltage (struct dvb_i2c_bus *i2c, fe_sec_voltage_t voltage)
 		return ves1893_writereg (i2c, 0x1f, 0x30);
 	default:
 		return -EINVAL;
-	};
+	}
 }
 
 
@@ -314,7 +313,7 @@ int bsrv2_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
         case FE_READ_STATUS:
 	{
 		fe_status_t *status = arg;
-		int sync = ves1893_readreg (i2c, 0x0e);
+		u8 sync = ves1893_readreg (i2c, 0x0e);
 
 		*status = 0;
 

drivers/media/dvb/frontends/alps_tdmb7.c

@@ -23,7 +23,6 @@
 #include <linux/init.h>
 #include <linux/module.h>
 
-#include "compat.h"
 #include "dvb_frontend.h"
 
 
@@ -33,15 +32,22 @@ static int debug = 0;
 
 static
 struct dvb_frontend_info tdmb7_info = {
-	.name			= "Alps TDMB7",
-	.type			= FE_OFDM,
-	.frequency_min		= 470000000,
-	.frequency_max		= 860000000,
-	.frequency_stepsize	= 166667,
-	.caps			= FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
-				  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
-				  FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
-				  FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64
+	name: "Alps TDMB7",
+	type: FE_OFDM,
+	frequency_min: 470000000,
+	frequency_max: 860000000,
+	frequency_stepsize: 166667,
+#if 0
+    	frequency_tolerance: ???,
+	symbol_rate_min: ???,
+	symbol_rate_max: ???,
+	symbol_rate_tolerance: 500,  /* ppm */
+	notifier_delay: 0,
+#endif
+	caps: FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+	      FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+	      FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 | 
+	      FE_CAN_CLEAN_SETUP | FE_CAN_RECOVER
 };
 
 
@@ -81,7 +87,7 @@ int cx22700_writereg (struct dvb_i2c_bus *i2c, u8 reg, u8 data)
 {
 	int ret;
 	u8 buf [] = { reg, data };
-	struct i2c_msg msg = { .addr = 0x43, .flags = 0, .buf = buf, .len = 2 };
+	struct i2c_msg msg = { addr: 0x43, flags: 0, buf: buf, len: 2 };
 
 	dprintk ("%s\n", __FUNCTION__);
 
@@ -101,8 +107,8 @@ u8 cx22700_readreg (struct dvb_i2c_bus *i2c, u8 reg)
 	int ret;
 	u8 b0 [] = { reg };
 	u8 b1 [] = { 0 };
-	struct i2c_msg msg [] = { { .addr = 0x43, .flags = 0, .buf = b0, .len = 1 },
-			   { .addr = 0x43, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+	struct i2c_msg msg [] = { { addr: 0x43, flags: 0, buf: b0, len: 1 },
+			   { addr: 0x43, flags: I2C_M_RD, buf: b1, len: 1 } };
         
 	dprintk ("%s\n", __FUNCTION__);
 
@@ -118,7 +124,7 @@ u8 cx22700_readreg (struct dvb_i2c_bus *i2c, u8 reg)
 static
 int pll_write (struct dvb_i2c_bus *i2c, u8 data [4])
 {
-	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = 4 };
+	struct i2c_msg msg = { addr: 0x61, flags: 0, buf: data, len: 4 };
 	int ret;
 
 	cx22700_writereg (i2c, 0x0a, 0x00);  /* open i2c bus switch */
@@ -350,6 +356,7 @@ int tdmb7_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
 
         case FE_READ_BER:
 		*((uint32_t*) arg) = cx22700_readreg (i2c, 0x0c) & 0x7f;
+		cx22700_writereg (i2c, 0x0c, 0x00);
 		break;
 
 	case FE_READ_SIGNAL_STRENGTH:
@@ -368,6 +375,7 @@ int tdmb7_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
 	}
 	case FE_READ_UNCORRECTED_BLOCKS: 
 		*((uint32_t*) arg) = cx22700_readreg (i2c, 0x0f);
+		cx22700_writereg (i2c, 0x0f, 0x00);
 		break;
 
         case FE_SET_FRONTEND:
@@ -412,7 +420,7 @@ int tdmb7_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
 static
 int tdmb7_attach (struct dvb_i2c_bus *i2c)
 {
-	struct i2c_msg msg = { .addr = 0x43, .flags = 0, .buf = NULL, .len = 0 };
+	struct i2c_msg msg = { addr: 0x43, flags: 0, buf: NULL, len: 0 };
 
 	dprintk ("%s\n", __FUNCTION__);
 

drivers/media/dvb/frontends/dvb_dummy_fe.c

+/* 
+ *  Driver for Dummy Frontend 
+ *
+ *  Written by Emard <emard@softhome.net>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *
+ *  GNU General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License
+ *  along with this program; if not, write to the Free Software
+ *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.=
+ */    
+
+#include <linux/module.h>
+#include <linux/init.h>
+
+#include "dvb_frontend.h"
+
+static int sct = 0;
+
+
+/* depending on module parameter sct deliver different infos
+ */
+
+static
+struct dvb_frontend_info dvb_s_dummyfe_info = {
+	name: "DVB-S dummy frontend",
+	type: FE_QPSK,
+	frequency_min: 950000,
+	frequency_max: 2150000,
+	frequency_stepsize: 250,           /* kHz for QPSK frontends */
+	frequency_tolerance: 29500,
+	symbol_rate_min: 1000000,
+	symbol_rate_max: 45000000,
+/*      symbol_rate_tolerance: ???,*/
+	notifier_delay: 50,                /* 1/20 s */
+	caps:   FE_CAN_INVERSION_AUTO | 
+	FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+	FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 | FE_CAN_FEC_AUTO |
+	FE_CAN_QPSK
+};
+
+static
+struct dvb_frontend_info dvb_c_dummyfe_info = {
+	.name = "DVB-C dummy frontend",
+	.type = FE_QAM,
+	.frequency_stepsize = 62500,
+	.frequency_min = 51000000,
+	.frequency_max = 858000000,
+	.symbol_rate_min = (57840000/2)/64,     /* SACLK/64 == (XIN/2)/64 */
+	.symbol_rate_max = (57840000/2)/4,      /* SACLK/4 */
+#if 0
+	frequency_tolerance: ???,
+	symbol_rate_tolerance: ???,  /* ppm */  /* == 8% (spec p. 5) */
+	notifier_delay: ?,
+#endif
+	.caps = FE_CAN_QAM_16 | FE_CAN_QAM_32 | FE_CAN_QAM_64 |
+		FE_CAN_QAM_128 | FE_CAN_QAM_256 | 
+		FE_CAN_FEC_AUTO | FE_CAN_INVERSION_AUTO |
+		FE_CAN_CLEAN_SETUP
+};
+
+static struct dvb_frontend_info dvb_t_dummyfe_info = {
+	.name = "DVB-T dummy frontend",
+	.type = FE_OFDM,
+	.frequency_min = 0,
+	.frequency_max = 863250000,
+	.frequency_stepsize = 62500,
+	/*.frequency_tolerance = */	/* FIXME: 12% of SR */
+	.symbol_rate_min = 0,		/* FIXME */
+	.symbol_rate_max = 9360000,	/* FIXME */
+	.symbol_rate_tolerance = 4000,
+	.notifier_delay = 0,
+	.caps = FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+			FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
+			FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
+			FE_CAN_QAM_16 | FE_CAN_QAM_64 | FE_CAN_QAM_AUTO |
+			FE_CAN_TRANSMISSION_MODE_AUTO |
+			FE_CAN_GUARD_INTERVAL_AUTO |
+			FE_CAN_HIERARCHY_AUTO,
+};
+
+struct dvb_frontend_info *frontend_info(void)
+{
+	switch(sct)
+	{
+	case 2:
+		return &dvb_t_dummyfe_info;
+	case 1:
+		return &dvb_c_dummyfe_info;
+	case 0:
+	default:
+	        return &dvb_s_dummyfe_info;
+	}
+}
+
+
+static
+int dvbdummyfe_ioctl (struct dvb_frontend *fe, unsigned int cmd, void *arg)
+{
+        switch (cmd) {
+        case FE_GET_INFO:
+		memcpy (arg, frontend_info(), 
+			sizeof(struct dvb_frontend_info));
+		break;
+
+        case FE_READ_STATUS:
+	{
+		fe_status_t *status = arg;
+		*status = FE_HAS_SIGNAL
+			| FE_HAS_CARRIER
+			| FE_HAS_VITERBI
+			| FE_HAS_SYNC
+			| FE_HAS_LOCK;
+		break;
+	}
+
+        case FE_READ_BER:
+	{
+		u32 *ber = (u32 *) arg;
+		*ber = 0;
+		break;
+	}
+
+        case FE_READ_SIGNAL_STRENGTH:
+	{
+		u8 signal = 0xff;
+		*((u16*) arg) = (signal << 8) | signal;
+		break;
+	}
+
+        case FE_READ_SNR:
+	{
+		u8 snr = 0xf0;
+		*(u16*) arg = (snr << 8) | snr;
+		break;
+	}
+
+	case FE_READ_UNCORRECTED_BLOCKS: 
+		*(u32*) arg = 0;
+		break;
+
+        case FE_SET_FRONTEND:
+                break;
+
+	case FE_GET_FRONTEND:
+		break;
+
+        case FE_SLEEP:
+		return 0;
+
+        case FE_INIT:
+		return 0;
+
+	case FE_RESET:
+		return 0;
+
+	case FE_SET_TONE:
+		return -EOPNOTSUPP;
+
+	case FE_SET_VOLTAGE:
+		return 0;
+
+	default:
+		return -EOPNOTSUPP;
+        }
+        return 0;
+} 
+
+
+static
+int dvbdummyfe_attach (struct dvb_i2c_bus *i2c)
+{
+	dvb_register_frontend (dvbdummyfe_ioctl, i2c, NULL, frontend_info());
+	return 0;
+}
+
+
+static
+void dvbdummyfe_detach (struct dvb_i2c_bus *i2c)
+{
+	dvb_unregister_frontend (dvbdummyfe_ioctl, i2c);
+}
+
+
+static
+int __init init_dvbdummyfe (void)
+{
+	return dvb_register_i2c_device (THIS_MODULE,
+					dvbdummyfe_attach, 
+					dvbdummyfe_detach);
+	return 0;
+}
+
+
+static 
+void __exit exit_dvbdummyfe (void)
+{
+	dvb_unregister_i2c_device (dvbdummyfe_attach);
+	return;
+}
+
+
+module_init(init_dvbdummyfe);
+module_exit(exit_dvbdummyfe);
+
+
+MODULE_DESCRIPTION("DVB DUMMY Frontend");
+MODULE_AUTHOR("Emard");
+MODULE_LICENSE("GPL");
+MODULE_PARM(sct, "i");

drivers/media/dvb/frontends/grundig_29504-401.c

@@ -25,7 +25,6 @@
 #include <linux/module.h>
 #include <linux/init.h>
 
-#include "compat.h"
 #include "dvb_frontend.h"
 
 static int debug = 0;
@@ -34,14 +33,18 @@ static int debug = 0;
 
 
 struct dvb_frontend_info grundig_29504_401_info = {
-	.name			= "Grundig 29504-401",
-	.type			= FE_OFDM,
-	.frequency_stepsize	= 166666,
-	.caps 			= FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
-				  FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 |
-				  FE_CAN_FEC_7_8 | FE_CAN_QPSK |
-				  FE_CAN_QAM_16 | FE_CAN_QAM_64 |
-				  FE_CAN_MUTE_TS
+	name: "Grundig 29504-401",
+	type: FE_OFDM,
+/*	frequency_min: ???,*/
+/*	frequency_max: ???,*/
+	frequency_stepsize: 166666,
+/*      frequency_tolerance: ???,*/
+/*      symbol_rate_tolerance: ???,*/
+	notifier_delay: 0,
+	caps: FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 | 
+	      FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
+	      FE_CAN_QPSK | FE_CAN_QAM_16 | FE_CAN_QAM_64 |
+	      FE_CAN_MUTE_TS /*| FE_CAN_CLEAN_SETUP*/
 };
 
 
@@ -50,7 +53,7 @@ int l64781_writereg (struct dvb_i2c_bus *i2c, u8 reg, u8 data)
 {
 	int ret;
 	u8 buf [] = { reg, data };
-	struct i2c_msg msg = { .addr = 0x55, .flags = 0, .buf = buf, .len = 2 };
+	struct i2c_msg msg = { addr: 0x55, flags: 0, buf: buf, len: 2 };
 
 	if ((ret = i2c->xfer (i2c, &msg, 1)) != 1)
 		dprintk ("%s: write_reg error (reg == %02x) = %02x!\n",
@@ -66,8 +69,8 @@ u8 l64781_readreg (struct dvb_i2c_bus *i2c, u8 reg)
 	int ret;
 	u8 b0 [] = { reg };
 	u8 b1 [] = { 0 };
-	struct i2c_msg msg [] = { { .addr = 0x55, .flags = 0, .buf = b0, .len = 1 },
-			   { .addr = 0x55, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+	struct i2c_msg msg [] = { { addr: 0x55, flags: 0, buf: b0, len: 1 },
+			   { addr: 0x55, flags: I2C_M_RD, buf: b1, len: 1 } };
 
 	ret = i2c->xfer (i2c, msg, 2);
 
@@ -82,7 +85,7 @@ static
 int tsa5060_write (struct dvb_i2c_bus *i2c, u8 data [4])
 {
 	int ret;
-	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = 4 };
+	struct i2c_msg msg = { addr: 0x61, flags: 0, buf: data, len: 4 };
 
 	if ((ret = i2c->xfer (i2c, &msg, 1)) != 1)
 		dprintk ("%s: write_reg error == %02x!\n", __FUNCTION__, ret);
@@ -97,24 +100,19 @@ int tsa5060_write (struct dvb_i2c_bus *i2c, u8 data [4])
  *   frequency offset is 36000000 Hz.
  */
 static
-int tsa5060_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq, u8 pwr)
+int tsa5060_set_tv_freq (struct dvb_i2c_bus *i2c, u32 freq)
 {
 	u32 div;
 	u8 buf [4];
 	u8 cfg;
 
-	if (freq < 700000000) {
-		div = (36000000 + freq) / 31250;
-		cfg = 0x86;
-	} else {
-		div = (36000000 + freq) / 166666;
-		cfg = 0x88;
-	}
+	div = (36000000 + freq) / 166666;
+	cfg = 0x88;
 
 	buf [0] = (div >> 8) & 0x7f;
 	buf [1] = div & 0xff;
 	buf [2] = ((div >> 10) & 0x60) | cfg;
-	buf [3] = pwr << 6;
+	buf [3] = 0xc0;
 
 	return tsa5060_write (i2c, buf);
 }
@@ -175,12 +173,13 @@ int apply_frontend_param (struct dvb_i2c_bus *i2c,
 	u8 val0x04;
 	u8 val0x05;
 	u8 val0x06;
+	int bw = p->bandwidth - BANDWIDTH_8_MHZ;
 
 	if (param->inversion != INVERSION_ON &&
 	    param->inversion != INVERSION_OFF)
 		return -EINVAL;
 
-	if (p->bandwidth < BANDWIDTH_8_MHZ || p->bandwidth > BANDWIDTH_6_MHZ)
+	if (bw < 0 || bw > 2)
 		return -EINVAL;
 	
 	if (p->code_rate_HP != FEC_1_2 && p->code_rate_HP != FEC_2_3 &&
@@ -230,6 +229,7 @@ int apply_frontend_param (struct dvb_i2c_bus *i2c,
 
 	val0x04 = (p->transmission_mode << 2) | p->guard_interval;
 	val0x05 = fec_tab[p->code_rate_HP];
+
 	if (p->hierarchy_information != HIERARCHY_NONE)
 		val0x05 |= (p->code_rate_LP - FEC_1_2) << 3;
 
@@ -269,7 +269,7 @@ static
 void reset_and_configure (struct dvb_i2c_bus *i2c)
 {
 	u8 buf [] = { 0x06 };
-	struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };
+	struct i2c_msg msg = { addr: 0x00, flags: 0, buf: buf, len: 1 };
 
 	i2c->xfer (i2c, &msg, 1);
 }
@@ -307,7 +307,7 @@ int init (struct dvb_i2c_bus *i2c)
         /*l64781_writereg (i2c, 0x19, 0x92);*/
 
 	/* Everything is two's complement, soft bit and CSI_OUT too */
-	l64781_writereg (i2c, 0x1e, 0x49);
+	l64781_writereg (i2c, 0x1e, 0x09);
 
 	return 0;
 }
@@ -390,9 +390,8 @@ int grundig_29504_401_ioctl (struct dvb_frontend *fe,
 	{
 		struct dvb_frontend_parameters *p = arg;
 
-		tsa5060_set_tv_freq (i2c, p->frequency, 3);
+		tsa5060_set_tv_freq (i2c, p->frequency);
 		apply_frontend_param (i2c, p);
-//		tsa5060_set_tv_freq (i2c, p->frequency, 0);
 	}
         case FE_GET_FRONTEND:
 		/*  we could correct the frequency here, but...
@@ -407,13 +406,6 @@ int grundig_29504_401_ioctl (struct dvb_frontend *fe,
 	case FE_INIT:
 		return init (i2c);
 
-        case FE_RESET:
-		//reset_afc (i2c);
-		apply_tps (i2c);
-		l64781_readreg (i2c, 0x00);  /*  clear interrupt registers... */
-		l64781_readreg (i2c, 0x01);  /*  dto. */
-		break;
-
         default:
 		dprintk ("%s: unknown command !!!\n", __FUNCTION__);
 		return -EINVAL;
@@ -428,8 +420,8 @@ int l64781_attach (struct dvb_i2c_bus *i2c)
 {
 	u8 b0 [] = { 0x1a };
 	u8 b1 [] = { 0x00 };
-	struct i2c_msg msg [] = { { .addr = 0x55, .flags = 0, .buf = b0, .len = 1 },
-			   { .addr = 0x55, .flags = I2C_M_RD, .buf = b1, .len = 1 } };
+	struct i2c_msg msg [] = { { addr: 0x55, flags: 0, buf: b0, len: 1 },
+			   { addr: 0x55, flags: I2C_M_RD, buf: b1, len: 1 } };
 
 	if (i2c->xfer (i2c, msg, 2) == 2)   /*  probably an EEPROM... */
 		return -ENODEV;

drivers/media/dvb/frontends/grundig_29504-491.c

@@ -27,7 +27,6 @@
 #include <linux/init.h>
 #include <linux/module.h>
 
-#include "compat.h"
 #include "dvb_frontend.h"
 
 static int debug = 0;
@@ -36,20 +35,22 @@ static int debug = 0;
 
 static
 struct dvb_frontend_info grundig_29504_491_info = {
-	.name			= "Grundig 29504-491, (TDA8083 based)",
-	.type			= FE_QPSK,
-	.frequency_min		= 950000,     /* FIXME: guessed! */
-	.frequency_max		= 1400000,    /* FIXME: guessed! */
-	.frequency_stepsize	= 125,   /* kHz for QPSK frontends */
-	.symbol_rate_min	= 1000000,   /* FIXME: guessed! */
-	.symbol_rate_max	= 45000000,  /* FIXME: guessed! */
-	.caps			= FE_CAN_INVERSION_AUTO |
-				  FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
-				  FE_CAN_FEC_3_4 | FE_CAN_FEC_4_5 |
-				  FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
-				  FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 |
-				  FE_CAN_FEC_AUTO | FE_CAN_QPSK |
-				  FE_CAN_MUTE_TS
+	name: "Grundig 29504-491, (TDA8083 based)",
+	type: FE_QPSK,
+	frequency_min: 950000,     /* FIXME: guessed! */
+	frequency_max: 1400000,    /* FIXME: guessed! */
+	frequency_stepsize: 125,   /* kHz for QPSK frontends */
+/*      frequency_tolerance: ???,*/
+	symbol_rate_min: 1000000,   /* FIXME: guessed! */
+	symbol_rate_max: 45000000,  /* FIXME: guessed! */
+/*      symbol_rate_tolerance: ???,*/
+	notifier_delay: 0,
+	caps:	FE_CAN_INVERSION_AUTO |
+		FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 | FE_CAN_FEC_3_4 |
+		FE_CAN_FEC_4_5 | FE_CAN_FEC_5_6 | FE_CAN_FEC_6_7 |
+		FE_CAN_FEC_7_8 | FE_CAN_FEC_8_9 | FE_CAN_FEC_AUTO |
+		FE_CAN_QPSK |
+		FE_CAN_MUTE_TS | FE_CAN_CLEAN_SETUP
 };
 
 
@@ -71,7 +72,7 @@ int tda8083_writereg (struct dvb_i2c_bus *i2c, u8 reg, u8 data)
 {
 	int ret;
 	u8 buf [] = { reg, data };
-	struct i2c_msg msg = { .addr = 0x68, .flags = 0, .buf = buf, .len = 2 };
+	struct i2c_msg msg = { addr: 0x68, flags: 0, buf: buf, len: 2 };
 
         ret = i2c->xfer (i2c, &msg, 1);
 
@@ -87,8 +88,8 @@ static
 int tda8083_readregs (struct dvb_i2c_bus *i2c, u8 reg1, u8 *b, u8 len)
 {
 	int ret;
-	struct i2c_msg msg [] = { { .addr = 0x68, .flags = 0, .buf = &reg1, .len = 1 },
-			   { .addr = 0x68, .flags = I2C_M_RD, .buf = b, .len = len } };
+	struct i2c_msg msg [] = { { addr: 0x68, flags: 0, buf: &reg1, len: 1 },
+			   { addr: 0x68, flags: I2C_M_RD, buf: b, len: len } };
 
 	ret = i2c->xfer (i2c, msg, 2);
 
@@ -115,7 +116,7 @@ static
 int tsa5522_write (struct dvb_i2c_bus *i2c, u8 data [4])
 {
 	int ret;
-	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = 4 };
+	struct i2c_msg msg = { addr: 0x61, flags: 0, buf: data, len: 4 };
 
 	ret = i2c->xfer (i2c, &msg, 1);
 

drivers/media/dvb/frontends/nxt6000.h

+/**********************************************************************/
+ * DRV6000reg.H
+ * Public Include File for DRV6000 users
+ *
+ * Copyright (C) 2001 NxtWave Communications, Inc.
+ *
+ * $Log: nxt6000.h,v $
+ * Revision 1.2  2003/01/27 12:32:42  fschirmer
+ * Lots of bugfixes and new features
+ *
+ * Revision 1.1  2003/01/21 18:43:09  fschirmer
+ * Nxt6000 based frontend driver
+ *
+ * Revision 1.1  2003/01/03 02:25:45  obi
+ * alps tdme7 driver
+ *
+ * 
+ *    Rev 1.10   Jun 12 2002 11:28:02   dkoeger
+ * Updated for SA in GUi work
+ * 
+ *    Rev 1.9   Apr 01 2002 10:38:46   dkoeger
+ * Updated for 1.0.31 GUI
+ * 
+ *    Rev 1.8   Mar 11 2002 10:04:56   dkoeger
+ * Updated for 1.0.31 GUI version
+ * 
+ *    Rev 1.5   Dec 07 2001 14:40:40   dkoeger
+ * Updated for 1.0.28 GUI
+ * 
+ *    Rev 1.4   Nov 13 2001 11:09:00   dkoeger
+ * No change.
+ * 
+ *    Rev 1.3   Aug 23 2001 14:21:02   dkoeger
+ * Updated for driver version 2.1.9
+ * 
+ *    Rev 1.2   Jul 09 2001 09:20:04   dkoeger
+ * Updated for 1.0.18
+ * 
+ *    Rev 1.1   Jun 13 2001 16:14:24   dkoeger
+ * Updated to reflect NXT6000 GUI BETA 1.0.11 6/13/2001
+ **********************************************************************/
+
+
+/*  Nxt6000 Register Addresses and Bit Masks */
+
+/* Maximum Register Number */
+#define MAXNXT6000REG          (0x9A)
+
+/* 0x1B A_VIT_BER_0  aka 0x3A */
+#define A_VIT_BER_0            (0x1B)
+
+/* 0x1D A_VIT_BER_TIMER_0 aka 0x38 */
+#define A_VIT_BER_TIMER_0      (0x1D)
+
+/* 0x21 RS_COR_STAT */
+#define RS_COR_STAT            (0x21)
+#define RSCORESTATUS           (0x03)
+
+/* 0x22 RS_COR_INTEN */
+#define RS_COR_INTEN           (0x22)
+
+/* 0x23 RS_COR_INSTAT */
+#define RS_COR_INSTAT          (0x23)
+#define INSTAT_ERROR           (0x04)
+#define LOCK_LOSS_BITS         (0x03)
+
+/* 0x24 RS_COR_SYNC_PARAM */
+#define RS_COR_SYNC_PARAM      (0x24)
+#define SYNC_PARAM             (0x03)
+
+/* 0x25 BER_CTRL */
+#define BER_CTRL               (0x25)
+#define BER_ENABLE             (0x02)
+#define BER_RESET              (0x01)
+
+/* 0x26 BER_PAY */
+#define BER_PAY                (0x26)
+
+/* 0x27 BER_PKT_L */
+#define BER_PKT_L              (0x27)
+#define BER_PKTOVERFLOW        (0x80)
+
+/* 0x30 VIT_COR_CTL */
+#define VIT_COR_CTL            (0x30)
+#define BER_CONTROL            (0x02)
+#define VIT_COR_MASK           (0x82)
+#define VIT_COR_RESYNC         (0x80)
+
+
+/* 0x32 VIT_SYNC_STATUS */
+#define VIT_SYNC_STATUS        (0x32)
+#define VITINSYNC              (0x80)
+
+/* 0x33 VIT_COR_INTEN */
+#define VIT_COR_INTEN          (0x33)
+#define GLOBAL_ENABLE          (0x80)
+
+/* 0x34 VIT_COR_INTSTAT */
+#define VIT_COR_INTSTAT        (0x34)
+#define BER_DONE               (0x08)
+#define BER_OVERFLOW           (0x10)
+
+/* 0x38 OFDM_BERTimer */     /* Use the alias registers */
+#define A_VIT_BER_TIMER_0      (0x1D)
+
+/* 0x3A VIT_BER_TIMER_0 */   /* Use the alias registers */
+#define A_VIT_BER_0            (0x1B)
+
+/* 0x40 OFDM_COR_CTL */
+#define OFDM_COR_CTL           (0x40)
+#define COREACT                (0x20)
+#define HOLDSM                 (0x10)
+#define WAIT_AGC               (0x02)
+#define WAIT_SYR               (0x03)
+
+/* 0x41 OFDM_COR_STAT */
+#define OFDM_COR_STAT          (0x41)
+#define COR_STATUS             (0x0F)
+#define MONITOR_TPS            (0x06)
+#define TPSLOCKED              (0x40)
+#define AGCLOCKED              (0x10)
+
+/* 0x42 OFDM_COR_INTEN */
+#define OFDM_COR_INTEN         (0x42)
+#define TPSRCVBAD              (0x04)
+#define TPSRCVCHANGED         (0x02)
+#define TPSRCVUPDATE           (0x01)
+
+/* 0x43 OFDM_COR_INSTAT */
+#define OFDM_COR_INSTAT        (0x43)
+
+/* 0x44 OFDM_COR_MODEGUARD */
+#define OFDM_COR_MODEGUARD     (0x44)
+#define FORCEMODE              (0x08)
+#define FORCEMODE8K			   (0x04)
+
+/* 0x45 OFDM_AGC_CTL */
+#define OFDM_AGC_CTL           (0x45)
+#define INITIAL_AGC_BW		   (0x08)
+#define AGCNEG                 (0x02)
+#define AGCLAST				   (0x10)
+
+/* 0x48 OFDM_AGC_TARGET */
+#define OFDM_AGC_TARGET		   (0x48)
+#define OFDM_AGC_TARGET_DEFAULT (0x28)
+#define OFDM_AGC_TARGET_IMPULSE (0x38)
+
+/* 0x49 OFDM_AGC_GAIN_1 */
+#define OFDM_AGC_GAIN_1        (0x49)
+
+/* 0x4B OFDM_ITB_CTL */
+#define OFDM_ITB_CTL           (0x4B)
+#define ITBINV                 (0x01)
+
+/* 0x4C OFDM_ITB_FREQ_1 */
+#define OFDM_ITB_FREQ_1        (0x4C)
+
+/* 0x4D OFDM_ITB_FREQ_2 */
+#define OFDM_ITB_FREQ_2        (0x4D)
+
+/* 0x4E  OFDM_CAS_CTL */       
+#define OFDM_CAS_CTL           (0x4E)
+#define ACSDIS                 (0x40)
+#define CCSEN                  (0x80)
+
+/* 0x4F CAS_FREQ */
+#define CAS_FREQ               (0x4F)
+
+/* 0x51 OFDM_SYR_CTL */
+#define OFDM_SYR_CTL           (0x51)
+#define SIXTH_ENABLE           (0x80)
+#define SYR_TRACKING_DISABLE   (0x01)
+
+/* 0x52 OFDM_SYR_STAT */
+#define OFDM_SYR_STAT		   (0x52)
+#define GI14_2K_SYR_LOCK	   (0x13)
+#define GI14_8K_SYR_LOCK	   (0x17)
+#define GI14_SYR_LOCK		   (0x10)
+
+/* 0x55 OFDM_SYR_OFFSET_1 */
+#define OFDM_SYR_OFFSET_1      (0x55)
+
+/* 0x56 OFDM_SYR_OFFSET_2 */
+#define OFDM_SYR_OFFSET_2      (0x56)
+
+/* 0x58 OFDM_SCR_CTL */
+#define OFDM_SCR_CTL           (0x58)
+#define SYR_ADJ_DECAY_MASK     (0x70)
+#define SYR_ADJ_DECAY          (0x30)
+ 
+/* 0x59 OFDM_PPM_CTL_1 */
+#define OFDM_PPM_CTL_1         (0x59)
+#define PPMMAX_MASK            (0x30)
+#define PPM256				   (0x30)
+
+/* 0x5B OFDM_TRL_NOMINALRATE_1 */
+#define OFDM_TRL_NOMINALRATE_1 (0x5B)
+
+/* 0x5C OFDM_TRL_NOMINALRATE_2 */
+#define OFDM_TRL_NOMINALRATE_2 (0x5C)
+
+/* 0x5D OFDM_TRL_TIME_1 */
+#define OFDM_TRL_TIME_1        (0x5D)
+
+/* 0x60 OFDM_CRL_FREQ_1 */
+#define OFDM_CRL_FREQ_1        (0x60)
+
+/* 0x63 OFDM_CHC_CTL_1 */
+#define OFDM_CHC_CTL_1         (0x63)
+#define MANMEAN1               (0xF0);
+#define CHCFIR                 (0x01)
+
+/* 0x64 OFDM_CHC_SNR */
+#define OFDM_CHC_SNR           (0x64)
+
+/* 0x65 OFDM_BDI_CTL */
+#define OFDM_BDI_CTL           (0x65)
+#define LP_SELECT              (0x02)
+
+/* 0x67 OFDM_TPS_RCVD_1 */
+#define OFDM_TPS_RCVD_1        (0x67)
+#define TPSFRAME               (0x03)
+
+/* 0x68 OFDM_TPS_RCVD_2 */
+#define OFDM_TPS_RCVD_2        (0x68)
+
+/* 0x69 OFDM_TPS_RCVD_3 */
+#define OFDM_TPS_RCVD_3        (0x69)
+
+/* 0x6A OFDM_TPS_RCVD_4 */
+#define OFDM_TPS_RCVD_4        (0x6A)
+
+/* 0x6B OFDM_TPS_RESERVED_1 */
+#define OFDM_TPS_RESERVED_1    (0x6B)
+
+/* 0x6C OFDM_TPS_RESERVED_2 */
+#define OFDM_TPS_RESERVED_2    (0x6C)
+
+/* 0x73 OFDM_MSC_REV */
+#define OFDM_MSC_REV           (0x73)
+
+/* 0x76 OFDM_SNR_CARRIER_2 */
+#define OFDM_SNR_CARRIER_2     (0x76)
+#define MEAN_MASK              (0x80)
+#define MEANBIT                (0x80)
+
+/* 0x80 ANALOG_CONTROL_0 */
+#define ANALOG_CONTROL_0       (0x80)
+#define POWER_DOWN_ADC         (0x40)
+
+/* 0x81 ENABLE_TUNER_IIC */
+#define ENABLE_TUNER_IIC       (0x81)
+#define ENABLE_TUNER_BIT       (0x01)
+
+/* 0x82 EN_DMD_RACQ */
+#define EN_DMD_RACQ            (0x82)
+#define EN_DMD_RACQ_REG_VAL    (0x81) 
+#define EN_DMD_RACQ_REG_VAL_14 (0x01)
+
+/* 0x84 SNR_COMMAND */
+#define SNR_COMMAND            (0x84)
+#define SNRStat                (0x80)
+
+/* 0x85 SNRCARRIERNUMBER_LSB */
+#define SNRCARRIERNUMBER_LSB   (0x85)
+
+/* 0x87 SNRMINTHRESHOLD_LSB */
+#define SNRMINTHRESHOLD_LSB    (0x87)
+
+/* 0x89 SNR_PER_CARRIER_LSB */
+#define SNR_PER_CARRIER_LSB    (0x89)
+
+/* 0x8B SNRBELOWTHRESHOLD_LSB */
+#define SNRBELOWTHRESHOLD_LSB  (0x8B)
+
+/* 0x91 RF_AGC_VAL_1 */
+#define RF_AGC_VAL_1           (0x91)
+
+/* 0x92 RF_AGC_STATUS */
+#define RF_AGC_STATUS          (0x92)
+
+/* 0x98 DIAG_CONFIG */
+#define DIAG_CONFIG            (0x98)
+#define DIAG_MASK              (0x70)
+#define TB_SET                 (0x10)
+#define TRAN_SELECT            (0x07)
+#define SERIAL_SELECT          (0x01)
+
+/* 0x99 SUB_DIAG_MODE_SEL */
+#define SUB_DIAG_MODE_SEL      (0x99)
+#define CLKINVERSION           (0x01)
+
+/* 0x9A TS_FORMAT */
+#define TS_FORMAT              (0x9A)
+#define ERROR_SENSE            (0x08)
+#define VALID_SENSE            (0x04)
+#define SYNC_SENSE             (0x02)
+#define GATED_CLOCK            (0x01)
+
+#define NXT6000ASICDEVICE      (0x0b)
+