Commit 7db097dc authored by Serge Semin's avatar Serge Semin Committed by Mark Brown

spi: dw: Add Tx/Rx DMA properties

Since commit 22d48ad7 ("spi: dw: Add Elkhart Lake PSE DMA support")
the spi-dw-mid.c module supports a platform DMA engine handling the DW APB
SSI controller requests. Lets alter the DW SPI bindings file to accept the
Rx and Tx DMA line specifiers.
Signed-off-by: default avatarSerge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: Georgy Vlasov <Georgy.Vlasov@baikalelectronics.ru>
Cc: Ramil Zaripov <Ramil.Zaripov@baikalelectronics.ru>
Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru>
Cc: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: Paul Burton <paulburton@kernel.org>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Allison Randal <allison@lohutok.net>
Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Cc: Gareth Williams <gareth.williams.jx@renesas.com>
Cc: linux-mips@vger.kernel.org
Link: https://lore.kernel.org/r/20200515104758.6934-2-Sergey.Semin@baikalelectronics.ruSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent b271cf33
...@@ -23,6 +23,8 @@ Optional properties: ...@@ -23,6 +23,8 @@ Optional properties:
- num-cs : The number of chipselects. If omitted, this will default to 4. - num-cs : The number of chipselects. If omitted, this will default to 4.
- reg-io-width : The I/O register width (in bytes) implemented by this - reg-io-width : The I/O register width (in bytes) implemented by this
device. Supported values are 2 or 4 (the default). device. Supported values are 2 or 4 (the default).
- dmas : Phandle + identifiers of Tx and Rx DMA channels.
- dma-names : Contains the names of the DMA channels. Must be "tx" and "rx".
Child nodes as per the generic SPI binding. Child nodes as per the generic SPI binding.
......
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