Skip to content

L
linux
Commit 7f12a563 authored by Ryder Lee's avatar Ryder Lee Committed by Mark Brown
Browse files
Options

ASoC: mediatek: update MT2701 AFE documentation to adapt mfd device 

As the new MFD parent is in place, modify MT2701 AFE documentation to
adapt it. Also add three core clocks in example.
Signed-off-by: default avatarRyder Lee <ryder.lee@mediatek.com>
Signed-off-by: default avatarMark Brown <broonie@kernel.org>
parent dfa3cbb8
Hide whitespace changes
Inline Side-by-side
Showing with 93 additions and 78 deletions
Documentation/devicetree/bindings/sound/mt2701-afe-pcm.txt
View file @ 7f12a563
...@@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701 ...@@ -2,15 +2,17 @@ Mediatek AFE PCM controller for mt2701
Required properties: Required properties:
- compatible = "mediatek,mt2701-audio"; - compatible = "mediatek,mt2701-audio";
- reg: register location and size
- interrupts: should contain AFE and ASYS interrupts - interrupts: should contain AFE and ASYS interrupts
- interrupt-names: should be "afe" and "asys" - interrupt-names: should be "afe" and "asys"
- power-domains: should define the power domain - power-domains: should define the power domain
- clocks: Must contain an entry for each entry in clock-names - clocks: Must contain an entry for each entry in clock-names
See ../clocks/clock-bindings.txt for details See ../clocks/clock-bindings.txt for details
- clock-names: should have these clock names: - clock-names: should have these clock names:
"infra_sys_audio_clk",
"top_audio_mux1_sel", "top_audio_mux1_sel",
"top_audio_mux2_sel", "top_audio_mux2_sel",
"top_audio_a1sys_hp",
"top_audio_a2sys_hp",
"i2s0_src_sel", "i2s0_src_sel",
"i2s1_src_sel", "i2s1_src_sel",
"i2s2_src_sel", "i2s2_src_sel",
...@@ -45,85 +47,98 @@ Required properties: ...@@ -45,85 +47,98 @@ Required properties:
- assigned-clocks-parents: parent of input clocks of assigned clocks. - assigned-clocks-parents: parent of input clocks of assigned clocks.
- assigned-clock-rates: list of clock frequencies of assigned clocks. - assigned-clock-rates: list of clock frequencies of assigned clocks.
Must be a subnode of MediaTek audsys device tree node.
See ../arm/mediatek/mediatek,audsys.txt for details about the parent node.
Example: Example:
afe: mt2701-afe-pcm@11220000 { audsys: audio-subsystem@11220000 {
compatible = "mediatek,mt2701-audio"; compatible = "mediatek,mt2701-audsys", "syscon", "simple-mfd";
reg = <0 0x11220000 0 0x2000>, ...
<0 0x112A0000 0 0x20000>;
interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>, afe: audio-controller {
<GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>; compatible = "mediatek,mt2701-audio";
interrupt-names = "afe", "asys"; interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_LOW>,
power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>; <GIC_SPI 132 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, interrupt-names = "afe", "asys";
<&topckgen CLK_TOP_AUD_MUX2_SEL>, power-domains = <&scpsys MT2701_POWER_DOMAIN_IFR_MSC>;
<&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K2_SRC_SEL>, clocks = <&infracfg CLK_INFRA_AUDIO>,
<&topckgen CLK_TOP_AUD_K3_SRC_SEL>, <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_SEL>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_K1_SRC_DIV>, <&topckgen CLK_TOP_AUD_48K_TIMING>,
<&topckgen CLK_TOP_AUD_K2_SRC_DIV>, <&topckgen CLK_TOP_AUD_44K_TIMING>,
<&topckgen CLK_TOP_AUD_K3_SRC_DIV>, <&topckgen CLK_TOP_AUD_K1_SRC_SEL>,
<&topckgen CLK_TOP_AUD_K4_SRC_DIV>, <&topckgen CLK_TOP_AUD_K2_SRC_SEL>,
<&topckgen CLK_TOP_AUD_I2S1_MCLK>, <&topckgen CLK_TOP_AUD_K3_SRC_SEL>,
<&topckgen CLK_TOP_AUD_I2S2_MCLK>, <&topckgen CLK_TOP_AUD_K4_SRC_SEL>,
<&topckgen CLK_TOP_AUD_I2S3_MCLK>, <&topckgen CLK_TOP_AUD_K1_SRC_DIV>,
<&topckgen CLK_TOP_AUD_I2S4_MCLK>, <&topckgen CLK_TOP_AUD_K2_SRC_DIV>,
<&audiosys CLK_AUD_I2SO1>, <&topckgen CLK_TOP_AUD_K3_SRC_DIV>,
<&audiosys CLK_AUD_I2SO2>, <&topckgen CLK_TOP_AUD_K4_SRC_DIV>,
<&audiosys CLK_AUD_I2SO3>, <&topckgen CLK_TOP_AUD_I2S1_MCLK>,
<&audiosys CLK_AUD_I2SO4>, <&topckgen CLK_TOP_AUD_I2S2_MCLK>,
<&audiosys CLK_AUD_I2SIN1>, <&topckgen CLK_TOP_AUD_I2S3_MCLK>,
<&audiosys CLK_AUD_I2SIN2>, <&topckgen CLK_TOP_AUD_I2S4_MCLK>,
<&audiosys CLK_AUD_I2SIN3>, <&audsys CLK_AUD_I2SO1>,
<&audiosys CLK_AUD_I2SIN4>, <&audsys CLK_AUD_I2SO2>,
<&audiosys CLK_AUD_ASRCO1>, <&audsys CLK_AUD_I2SO3>,
<&audiosys CLK_AUD_ASRCO2>, <&audsys CLK_AUD_I2SO4>,
<&audiosys CLK_AUD_ASRCO3>, <&audsys CLK_AUD_I2SIN1>,
<&audiosys CLK_AUD_ASRCO4>, <&audsys CLK_AUD_I2SIN2>,
<&audiosys CLK_AUD_AFE>, <&audsys CLK_AUD_I2SIN3>,
<&audiosys CLK_AUD_AFE_CONN>, <&audsys CLK_AUD_I2SIN4>,
<&audiosys CLK_AUD_A1SYS>, <&audsys CLK_AUD_ASRCO1>,
<&audiosys CLK_AUD_A2SYS>, <&audsys CLK_AUD_ASRCO2>,
<&audiosys CLK_AUD_AFE_MRGIF>; <&audsys CLK_AUD_ASRCO3>,
<&audsys CLK_AUD_ASRCO4>,
<&audsys CLK_AUD_AFE>,
<&audsys CLK_AUD_AFE_CONN>,
<&audsys CLK_AUD_A1SYS>,
<&audsys CLK_AUD_A2SYS>,
<&audsys CLK_AUD_AFE_MRGIF>;
clock-names = "top_audio_mux1_sel", clock-names = "infra_sys_audio_clk",
"top_audio_mux2_sel", "top_audio_mux1_sel",
"i2s0_src_sel", "top_audio_mux2_sel",
"i2s1_src_sel", "top_audio_a1sys_hp",
"i2s2_src_sel", "top_audio_a2sys_hp",
"i2s3_src_sel", "i2s0_src_sel",
"i2s0_src_div", "i2s1_src_sel",
"i2s1_src_div", "i2s2_src_sel",
"i2s2_src_div", "i2s3_src_sel",
"i2s3_src_div", "i2s0_src_div",
"i2s0_mclk_en", "i2s1_src_div",
"i2s1_mclk_en", "i2s2_src_div",
"i2s2_mclk_en", "i2s3_src_div",
"i2s3_mclk_en", "i2s0_mclk_en",
"i2so0_hop_ck", "i2s1_mclk_en",
"i2so1_hop_ck", "i2s2_mclk_en",
"i2so2_hop_ck", "i2s3_mclk_en",
"i2so3_hop_ck", "i2so0_hop_ck",
"i2si0_hop_ck", "i2so1_hop_ck",
"i2si1_hop_ck", "i2so2_hop_ck",
"i2si2_hop_ck", "i2so3_hop_ck",
"i2si3_hop_ck", "i2si0_hop_ck",
"asrc0_out_ck", "i2si1_hop_ck",
"asrc1_out_ck", "i2si2_hop_ck",
"asrc2_out_ck", "i2si3_hop_ck",
"asrc3_out_ck", "asrc0_out_ck",
"audio_afe_pd", "asrc1_out_ck",
"audio_afe_conn_pd", "asrc2_out_ck",
"audio_a1sys_pd", "asrc3_out_ck",
"audio_a2sys_pd", "audio_afe_pd",
"audio_mrgif_pd"; "audio_afe_conn_pd",
"audio_a1sys_pd",
"audio_a2sys_pd",
"audio_mrgif_pd";
assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>, assigned-clocks = <&topckgen CLK_TOP_AUD_MUX1_SEL>,
<&topckgen CLK_TOP_AUD_MUX2_SEL>, <&topckgen CLK_TOP_AUD_MUX2_SEL>,
<&topckgen CLK_TOP_AUD_MUX1_DIV>, <&topckgen CLK_TOP_AUD_MUX1_DIV>,
<&topckgen CLK_TOP_AUD_MUX2_DIV>; <&topckgen CLK_TOP_AUD_MUX2_DIV>;
assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>, assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL_98M>,
<&topckgen CLK_TOP_AUD2PLL_90M>; <&topckgen CLK_TOP_AUD2PLL_90M>;
assigned-clock-rates = <0>, <0>, <49152000>, <45158400>; assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
};
}; };
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7