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nexedi
linux
Commits
7fb8ec8e
Commit
7fb8ec8e
authored
Jan 05, 2010
by
Ben Skeggs
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Plain Diff
drm/nv50: restore correct cache1 get/put address on fifoctx load
Signed-off-by:
Ben Skeggs
<
bskeggs@redhat.com
>
parent
846975a9
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1 changed file
with
2 additions
and
4 deletions
+2
-4
drivers/gpu/drm/nouveau/nv50_fifo.c
drivers/gpu/drm/nouveau/nv50_fifo.c
+2
-4
No files found.
drivers/gpu/drm/nouveau/nv50_fifo.c
View file @
7fb8ec8e
...
...
@@ -384,8 +384,8 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
nv_wr32
(
dev
,
NV40_PFIFO_CACHE1_DATA
(
ptr
),
nv_ro32
(
dev
,
cache
,
(
ptr
*
2
)
+
1
));
}
nv_wr32
(
dev
,
0x3210
,
cnt
<<
2
);
nv_wr32
(
dev
,
0x3270
,
0
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUT
,
cnt
<<
2
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_GET
,
0
);
/* guessing that all the 0x34xx regs aren't on NV50 */
if
(
!
IS_G80
)
{
...
...
@@ -398,8 +398,6 @@ nv50_fifo_load_context(struct nouveau_channel *chan)
dev_priv
->
engine
.
instmem
.
finish_access
(
dev
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_GET
,
0
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUT
,
0
);
nv_wr32
(
dev
,
NV03_PFIFO_CACHE1_PUSH1
,
chan
->
id
|
(
1
<<
16
));
return
0
;
}
...
...
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