drm/amd/display: link training fallback actions

Signed-off-by: Ding Wang <ding.wang@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/display/dc/dc.h

@@ -777,7 +777,7 @@ void dc_link_dp_set_drive_settings(
 	const struct dc_link *link,
 	struct link_training_settings *lt_settings);
 
-bool dc_link_dp_perform_link_training(
+enum link_training_result dc_link_dp_perform_link_training(
 	struct dc_link *link,
 	const struct dc_link_settings *link_setting,
 	bool skip_video_pattern);

drivers/gpu/drm/amd/display/dc/inc/dc_link_dp.h

@@ -37,6 +37,14 @@ bool dp_hbr_verify_link_cap(
 	struct core_link *link,
 	struct dc_link_settings *known_limit_link_setting);
 
+bool decide_fallback_link_setting(struct dc_link_settings link_setting_init,
+		struct dc_link_settings *link_setting_current,
+		enum link_training_result training_result);
+
+struct dc_link_settings get_common_supported_link_settings (
+		struct dc_link_settings link_setting_a,
+		struct dc_link_settings link_setting_b);
+
 bool dp_validate_mode_timing(
 	struct core_link *link,
 	const struct dc_crtc_timing *timing);

drivers/gpu/drm/amd/display/include/link_service_types.h

@@ -56,6 +56,15 @@ enum {
 	LINK_RATE_REF_FREQ_IN_KHZ = 27000 /*27MHz*/
 };
 
+enum link_training_result {
+	LINK_TRAINING_SUCCESS,
+	LINK_TRAINING_CR_FAIL,
+	/* CR DONE bit is cleared during EQ step */
+	LINK_TRAINING_EQ_FAIL_CR,
+	/* other failure during EQ step */
+	LINK_TRAINING_EQ_FAIL_EQ,
+};
+
 struct link_training_settings {
 	struct dc_link_settings link_settings;
 	struct dc_lane_settings lane_settings[LANE_COUNT_DP_MAX];