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Commit 83ebb3e3 authored by Benjamin Herrenschmidt's avatar Benjamin Herrenschmidt
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Merge remote branch 'kumar/merge' into merge

parents b2a8b4b8 a94d7b35
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Showing with 38 additions and 27 deletions
arch/powerpc/boot/dts/p1020rdb.dts
View file @ 83ebb3e3
/* /*
* P1020 RDB Device Tree Source * P1020 RDB Device Tree Source
* *
* Copyright 2009 Freescale Semiconductor Inc. * Copyright 2009-2011 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -553,7 +553,7 @@ pci0: pcie@ffe09000 { ...@@ -553,7 +553,7 @@ pci0: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>; reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>; bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <16 2>; interrupts = <16 2>;
...@@ -580,8 +580,8 @@ pci1: pcie@ffe0a000 { ...@@ -580,8 +580,8 @@ pci1: pcie@ffe0a000 {
#address-cells = <3>; #address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>; reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>; bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <16 2>; interrupts = <16 2>;
...@@ -590,8 +590,8 @@ pcie@0 { ...@@ -590,8 +590,8 @@ pcie@0 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000 ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0xc0000000 0x2000000 0x0 0x80000000
0x0 0x20000000 0x0 0x20000000
0x1000000 0x0 0x0 0x1000000 0x0 0x0
......
arch/powerpc/boot/dts/p2020rdb.dts
View file @ 83ebb3e3
/* /*
* P2020 RDB Device Tree Source * P2020 RDB Device Tree Source
* *
* Copyright 2009 Freescale Semiconductor Inc. * Copyright 2009-2011 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -537,7 +537,7 @@ pci0: pcie@ffe09000 { ...@@ -537,7 +537,7 @@ pci0: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>; reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>; bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <25 2>; interrupts = <25 2>;
...@@ -564,8 +564,8 @@ pci1: pcie@ffe0a000 { ...@@ -564,8 +564,8 @@ pci1: pcie@ffe0a000 {
#address-cells = <3>; #address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>; reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>; bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <26 2>; interrupts = <26 2>;
...@@ -574,8 +574,8 @@ pcie@0 { ...@@ -574,8 +574,8 @@ pcie@0 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000 ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0xc0000000 0x2000000 0x0 0x80000000
0x0 0x20000000 0x0 0x20000000
0x1000000 0x0 0x0 0x1000000 0x0 0x0
......
arch/powerpc/boot/dts/p2020rdb_camp_core0.dts
View file @ 83ebb3e3
...@@ -6,7 +6,7 @@ ...@@ -6,7 +6,7 @@
* This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb, * This dts file allows core0 to have memory, l2, i2c, spi, gpio, dma1, usb,
* eth1, eth2, sdhc, crypto, global-util, pci0. * eth1, eth2, sdhc, crypto, global-util, pci0.
* *
* Copyright 2009 Freescale Semiconductor Inc. * Copyright 2009-2011 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -342,7 +342,7 @@ pci0: pcie@ffe09000 { ...@@ -342,7 +342,7 @@ pci0: pcie@ffe09000 {
reg = <0 0xffe09000 0 0x1000>; reg = <0 0xffe09000 0 0x1000>;
bus-range = <0 255>; bus-range = <0 255>;
ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000 ranges = <0x2000000 0x0 0xa0000000 0 0xa0000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc30000 0x0 0x10000>; 0x1000000 0x0 0x00000000 0 0xffc10000 0x0 0x10000>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <25 2>; interrupts = <25 2>;
......
arch/powerpc/boot/dts/p2020rdb_camp_core1.dts
View file @ 83ebb3e3
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* *
* Please note to add "-b 1" for core1's dts compiling. * Please note to add "-b 1" for core1's dts compiling.
* *
* Copyright 2009 Freescale Semiconductor Inc. * Copyright 2009-2011 Freescale Semiconductor Inc.
* *
* This program is free software; you can redistribute it and/or modify it * This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the * under the terms of the GNU General Public License as published by the
...@@ -162,8 +162,8 @@ pci1: pcie@ffe0a000 { ...@@ -162,8 +162,8 @@ pci1: pcie@ffe0a000 {
#address-cells = <3>; #address-cells = <3>;
reg = <0 0xffe0a000 0 0x1000>; reg = <0 0xffe0a000 0 0x1000>;
bus-range = <0 255>; bus-range = <0 255>;
ranges = <0x2000000 0x0 0xc0000000 0 0xc0000000 0x0 0x20000000 ranges = <0x2000000 0x0 0x80000000 0 0x80000000 0x0 0x20000000
0x1000000 0x0 0x00000000 0 0xffc20000 0x0 0x10000>; 0x1000000 0x0 0x00000000 0 0xffc00000 0x0 0x10000>;
clock-frequency = <33333333>; clock-frequency = <33333333>;
interrupt-parent = <&mpic>; interrupt-parent = <&mpic>;
interrupts = <26 2>; interrupts = <26 2>;
...@@ -172,8 +172,8 @@ pcie@0 { ...@@ -172,8 +172,8 @@ pcie@0 {
#size-cells = <2>; #size-cells = <2>;
#address-cells = <3>; #address-cells = <3>;
device_type = "pci"; device_type = "pci";
ranges = <0x2000000 0x0 0xc0000000 ranges = <0x2000000 0x0 0x80000000
0x2000000 0x0 0xc0000000 0x2000000 0x0 0x80000000
0x0 0x20000000 0x0 0x20000000
0x1000000 0x0 0x0 0x1000000 0x0 0x0
......
drivers/edac/mpc85xx_edac.c
View file @ 83ebb3e3
...@@ -1147,13 +1147,14 @@ static struct platform_driver mpc85xx_mc_err_driver = { ...@@ -1147,13 +1147,14 @@ static struct platform_driver mpc85xx_mc_err_driver = {
static void __init mpc85xx_mc_clear_rfxe(void *data) static void __init mpc85xx_mc_clear_rfxe(void *data)
{ {
orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1); orig_hid1[smp_processor_id()] = mfspr(SPRN_HID1);
mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~0x20000)); mtspr(SPRN_HID1, (orig_hid1[smp_processor_id()] & ~HID1_RFXE));
} }
#endif #endif
static int __init mpc85xx_mc_init(void) static int __init mpc85xx_mc_init(void)
{ {
int res = 0; int res = 0;
u32 pvr = 0;
printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, " printk(KERN_INFO "Freescale(R) MPC85xx EDAC driver, "
"(C) 2006 Montavista Software\n"); "(C) 2006 Montavista Software\n");
...@@ -1183,12 +1184,17 @@ static int __init mpc85xx_mc_init(void) ...@@ -1183,12 +1184,17 @@ static int __init mpc85xx_mc_init(void)
#endif #endif
#ifdef CONFIG_FSL_SOC_BOOKE #ifdef CONFIG_FSL_SOC_BOOKE
/* pvr = mfspr(SPRN_PVR);
* need to clear HID1[RFXE] to disable machine check int
* so we can catch it if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
*/ (PVR_VER(pvr) == PVR_VER_E500V2)) {
if (edac_op_state == EDAC_OPSTATE_INT) /*
on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0); * need to clear HID1[RFXE] to disable machine check int
* so we can catch it
*/
if (edac_op_state == EDAC_OPSTATE_INT)
on_each_cpu(mpc85xx_mc_clear_rfxe, NULL, 0);
}
#endif #endif
return 0; return 0;
...@@ -1206,7 +1212,12 @@ static void __exit mpc85xx_mc_restore_hid1(void *data) ...@@ -1206,7 +1212,12 @@ static void __exit mpc85xx_mc_restore_hid1(void *data)
static void __exit mpc85xx_mc_exit(void) static void __exit mpc85xx_mc_exit(void)
{ {
#ifdef CONFIG_FSL_SOC_BOOKE #ifdef CONFIG_FSL_SOC_BOOKE
on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0); u32 pvr = mfspr(SPRN_PVR);
if ((PVR_VER(pvr) == PVR_VER_E500V1) ||
(PVR_VER(pvr) == PVR_VER_E500V2)) {
on_each_cpu(mpc85xx_mc_restore_hid1, NULL, 0);
}
#endif #endif
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
platform_driver_unregister(&mpc85xx_pci_err_driver); platform_driver_unregister(&mpc85xx_pci_err_driver);
......
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