Commit 844ef042 authored by Maxime Ripard's avatar Maxime Ripard Committed by Mauro Carvalho Chehab

media: dt-bindings: media: Add Cadence MIPI-CSI2 TX Device Tree bindings

The Cadence MIPI-CSI2 TX controller is a CSI2 bridge that supports up to 4
video streams and can output on up to 4 CSI-2 lanes, depending on the
hardware implementation.

It can operate with an external D-PHY, an internal one or no D-PHY at all
in some configurations.
Acked-by: default avatarBenoit Parrot <bparrot@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Reviewed-by: default avatarNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Signed-off-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: default avatarSakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab+samsung@kernel.org>
parent 1fc3b37f
Cadence MIPI-CSI2 TX controller
===============================
The Cadence MIPI-CSI2 TX controller is a CSI-2 bridge supporting up to
4 CSI lanes in output, and up to 4 different pixel streams in input.
Required properties:
- compatible: must be set to "cdns,csi2tx"
- reg: base address and size of the memory mapped region
- clocks: phandles to the clocks driving the controller
- clock-names: must contain:
* esc_clk: escape mode clock
* p_clk: register bank clock
* pixel_if[0-3]_clk: pixel stream output clock, one for each stream
implemented in hardware, between 0 and 3
Optional properties
- phys: phandle to the D-PHY. If it is set, phy-names need to be set
- phy-names: must contain "dphy"
Required subnodes:
- ports: A ports node with one port child node per device input and output
port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The
port nodes are numbered as follows.
Port Description
-----------------------------
0 CSI-2 output
1 Stream 0 input
2 Stream 1 input
3 Stream 2 input
4 Stream 3 input
The stream input port nodes are optional if they are not
connected to anything at the hardware level or implemented
in the design. Since there is only one endpoint per port,
the endpoints are not numbered.
Example:
csi2tx: csi-bridge@0d0e1000 {
compatible = "cdns,csi2tx";
reg = <0x0d0e1000 0x1000>;
clocks = <&byteclock>, <&byteclock>,
<&coreclock>, <&coreclock>,
<&coreclock>, <&coreclock>;
clock-names = "p_clk", "esc_clk",
"pixel_if0_clk", "pixel_if1_clk",
"pixel_if2_clk", "pixel_if3_clk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
csi2tx_out: endpoint {
remote-endpoint = <&remote_in>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
csi2tx_in_stream0: endpoint {
remote-endpoint = <&stream0_out>;
};
};
port@2 {
reg = <2>;
csi2tx_in_stream1: endpoint {
remote-endpoint = <&stream1_out>;
};
};
port@3 {
reg = <3>;
csi2tx_in_stream2: endpoint {
remote-endpoint = <&stream2_out>;
};
};
port@4 {
reg = <4>;
csi2tx_in_stream3: endpoint {
remote-endpoint = <&stream3_out>;
};
};
};
};
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