Commit 864edb75 authored by Aneesh Kumar K.V's avatar Aneesh Kumar K.V Committed by Michael Ellerman

powerpc/mm/book3s64/radix: Flush the full mm even when need_flush_all is set

With the previous patch, we should now not be using need_flush_all for
powerpc. But then make sure we force a PID tlbie flush with RIC=2 if
we ever find need_flush_all set. Also don't reset it after a mmu
gather flush.
Signed-off-by: default avatarAneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: default avatarMichael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20191024075801.22434-3-aneesh.kumar@linux.ibm.com
parent 52162ec7
...@@ -995,7 +995,7 @@ void radix__tlb_flush(struct mmu_gather *tlb) ...@@ -995,7 +995,7 @@ void radix__tlb_flush(struct mmu_gather *tlb)
* that flushes the process table entry cache upon process teardown. * that flushes the process table entry cache upon process teardown.
* See the comment for radix in arch_exit_mmap(). * See the comment for radix in arch_exit_mmap().
*/ */
if (tlb->fullmm) { if (tlb->fullmm || tlb->need_flush_all) {
__flush_all_mm(mm, true); __flush_all_mm(mm, true);
} else if ( (psize = radix_get_mmu_psize(page_size)) == -1) { } else if ( (psize = radix_get_mmu_psize(page_size)) == -1) {
if (!tlb->freed_tables) if (!tlb->freed_tables)
...@@ -1008,7 +1008,6 @@ void radix__tlb_flush(struct mmu_gather *tlb) ...@@ -1008,7 +1008,6 @@ void radix__tlb_flush(struct mmu_gather *tlb)
else else
radix__flush_tlb_pwc_range_psize(mm, start, end, psize); radix__flush_tlb_pwc_range_psize(mm, start, end, psize);
} }
tlb->need_flush_all = 0;
} }
static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm, static __always_inline void __radix__flush_tlb_range_psize(struct mm_struct *mm,
......
...@@ -428,7 +428,7 @@ static inline void tlb_change_page_size(struct mmu_gather *tlb, ...@@ -428,7 +428,7 @@ static inline void tlb_change_page_size(struct mmu_gather *tlb,
{ {
#ifdef CONFIG_HAVE_MMU_GATHER_PAGE_SIZE #ifdef CONFIG_HAVE_MMU_GATHER_PAGE_SIZE
if (tlb->page_size && tlb->page_size != page_size) { if (tlb->page_size && tlb->page_size != page_size) {
if (!tlb->fullmm) if (!tlb->fullmm && !tlb->need_flush_all)
tlb_flush_mmu(tlb); tlb_flush_mmu(tlb);
} }
......
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