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nexedi
linux
Commits
867a5a12
Commit
867a5a12
authored
Mar 13, 2018
by
Neil Armstrong
Browse files
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Merge branch 'topic/pll-fixes' into next/drivers
parents
f5edaefe
6c00e7b7
Changes
6
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Showing
6 changed files
with
140 additions
and
201 deletions
+140
-201
drivers/clk/meson/axg.c
drivers/clk/meson/axg.c
+26
-95
drivers/clk/meson/clk-mpll.c
drivers/clk/meson/clk-mpll.c
+7
-0
drivers/clk/meson/clk-pll.c
drivers/clk/meson/clk-pll.c
+32
-9
drivers/clk/meson/clkc.h
drivers/clk/meson/clkc.h
+3
-0
drivers/clk/meson/gxbb.c
drivers/clk/meson/gxbb.c
+70
-96
drivers/clk/meson/gxbb.h
drivers/clk/meson/gxbb.h
+2
-1
No files found.
drivers/clk/meson/axg.c
View file @
867a5a12
...
@@ -21,98 +21,6 @@
...
@@ -21,98 +21,6 @@
static
DEFINE_SPINLOCK
(
meson_clk_lock
);
static
DEFINE_SPINLOCK
(
meson_clk_lock
);
static
const
struct
pll_rate_table
sys_pll_rate_table
[]
=
{
PLL_RATE
(
24000000
,
56
,
1
,
2
),
PLL_RATE
(
48000000
,
64
,
1
,
2
),
PLL_RATE
(
72000000
,
72
,
1
,
2
),
PLL_RATE
(
96000000
,
64
,
1
,
2
),
PLL_RATE
(
120000000
,
80
,
1
,
2
),
PLL_RATE
(
144000000
,
96
,
1
,
2
),
PLL_RATE
(
168000000
,
56
,
1
,
1
),
PLL_RATE
(
192000000
,
64
,
1
,
1
),
PLL_RATE
(
216000000
,
72
,
1
,
1
),
PLL_RATE
(
240000000
,
80
,
1
,
1
),
PLL_RATE
(
264000000
,
88
,
1
,
1
),
PLL_RATE
(
288000000
,
96
,
1
,
1
),
PLL_RATE
(
312000000
,
52
,
1
,
2
),
PLL_RATE
(
336000000
,
56
,
1
,
2
),
PLL_RATE
(
360000000
,
60
,
1
,
2
),
PLL_RATE
(
384000000
,
64
,
1
,
2
),
PLL_RATE
(
408000000
,
68
,
1
,
2
),
PLL_RATE
(
432000000
,
72
,
1
,
2
),
PLL_RATE
(
456000000
,
76
,
1
,
2
),
PLL_RATE
(
480000000
,
80
,
1
,
2
),
PLL_RATE
(
504000000
,
84
,
1
,
2
),
PLL_RATE
(
528000000
,
88
,
1
,
2
),
PLL_RATE
(
552000000
,
92
,
1
,
2
),
PLL_RATE
(
576000000
,
96
,
1
,
2
),
PLL_RATE
(
600000000
,
50
,
1
,
1
),
PLL_RATE
(
624000000
,
52
,
1
,
1
),
PLL_RATE
(
648000000
,
54
,
1
,
1
),
PLL_RATE
(
672000000
,
56
,
1
,
1
),
PLL_RATE
(
696000000
,
58
,
1
,
1
),
PLL_RATE
(
720000000
,
60
,
1
,
1
),
PLL_RATE
(
744000000
,
62
,
1
,
1
),
PLL_RATE
(
768000000
,
64
,
1
,
1
),
PLL_RATE
(
792000000
,
66
,
1
,
1
),
PLL_RATE
(
816000000
,
68
,
1
,
1
),
PLL_RATE
(
840000000
,
70
,
1
,
1
),
PLL_RATE
(
864000000
,
72
,
1
,
1
),
PLL_RATE
(
888000000
,
74
,
1
,
1
),
PLL_RATE
(
912000000
,
76
,
1
,
1
),
PLL_RATE
(
936000000
,
78
,
1
,
1
),
PLL_RATE
(
960000000
,
80
,
1
,
1
),
PLL_RATE
(
984000000
,
82
,
1
,
1
),
PLL_RATE
(
1008000000
,
84
,
1
,
1
),
PLL_RATE
(
1032000000
,
86
,
1
,
1
),
PLL_RATE
(
1056000000
,
88
,
1
,
1
),
PLL_RATE
(
1080000000
,
90
,
1
,
1
),
PLL_RATE
(
1104000000
,
92
,
1
,
1
),
PLL_RATE
(
1128000000
,
94
,
1
,
1
),
PLL_RATE
(
1152000000
,
96
,
1
,
1
),
PLL_RATE
(
1176000000
,
98
,
1
,
1
),
PLL_RATE
(
1200000000
,
50
,
1
,
0
),
PLL_RATE
(
1224000000
,
51
,
1
,
0
),
PLL_RATE
(
1248000000
,
52
,
1
,
0
),
PLL_RATE
(
1272000000
,
53
,
1
,
0
),
PLL_RATE
(
1296000000
,
54
,
1
,
0
),
PLL_RATE
(
1320000000
,
55
,
1
,
0
),
PLL_RATE
(
1344000000
,
56
,
1
,
0
),
PLL_RATE
(
1368000000
,
57
,
1
,
0
),
PLL_RATE
(
1392000000
,
58
,
1
,
0
),
PLL_RATE
(
1416000000
,
59
,
1
,
0
),
PLL_RATE
(
1440000000
,
60
,
1
,
0
),
PLL_RATE
(
1464000000
,
61
,
1
,
0
),
PLL_RATE
(
1488000000
,
62
,
1
,
0
),
PLL_RATE
(
1512000000
,
63
,
1
,
0
),
PLL_RATE
(
1536000000
,
64
,
1
,
0
),
PLL_RATE
(
1560000000
,
65
,
1
,
0
),
PLL_RATE
(
1584000000
,
66
,
1
,
0
),
PLL_RATE
(
1608000000
,
67
,
1
,
0
),
PLL_RATE
(
1632000000
,
68
,
1
,
0
),
PLL_RATE
(
1656000000
,
68
,
1
,
0
),
PLL_RATE
(
1680000000
,
68
,
1
,
0
),
PLL_RATE
(
1704000000
,
68
,
1
,
0
),
PLL_RATE
(
1728000000
,
69
,
1
,
0
),
PLL_RATE
(
1752000000
,
69
,
1
,
0
),
PLL_RATE
(
1776000000
,
69
,
1
,
0
),
PLL_RATE
(
1800000000
,
69
,
1
,
0
),
PLL_RATE
(
1824000000
,
70
,
1
,
0
),
PLL_RATE
(
1848000000
,
70
,
1
,
0
),
PLL_RATE
(
1872000000
,
70
,
1
,
0
),
PLL_RATE
(
1896000000
,
70
,
1
,
0
),
PLL_RATE
(
1920000000
,
71
,
1
,
0
),
PLL_RATE
(
1944000000
,
71
,
1
,
0
),
PLL_RATE
(
1968000000
,
71
,
1
,
0
),
PLL_RATE
(
1992000000
,
71
,
1
,
0
),
PLL_RATE
(
2016000000
,
72
,
1
,
0
),
PLL_RATE
(
2040000000
,
72
,
1
,
0
),
PLL_RATE
(
2064000000
,
72
,
1
,
0
),
PLL_RATE
(
2088000000
,
72
,
1
,
0
),
PLL_RATE
(
2112000000
,
73
,
1
,
0
),
{
/* sentinel */
},
};
static
struct
meson_clk_pll
axg_fixed_pll
=
{
static
struct
meson_clk_pll
axg_fixed_pll
=
{
.
m
=
{
.
m
=
{
.
reg_off
=
HHI_MPLL_CNTL
,
.
reg_off
=
HHI_MPLL_CNTL
,
...
@@ -129,6 +37,11 @@ static struct meson_clk_pll axg_fixed_pll = {
...
@@ -129,6 +37,11 @@ static struct meson_clk_pll axg_fixed_pll = {
.
shift
=
16
,
.
shift
=
16
,
.
width
=
2
,
.
width
=
2
,
},
},
.
frac
=
{
.
reg_off
=
HHI_MPLL_CNTL2
,
.
shift
=
0
,
.
width
=
12
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"fixed_pll"
,
.
name
=
"fixed_pll"
,
...
@@ -151,11 +64,9 @@ static struct meson_clk_pll axg_sys_pll = {
...
@@ -151,11 +64,9 @@ static struct meson_clk_pll axg_sys_pll = {
},
},
.
od
=
{
.
od
=
{
.
reg_off
=
HHI_SYS_PLL_CNTL
,
.
reg_off
=
HHI_SYS_PLL_CNTL
,
.
shift
=
1
0
,
.
shift
=
1
6
,
.
width
=
2
,
.
width
=
2
,
},
},
.
rate_table
=
sys_pll_rate_table
,
.
rate_count
=
ARRAY_SIZE
(
sys_pll_rate_table
),
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"sys_pll"
,
.
name
=
"sys_pll"
,
...
@@ -381,6 +292,11 @@ static struct meson_clk_mpll axg_mpll0 = {
...
@@ -381,6 +292,11 @@ static struct meson_clk_mpll axg_mpll0 = {
.
shift
=
25
,
.
shift
=
25
,
.
width
=
1
,
.
width
=
1
,
},
},
.
misc
=
{
.
reg_off
=
HHI_PLL_TOP_MISC
,
.
shift
=
0
,
.
width
=
1
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"mpll0"
,
.
name
=
"mpll0"
,
...
@@ -411,6 +327,11 @@ static struct meson_clk_mpll axg_mpll1 = {
...
@@ -411,6 +327,11 @@ static struct meson_clk_mpll axg_mpll1 = {
.
shift
=
14
,
.
shift
=
14
,
.
width
=
1
,
.
width
=
1
,
},
},
.
misc
=
{
.
reg_off
=
HHI_PLL_TOP_MISC
,
.
shift
=
1
,
.
width
=
1
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"mpll1"
,
.
name
=
"mpll1"
,
...
@@ -441,6 +362,11 @@ static struct meson_clk_mpll axg_mpll2 = {
...
@@ -441,6 +362,11 @@ static struct meson_clk_mpll axg_mpll2 = {
.
shift
=
14
,
.
shift
=
14
,
.
width
=
1
,
.
width
=
1
,
},
},
.
misc
=
{
.
reg_off
=
HHI_PLL_TOP_MISC
,
.
shift
=
2
,
.
width
=
1
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"mpll2"
,
.
name
=
"mpll2"
,
...
@@ -471,6 +397,11 @@ static struct meson_clk_mpll axg_mpll3 = {
...
@@ -471,6 +397,11 @@ static struct meson_clk_mpll axg_mpll3 = {
.
shift
=
0
,
.
shift
=
0
,
.
width
=
1
,
.
width
=
1
,
},
},
.
misc
=
{
.
reg_off
=
HHI_PLL_TOP_MISC
,
.
shift
=
3
,
.
width
=
1
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"mpll3"
,
.
name
=
"mpll3"
,
...
...
drivers/clk/meson/clk-mpll.c
View file @
867a5a12
...
@@ -173,6 +173,13 @@ static int mpll_set_rate(struct clk_hw *hw,
...
@@ -173,6 +173,13 @@ static int mpll_set_rate(struct clk_hw *hw,
reg
=
PARM_SET
(
p
->
width
,
p
->
shift
,
reg
,
n2
);
reg
=
PARM_SET
(
p
->
width
,
p
->
shift
,
reg
,
n2
);
writel
(
reg
,
mpll
->
base
+
p
->
reg_off
);
writel
(
reg
,
mpll
->
base
+
p
->
reg_off
);
p
=
&
mpll
->
misc
;
if
(
p
->
width
!=
0
)
{
reg
=
readl
(
mpll
->
base
+
p
->
reg_off
);
reg
=
PARM_SET
(
p
->
width
,
p
->
shift
,
reg
,
1
);
writel
(
reg
,
mpll
->
base
+
p
->
reg_off
);
}
if
(
mpll
->
lock
)
if
(
mpll
->
lock
)
spin_unlock_irqrestore
(
mpll
->
lock
,
flags
);
spin_unlock_irqrestore
(
mpll
->
lock
,
flags
);
else
else
...
...
drivers/clk/meson/clk-pll.c
View file @
867a5a12
...
@@ -34,6 +34,7 @@
...
@@ -34,6 +34,7 @@
#include <linux/delay.h>
#include <linux/delay.h>
#include <linux/err.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/io.h>
#include <linux/math64.h>
#include <linux/module.h>
#include <linux/module.h>
#include <linux/of_address.h>
#include <linux/of_address.h>
#include <linux/slab.h>
#include <linux/slab.h>
...
@@ -51,9 +52,8 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
...
@@ -51,9 +52,8 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
{
{
struct
meson_clk_pll
*
pll
=
to_meson_clk_pll
(
hw
);
struct
meson_clk_pll
*
pll
=
to_meson_clk_pll
(
hw
);
struct
parm
*
p
;
struct
parm
*
p
;
unsigned
long
parent_rate_mhz
=
parent_rate
/
1000000
;
u64
rate
;
unsigned
long
rate_mhz
;
u16
n
,
m
,
frac
=
0
,
od
,
od2
=
0
,
od3
=
0
;
u16
n
,
m
,
frac
=
0
,
od
,
od2
=
0
;
u32
reg
;
u32
reg
;
p
=
&
pll
->
n
;
p
=
&
pll
->
n
;
...
@@ -74,17 +74,23 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
...
@@ -74,17 +74,23 @@ static unsigned long meson_clk_pll_recalc_rate(struct clk_hw *hw,
od2
=
PARM_GET
(
p
->
width
,
p
->
shift
,
reg
);
od2
=
PARM_GET
(
p
->
width
,
p
->
shift
,
reg
);
}
}
p
=
&
pll
->
od3
;
if
(
p
->
width
)
{
reg
=
readl
(
pll
->
base
+
p
->
reg_off
);
od3
=
PARM_GET
(
p
->
width
,
p
->
shift
,
reg
);
}
rate
=
(
u64
)
m
*
parent_rate
;
p
=
&
pll
->
frac
;
p
=
&
pll
->
frac
;
if
(
p
->
width
)
{
if
(
p
->
width
)
{
reg
=
readl
(
pll
->
base
+
p
->
reg_off
);
reg
=
readl
(
pll
->
base
+
p
->
reg_off
);
frac
=
PARM_GET
(
p
->
width
,
p
->
shift
,
reg
);
frac
=
PARM_GET
(
p
->
width
,
p
->
shift
,
reg
);
rate_mhz
=
(
parent_rate_mhz
*
m
+
\
(
parent_rate_mhz
*
frac
>>
12
))
*
2
/
n
;
rate_mhz
=
rate_mhz
>>
od
>>
od2
;
}
else
rate_mhz
=
(
parent_rate_mhz
*
m
/
n
)
>>
od
>>
od2
;
return
rate_mhz
*
1000000
;
rate
+=
mul_u64_u32_shr
(
parent_rate
,
frac
,
p
->
width
);
}
return
div_u64
(
rate
,
n
)
>>
od
>>
od2
>>
od3
;
}
}
static
long
meson_clk_pll_round_rate
(
struct
clk_hw
*
hw
,
unsigned
long
rate
,
static
long
meson_clk_pll_round_rate
(
struct
clk_hw
*
hw
,
unsigned
long
rate
,
...
@@ -94,6 +100,13 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
...
@@ -94,6 +100,13 @@ static long meson_clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
const
struct
pll_rate_table
*
rate_table
=
pll
->
rate_table
;
const
struct
pll_rate_table
*
rate_table
=
pll
->
rate_table
;
int
i
;
int
i
;
/*
* if the table is missing, just return the current rate
* since we don't have the other available frequencies
*/
if
(
!
rate_table
)
return
meson_clk_pll_recalc_rate
(
hw
,
*
parent_rate
);
for
(
i
=
0
;
i
<
pll
->
rate_count
;
i
++
)
{
for
(
i
=
0
;
i
<
pll
->
rate_count
;
i
++
)
{
if
(
rate
<=
rate_table
[
i
].
rate
)
if
(
rate
<=
rate_table
[
i
].
rate
)
return
rate_table
[
i
].
rate
;
return
rate_table
[
i
].
rate
;
...
@@ -109,6 +122,9 @@ static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_
...
@@ -109,6 +122,9 @@ static const struct pll_rate_table *meson_clk_get_pll_settings(struct meson_clk_
const
struct
pll_rate_table
*
rate_table
=
pll
->
rate_table
;
const
struct
pll_rate_table
*
rate_table
=
pll
->
rate_table
;
int
i
;
int
i
;
if
(
!
rate_table
)
return
NULL
;
for
(
i
=
0
;
i
<
pll
->
rate_count
;
i
++
)
{
for
(
i
=
0
;
i
<
pll
->
rate_count
;
i
++
)
{
if
(
rate
==
rate_table
[
i
].
rate
)
if
(
rate
==
rate_table
[
i
].
rate
)
return
&
rate_table
[
i
];
return
&
rate_table
[
i
];
...
@@ -215,6 +231,13 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
...
@@ -215,6 +231,13 @@ static int meson_clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
writel
(
reg
,
pll
->
base
+
p
->
reg_off
);
writel
(
reg
,
pll
->
base
+
p
->
reg_off
);
}
}
p
=
&
pll
->
od3
;
if
(
p
->
width
)
{
reg
=
readl
(
pll
->
base
+
p
->
reg_off
);
reg
=
PARM_SET
(
p
->
width
,
p
->
shift
,
reg
,
rate_set
->
od3
);
writel
(
reg
,
pll
->
base
+
p
->
reg_off
);
}
p
=
&
pll
->
frac
;
p
=
&
pll
->
frac
;
if
(
p
->
width
)
{
if
(
p
->
width
)
{
reg
=
readl
(
pll
->
base
+
p
->
reg_off
);
reg
=
readl
(
pll
->
base
+
p
->
reg_off
);
...
...
drivers/clk/meson/clkc.h
View file @
867a5a12
...
@@ -41,6 +41,7 @@ struct pll_rate_table {
...
@@ -41,6 +41,7 @@ struct pll_rate_table {
u16
n
;
u16
n
;
u16
od
;
u16
od
;
u16
od2
;
u16
od2
;
u16
od3
;
u16
frac
;
u16
frac
;
};
};
...
@@ -92,6 +93,7 @@ struct meson_clk_pll {
...
@@ -92,6 +93,7 @@ struct meson_clk_pll {
struct
parm
frac
;
struct
parm
frac
;
struct
parm
od
;
struct
parm
od
;
struct
parm
od2
;
struct
parm
od2
;
struct
parm
od3
;
const
struct
pll_setup_params
params
;
const
struct
pll_setup_params
params
;
const
struct
pll_rate_table
*
rate_table
;
const
struct
pll_rate_table
*
rate_table
;
unsigned
int
rate_count
;
unsigned
int
rate_count
;
...
@@ -119,6 +121,7 @@ struct meson_clk_mpll {
...
@@ -119,6 +121,7 @@ struct meson_clk_mpll {
struct
parm
n2
;
struct
parm
n2
;
struct
parm
en
;
struct
parm
en
;
struct
parm
ssen
;
struct
parm
ssen
;
struct
parm
misc
;
spinlock_t
*
lock
;
spinlock_t
*
lock
;
};
};
...
...
drivers/clk/meson/gxbb.c
View file @
867a5a12
...
@@ -29,98 +29,6 @@
...
@@ -29,98 +29,6 @@
static
DEFINE_SPINLOCK
(
meson_clk_lock
);
static
DEFINE_SPINLOCK
(
meson_clk_lock
);
static
const
struct
pll_rate_table
sys_pll_rate_table
[]
=
{
PLL_RATE
(
24000000
,
56
,
1
,
2
),
PLL_RATE
(
48000000
,
64
,
1
,
2
),
PLL_RATE
(
72000000
,
72
,
1
,
2
),
PLL_RATE
(
96000000
,
64
,
1
,
2
),
PLL_RATE
(
120000000
,
80
,
1
,
2
),
PLL_RATE
(
144000000
,
96
,
1
,
2
),
PLL_RATE
(
168000000
,
56
,
1
,
1
),
PLL_RATE
(
192000000
,
64
,
1
,
1
),
PLL_RATE
(
216000000
,
72
,
1
,
1
),
PLL_RATE
(
240000000
,
80
,
1
,
1
),
PLL_RATE
(
264000000
,
88
,
1
,
1
),
PLL_RATE
(
288000000
,
96
,
1
,
1
),
PLL_RATE
(
312000000
,
52
,
1
,
2
),
PLL_RATE
(
336000000
,
56
,
1
,
2
),
PLL_RATE
(
360000000
,
60
,
1
,
2
),
PLL_RATE
(
384000000
,
64
,
1
,
2
),
PLL_RATE
(
408000000
,
68
,
1
,
2
),
PLL_RATE
(
432000000
,
72
,
1
,
2
),
PLL_RATE
(
456000000
,
76
,
1
,
2
),
PLL_RATE
(
480000000
,
80
,
1
,
2
),
PLL_RATE
(
504000000
,
84
,
1
,
2
),
PLL_RATE
(
528000000
,
88
,
1
,
2
),
PLL_RATE
(
552000000
,
92
,
1
,
2
),
PLL_RATE
(
576000000
,
96
,
1
,
2
),
PLL_RATE
(
600000000
,
50
,
1
,
1
),
PLL_RATE
(
624000000
,
52
,
1
,
1
),
PLL_RATE
(
648000000
,
54
,
1
,
1
),
PLL_RATE
(
672000000
,
56
,
1
,
1
),
PLL_RATE
(
696000000
,
58
,
1
,
1
),
PLL_RATE
(
720000000
,
60
,
1
,
1
),
PLL_RATE
(
744000000
,
62
,
1
,
1
),
PLL_RATE
(
768000000
,
64
,
1
,
1
),
PLL_RATE
(
792000000
,
66
,
1
,
1
),
PLL_RATE
(
816000000
,
68
,
1
,
1
),
PLL_RATE
(
840000000
,
70
,
1
,
1
),
PLL_RATE
(
864000000
,
72
,
1
,
1
),
PLL_RATE
(
888000000
,
74
,
1
,
1
),
PLL_RATE
(
912000000
,
76
,
1
,
1
),
PLL_RATE
(
936000000
,
78
,
1
,
1
),
PLL_RATE
(
960000000
,
80
,
1
,
1
),
PLL_RATE
(
984000000
,
82
,
1
,
1
),
PLL_RATE
(
1008000000
,
84
,
1
,
1
),
PLL_RATE
(
1032000000
,
86
,
1
,
1
),
PLL_RATE
(
1056000000
,
88
,
1
,
1
),
PLL_RATE
(
1080000000
,
90
,
1
,
1
),
PLL_RATE
(
1104000000
,
92
,
1
,
1
),
PLL_RATE
(
1128000000
,
94
,
1
,
1
),
PLL_RATE
(
1152000000
,
96
,
1
,
1
),
PLL_RATE
(
1176000000
,
98
,
1
,
1
),
PLL_RATE
(
1200000000
,
50
,
1
,
0
),
PLL_RATE
(
1224000000
,
51
,
1
,
0
),
PLL_RATE
(
1248000000
,
52
,
1
,
0
),
PLL_RATE
(
1272000000
,
53
,
1
,
0
),
PLL_RATE
(
1296000000
,
54
,
1
,
0
),
PLL_RATE
(
1320000000
,
55
,
1
,
0
),
PLL_RATE
(
1344000000
,
56
,
1
,
0
),
PLL_RATE
(
1368000000
,
57
,
1
,
0
),
PLL_RATE
(
1392000000
,
58
,
1
,
0
),
PLL_RATE
(
1416000000
,
59
,
1
,
0
),
PLL_RATE
(
1440000000
,
60
,
1
,
0
),
PLL_RATE
(
1464000000
,
61
,
1
,
0
),
PLL_RATE
(
1488000000
,
62
,
1
,
0
),
PLL_RATE
(
1512000000
,
63
,
1
,
0
),
PLL_RATE
(
1536000000
,
64
,
1
,
0
),
PLL_RATE
(
1560000000
,
65
,
1
,
0
),
PLL_RATE
(
1584000000
,
66
,
1
,
0
),
PLL_RATE
(
1608000000
,
67
,
1
,
0
),
PLL_RATE
(
1632000000
,
68
,
1
,
0
),
PLL_RATE
(
1656000000
,
68
,
1
,
0
),
PLL_RATE
(
1680000000
,
68
,
1
,
0
),
PLL_RATE
(
1704000000
,
68
,
1
,
0
),
PLL_RATE
(
1728000000
,
69
,
1
,
0
),
PLL_RATE
(
1752000000
,
69
,
1
,
0
),
PLL_RATE
(
1776000000
,
69
,
1
,
0
),
PLL_RATE
(
1800000000
,
69
,
1
,
0
),
PLL_RATE
(
1824000000
,
70
,
1
,
0
),
PLL_RATE
(
1848000000
,
70
,
1
,
0
),
PLL_RATE
(
1872000000
,
70
,
1
,
0
),
PLL_RATE
(
1896000000
,
70
,
1
,
0
),
PLL_RATE
(
1920000000
,
71
,
1
,
0
),
PLL_RATE
(
1944000000
,
71
,
1
,
0
),
PLL_RATE
(
1968000000
,
71
,
1
,
0
),
PLL_RATE
(
1992000000
,
71
,
1
,
0
),
PLL_RATE
(
2016000000
,
72
,
1
,
0
),
PLL_RATE
(
2040000000
,
72
,
1
,
0
),
PLL_RATE
(
2064000000
,
72
,
1
,
0
),
PLL_RATE
(
2088000000
,
72
,
1
,
0
),
PLL_RATE
(
2112000000
,
73
,
1
,
0
),
{
/* sentinel */
},
};
static
const
struct
pll_rate_table
gxbb_gp0_pll_rate_table
[]
=
{
static
const
struct
pll_rate_table
gxbb_gp0_pll_rate_table
[]
=
{
PLL_RATE
(
96000000
,
32
,
1
,
3
),
PLL_RATE
(
96000000
,
32
,
1
,
3
),
PLL_RATE
(
99000000
,
33
,
1
,
3
),
PLL_RATE
(
99000000
,
33
,
1
,
3
),
...
@@ -294,6 +202,11 @@ static struct meson_clk_pll gxbb_fixed_pll = {
...
@@ -294,6 +202,11 @@ static struct meson_clk_pll gxbb_fixed_pll = {
.
shift
=
16
,
.
shift
=
16
,
.
width
=
2
,
.
width
=
2
,
},
},
.
frac
=
{
.
reg_off
=
HHI_MPLL_CNTL2
,
.
shift
=
0
,
.
width
=
12
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"fixed_pll"
,
.
name
=
"fixed_pll"
,
...
@@ -304,6 +217,17 @@ static struct meson_clk_pll gxbb_fixed_pll = {
...
@@ -304,6 +217,17 @@ static struct meson_clk_pll gxbb_fixed_pll = {
},
},
};
};
static
struct
clk_fixed_factor
gxbb_hdmi_pll_pre_mult
=
{
.
mult
=
2
,
.
div
=
1
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"hdmi_pll_pre_mult"
,
.
ops
=
&
clk_fixed_factor_ops
,
.
parent_names
=
(
const
char
*
[]){
"xtal"
},
.
num_parents
=
1
,
},
};
static
struct
meson_clk_pll
gxbb_hdmi_pll
=
{
static
struct
meson_clk_pll
gxbb_hdmi_pll
=
{
.
m
=
{
.
m
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL
,
.
reg_off
=
HHI_HDMI_PLL_CNTL
,
...
@@ -330,6 +254,57 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
...
@@ -330,6 +254,57 @@ static struct meson_clk_pll gxbb_hdmi_pll = {
.
shift
=
22
,
.
shift
=
22
,
.
width
=
2
,
.
width
=
2
,
},
},
.
od3
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL2
,
.
shift
=
18
,
.
width
=
2
,
},
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"hdmi_pll"
,
.
ops
=
&
meson_clk_pll_ro_ops
,
.
parent_names
=
(
const
char
*
[]){
"hdmi_pll_pre_mult"
},
.
num_parents
=
1
,
.
flags
=
CLK_GET_RATE_NOCACHE
,
},
};
static
struct
meson_clk_pll
gxl_hdmi_pll
=
{
.
m
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL
,
.
shift
=
0
,
.
width
=
9
,
},
.
n
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL
,
.
shift
=
9
,
.
width
=
5
,
},
.
frac
=
{
/*
* On gxl, there is a register shift due to HHI_HDMI_PLL_CNTL1
* which does not exist on gxbb, so we compute the register
* offset based on the PLL base to get it right
*/
.
reg_off
=
HHI_HDMI_PLL_CNTL
+
4
,
.
shift
=
0
,
.
width
=
12
,
},
.
od
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL
+
8
,
.
shift
=
21
,
.
width
=
2
,
},
.
od2
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL
+
8
,
.
shift
=
23
,
.
width
=
2
,
},
.
od3
=
{
.
reg_off
=
HHI_HDMI_PLL_CNTL
+
8
,
.
shift
=
19
,
.
width
=
2
,
},
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"hdmi_pll"
,
.
name
=
"hdmi_pll"
,
...
@@ -356,8 +331,6 @@ static struct meson_clk_pll gxbb_sys_pll = {
...
@@ -356,8 +331,6 @@ static struct meson_clk_pll gxbb_sys_pll = {
.
shift
=
10
,
.
shift
=
10
,
.
width
=
2
,
.
width
=
2
,
},
},
.
rate_table
=
sys_pll_rate_table
,
.
rate_count
=
ARRAY_SIZE
(
sys_pll_rate_table
),
.
lock
=
&
meson_clk_lock
,
.
lock
=
&
meson_clk_lock
,
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
hw
.
init
=
&
(
struct
clk_init_data
){
.
name
=
"sys_pll"
,
.
name
=
"sys_pll"
,
...
@@ -1601,6 +1574,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
...
@@ -1601,6 +1574,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[
CLKID_VAPB_1
]
=
&
gxbb_vapb_1
.
hw
,
[
CLKID_VAPB_1
]
=
&
gxbb_vapb_1
.
hw
,
[
CLKID_VAPB_SEL
]
=
&
gxbb_vapb_sel
.
hw
,
[
CLKID_VAPB_SEL
]
=
&
gxbb_vapb_sel
.
hw
,
[
CLKID_VAPB
]
=
&
gxbb_vapb
.
hw
,
[
CLKID_VAPB
]
=
&
gxbb_vapb
.
hw
,
[
CLKID_HDMI_PLL_PRE_MULT
]
=
&
gxbb_hdmi_pll_pre_mult
.
hw
,
[
NR_CLKS
]
=
NULL
,
[
NR_CLKS
]
=
NULL
,
},
},
.
num
=
NR_CLKS
,
.
num
=
NR_CLKS
,
...
@@ -1609,7 +1583,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
...
@@ -1609,7 +1583,7 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
static
struct
clk_hw_onecell_data
gxl_hw_onecell_data
=
{
static
struct
clk_hw_onecell_data
gxl_hw_onecell_data
=
{
.
hws
=
{
.
hws
=
{
[
CLKID_SYS_PLL
]
=
&
gxbb_sys_pll
.
hw
,
[
CLKID_SYS_PLL
]
=
&
gxbb_sys_pll
.
hw
,
[
CLKID_HDMI_PLL
]
=
&
gx
bb
_hdmi_pll
.
hw
,
[
CLKID_HDMI_PLL
]
=
&
gx
l
_hdmi_pll
.
hw
,
[
CLKID_FIXED_PLL
]
=
&
gxbb_fixed_pll
.
hw
,
[
CLKID_FIXED_PLL
]
=
&
gxbb_fixed_pll
.
hw
,
[
CLKID_FCLK_DIV2
]
=
&
gxbb_fclk_div2
.
hw
,
[
CLKID_FCLK_DIV2
]
=
&
gxbb_fclk_div2
.
hw
,
[
CLKID_FCLK_DIV3
]
=
&
gxbb_fclk_div3
.
hw
,
[
CLKID_FCLK_DIV3
]
=
&
gxbb_fclk_div3
.
hw
,
...
@@ -1764,7 +1738,7 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = {
...
@@ -1764,7 +1738,7 @@ static struct meson_clk_pll *const gxbb_clk_plls[] = {
static
struct
meson_clk_pll
*
const
gxl_clk_plls
[]
=
{
static
struct
meson_clk_pll
*
const
gxl_clk_plls
[]
=
{
&
gxbb_fixed_pll
,
&
gxbb_fixed_pll
,
&
gx
bb
_hdmi_pll
,
&
gx
l
_hdmi_pll
,
&
gxbb_sys_pll
,
&
gxbb_sys_pll
,
&
gxl_gp0_pll
,
&
gxl_gp0_pll
,
};
};
...
...
drivers/clk/meson/gxbb.h
View file @
867a5a12
...
@@ -194,8 +194,9 @@
...
@@ -194,8 +194,9 @@
#define CLKID_VPU_1_DIV 130
#define CLKID_VPU_1_DIV 130
#define CLKID_VAPB_0_DIV 134
#define CLKID_VAPB_0_DIV 134
#define CLKID_VAPB_1_DIV 137
#define CLKID_VAPB_1_DIV 137
#define CLKID_HDMI_PLL_PRE_MULT 141
#define NR_CLKS 14
1
#define NR_CLKS 14
2
/* include the CLKIDs that have been made part of the DT binding */
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
#include <dt-bindings/clock/gxbb-clkc.h>
...
...
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