Commit 8693a824 authored by Damien Lespiau's avatar Damien Lespiau Committed by Daniel Vetter

drm/i915: Add references to some workaround we implement

We did not mention the workaround name when implementing those. This
should help us track what we already implement.
Signed-off-by: default avatarDamien Lespiau <damien.lespiau@intel.com>
Reviewed-by: default avatarImre Deak <imre.deak@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent ecdb4eb7
...@@ -333,6 +333,7 @@ mi_set_context(struct intel_ring_buffer *ring, ...@@ -333,6 +333,7 @@ mi_set_context(struct intel_ring_buffer *ring,
if (ret) if (ret)
return ret; return ret;
/* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
if (IS_GEN7(ring->dev)) if (IS_GEN7(ring->dev))
intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE); intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
else else
......
...@@ -174,6 +174,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc) ...@@ -174,6 +174,8 @@ void hsw_fdi_link_train(struct drm_crtc *crtc)
* mode set "sequence for CRT port" document: * mode set "sequence for CRT port" document:
* - TP1 to TP2 time with the default value * - TP1 to TP2 time with the default value
* - FDI delay to 90h * - FDI delay to 90h
*
* WaFDIAutoLinkSetTimingOverrride:hsw
*/ */
I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) | I915_WRITE(_FDI_RXA_MISC, FDI_RX_PWRDN_LANE1_VAL(2) |
FDI_RX_PWRDN_LANE0_VAL(2) | FDI_RX_PWRDN_LANE0_VAL(2) |
......
...@@ -4125,8 +4125,8 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc, ...@@ -4125,8 +4125,8 @@ static int intel_crtc_compute_config(struct drm_crtc *crtc,
if (!pipe_config->timings_set) if (!pipe_config->timings_set)
drm_mode_set_crtcinfo(adjusted_mode, 0); drm_mode_set_crtcinfo(adjusted_mode, 0);
/* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes /* Cantiga+ cannot handle modes with a hsync front porch of 0.
* with a hsync front porch of 0. * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/ */
if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) && if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
adjusted_mode->hsync_start == adjusted_mode->hdisplay) adjusted_mode->hsync_start == adjusted_mode->hdisplay)
......
...@@ -4586,6 +4586,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv) ...@@ -4586,6 +4586,7 @@ static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
FORCEWAKE_ACK_TIMEOUT_MS)) FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
/* WaRsForcewakeWaitTC0:snb */
__gen6_gt_wait_for_thread_c0(dev_priv); __gen6_gt_wait_for_thread_c0(dev_priv);
} }
...@@ -4617,6 +4618,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv) ...@@ -4617,6 +4618,7 @@ static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
FORCEWAKE_ACK_TIMEOUT_MS)) FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
/* WaRsForcewakeWaitTC0:ivb,hsw */
__gen6_gt_wait_for_thread_c0(dev_priv); __gen6_gt_wait_for_thread_c0(dev_priv);
} }
...@@ -4720,6 +4722,7 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv) ...@@ -4720,6 +4722,7 @@ static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
FORCEWAKE_ACK_TIMEOUT_MS)) FORCEWAKE_ACK_TIMEOUT_MS))
DRM_ERROR("Timed out waiting for media to ack forcewake request.\n"); DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
/* WaRsForcewakeWaitTC0:vlv */
__gen6_gt_wait_for_thread_c0(dev_priv); __gen6_gt_wait_for_thread_c0(dev_priv);
} }
......
...@@ -515,6 +515,8 @@ static int init_render_ring(struct intel_ring_buffer *ring) ...@@ -515,6 +515,8 @@ static int init_render_ring(struct intel_ring_buffer *ring)
/* We need to disable the AsyncFlip performance optimisations in order /* We need to disable the AsyncFlip performance optimisations in order
* to use MI_WAIT_FOR_EVENT within the CS. It should already be * to use MI_WAIT_FOR_EVENT within the CS. It should already be
* programmed to '1' on all products. * programmed to '1' on all products.
*
* WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
*/ */
if (INTEL_INFO(dev)->gen >= 6) if (INTEL_INFO(dev)->gen >= 6)
I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
......
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