Commit 886015a0 authored by Gabriel Krisman Bertazi's avatar Gabriel Krisman Bertazi Committed by Ville Syrjälä

drm/i915: reintroduce VLV/CHV PFI programming power domain workaround

There are still cases on these platforms where an attempt is made to
configure the CDCLK while the power domain is off, like when coming back
from a suspend.  So the workaround below is still needed.

This effectively reverts commit 63ff3044 ("drm/i915: Nuke the
VLV/CHV PFI programming power domain workaround").

Cc: stable@vger.kernel.org
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101517Suggested-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarGabriel Krisman Bertazi <krisman@collabora.co.uk>
Link: http://patchwork.freedesktop.org/patch/msgid/20170628210605.4994-1-krisman@collabora.co.ukReviewed-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
parent 7b92c1bd
...@@ -491,6 +491,14 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -491,6 +491,14 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
int cdclk = cdclk_state->cdclk; int cdclk = cdclk_state->cdclk;
u32 val, cmd; u32 val, cmd;
/* There are cases where we can end up here with power domains
* off and a CDCLK frequency other than the minimum, like when
* issuing a modeset without actually changing any display after
* a system suspend. So grab the PIPE-A domain, which covers
* the HW blocks needed for the following programming.
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */ if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
cmd = 2; cmd = 2;
else if (cdclk == 266667) else if (cdclk == 266667)
...@@ -549,6 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -549,6 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
intel_update_cdclk(dev_priv); intel_update_cdclk(dev_priv);
vlv_program_pfi_credits(dev_priv); vlv_program_pfi_credits(dev_priv);
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
} }
static void chv_set_cdclk(struct drm_i915_private *dev_priv, static void chv_set_cdclk(struct drm_i915_private *dev_priv,
...@@ -568,6 +578,14 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -568,6 +578,14 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
return; return;
} }
/* There are cases where we can end up here with power domains
* off and a CDCLK frequency other than the minimum, like when
* issuing a modeset without actually changing any display after
* a system suspend. So grab the PIPE-A domain, which covers
* the HW blocks needed for the following programming.
*/
intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
/* /*
* Specs are full of misinformation, but testing on actual * Specs are full of misinformation, but testing on actual
* hardware has shown that we just need to write the desired * hardware has shown that we just need to write the desired
...@@ -590,6 +608,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv, ...@@ -590,6 +608,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
intel_update_cdclk(dev_priv); intel_update_cdclk(dev_priv);
vlv_program_pfi_credits(dev_priv); vlv_program_pfi_credits(dev_priv);
intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
} }
static int bdw_calc_cdclk(int max_pixclk) static int bdw_calc_cdclk(int max_pixclk)
......
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