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Commit 88b1943b authored by Al Viro's avatar Al Viro Committed by David S. Miller
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starfire: trivial endianness annotations 

Note: we still have several fishy areas - mcast filter
and vlan handling.
Signed-off-by: default avatarAl Viro <viro@zeniv.linux.org.uk>
Signed-off-by: default avatarJeff Garzik <jeff@garzik.org>
parent 37e1370b
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Showing with 44 additions and 44 deletions
drivers/net/starfire.c
View file @ 88b1943b
...@@ -155,7 +155,7 @@ static int full_duplex[MAX_UNITS] = {0, }; ...@@ -155,7 +155,7 @@ static int full_duplex[MAX_UNITS] = {0, };
#if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) #if (defined(__i386__) && defined(CONFIG_HIGHMEM64G)) || defined(__x86_64__) || defined (__ia64__) || defined(__alpha__) || defined(__mips64__) || (defined(__mips__) && defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR))
/* 64-bit dma_addr_t */ /* 64-bit dma_addr_t */
#define ADDR_64BITS /* This chip uses 64 bit addresses. */ #define ADDR_64BITS /* This chip uses 64 bit addresses. */
#define netdrv_addr_t u64 #define netdrv_addr_t __le64
#define cpu_to_dma(x) cpu_to_le64(x) #define cpu_to_dma(x) cpu_to_le64(x)
#define dma_to_cpu(x) le64_to_cpu(x) #define dma_to_cpu(x) le64_to_cpu(x)
#define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit #define RX_DESC_Q_ADDR_SIZE RxDescQAddr64bit
...@@ -164,7 +164,7 @@ static int full_duplex[MAX_UNITS] = {0, }; ...@@ -164,7 +164,7 @@ static int full_duplex[MAX_UNITS] = {0, };
#define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit #define TX_COMPL_Q_ADDR_SIZE TxComplQAddr64bit
#define RX_DESC_ADDR_SIZE RxDescAddr64bit #define RX_DESC_ADDR_SIZE RxDescAddr64bit
#else /* 32-bit dma_addr_t */ #else /* 32-bit dma_addr_t */
#define netdrv_addr_t u32 #define netdrv_addr_t __le32
#define cpu_to_dma(x) cpu_to_le32(x) #define cpu_to_dma(x) cpu_to_le32(x)
#define dma_to_cpu(x) le32_to_cpu(x) #define dma_to_cpu(x) le32_to_cpu(x)
#define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit #define RX_DESC_Q_ADDR_SIZE RxDescQAddr32bit
...@@ -494,7 +494,7 @@ enum intr_ctrl_bits { ...@@ -494,7 +494,7 @@ enum intr_ctrl_bits {
/* The Rx and Tx buffer descriptors. */ /* The Rx and Tx buffer descriptors. */
struct starfire_rx_desc { struct starfire_rx_desc {
dma_addr_t rxaddr; netdrv_addr_t rxaddr;
}; };
enum rx_desc_bits { enum rx_desc_bits {
RxDescValid=1, RxDescEndRing=2, RxDescValid=1, RxDescEndRing=2,
...@@ -502,25 +502,25 @@ enum rx_desc_bits { ...@@ -502,25 +502,25 @@ enum rx_desc_bits {
/* Completion queue entry. */ /* Completion queue entry. */
struct short_rx_done_desc { struct short_rx_done_desc {
u32 status; /* Low 16 bits is length. */ __le32 status; /* Low 16 bits is length. */
}; };
struct basic_rx_done_desc { struct basic_rx_done_desc {
u32 status; /* Low 16 bits is length. */ __le32 status; /* Low 16 bits is length. */
u16 vlanid; __le16 vlanid;
u16 status2; __le16 status2;
}; };
struct csum_rx_done_desc { struct csum_rx_done_desc {
u32 status; /* Low 16 bits is length. */ __le32 status; /* Low 16 bits is length. */
u16 csum; /* Partial checksum */ __le16 csum; /* Partial checksum */
u16 status2; __le16 status2;
}; };
struct full_rx_done_desc { struct full_rx_done_desc {
u32 status; /* Low 16 bits is length. */ __le32 status; /* Low 16 bits is length. */
u16 status3; __le16 status3;
u16 status2; __le16 status2;
u16 vlanid; __le16 vlanid;
u16 csum; /* partial checksum */ __le16 csum; /* partial checksum */
u32 timestamp; __le32 timestamp;
}; };
/* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */ /* XXX: this is ugly and I'm not sure it's worth the trouble -Ion */
#ifdef VLAN_SUPPORT #ifdef VLAN_SUPPORT
...@@ -537,15 +537,15 @@ enum rx_done_bits { ...@@ -537,15 +537,15 @@ enum rx_done_bits {
/* Type 1 Tx descriptor. */ /* Type 1 Tx descriptor. */
struct starfire_tx_desc_1 { struct starfire_tx_desc_1 {
u32 status; /* Upper bits are status, lower 16 length. */ __le32 status; /* Upper bits are status, lower 16 length. */
u32 addr; __le32 addr;
}; };
/* Type 2 Tx descriptor. */ /* Type 2 Tx descriptor. */
struct starfire_tx_desc_2 { struct starfire_tx_desc_2 {
u32 status; /* Upper bits are status, lower 16 length. */ __le32 status; /* Upper bits are status, lower 16 length. */
u32 reserved; __le32 reserved;
u64 addr; __le64 addr;
}; };
#ifdef ADDR_64BITS #ifdef ADDR_64BITS
...@@ -563,9 +563,9 @@ enum tx_desc_bits { ...@@ -563,9 +563,9 @@ enum tx_desc_bits {
TxRingWrap=0x04000000, TxCalTCP=0x02000000, TxRingWrap=0x04000000, TxCalTCP=0x02000000,
}; };
struct tx_done_desc { struct tx_done_desc {
u32 status; /* timestamp, index. */ __le32 status; /* timestamp, index. */
#if 0 #if 0
u32 intrstatus; /* interrupt status */ __le32 intrstatus; /* interrupt status */
#endif #endif
}; };
...@@ -963,7 +963,7 @@ static int netdev_open(struct net_device *dev) ...@@ -963,7 +963,7 @@ static int netdev_open(struct net_device *dev)
dev->name, dev->irq); dev->name, dev->irq);
/* Allocate the various queues. */ /* Allocate the various queues. */
if (np->queue_mem == 0) { if (!np->queue_mem) {
tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; tx_done_q_size = ((sizeof(struct tx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; rx_done_q_size = ((sizeof(rx_done_desc) * DONE_Q_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN; tx_ring_size = ((sizeof(starfire_tx_desc) * TX_RING_SIZE + QUEUE_ALIGN - 1) / QUEUE_ALIGN) * QUEUE_ALIGN;
...@@ -1036,11 +1036,11 @@ static int netdev_open(struct net_device *dev) ...@@ -1036,11 +1036,11 @@ static int netdev_open(struct net_device *dev)
writew(0, ioaddr + PerfFilterTable + 4); writew(0, ioaddr + PerfFilterTable + 4);
writew(0, ioaddr + PerfFilterTable + 8); writew(0, ioaddr + PerfFilterTable + 8);
for (i = 1; i < 16; i++) { for (i = 1; i < 16; i++) {
u16 *eaddrs = (u16 *)dev->dev_addr; __be16 *eaddrs = (__be16 *)dev->dev_addr;
void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16; void __iomem *setup_frm = ioaddr + PerfFilterTable + i * 16;
writew(cpu_to_be16(eaddrs[2]), setup_frm); setup_frm += 4; writew(be16_to_cpu(eaddrs[2]), setup_frm); setup_frm += 4;
writew(cpu_to_be16(eaddrs[1]), setup_frm); setup_frm += 4; writew(be16_to_cpu(eaddrs[1]), setup_frm); setup_frm += 4;
writew(cpu_to_be16(eaddrs[0]), setup_frm); setup_frm += 8; writew(be16_to_cpu(eaddrs[0]), setup_frm); setup_frm += 8;
} }
/* Initialize other registers. */ /* Initialize other registers. */
...@@ -1767,26 +1767,26 @@ static void set_rx_mode(struct net_device *dev) ...@@ -1767,26 +1767,26 @@ static void set_rx_mode(struct net_device *dev)
} else if (dev->mc_count <= 14) { } else if (dev->mc_count <= 14) {
/* Use the 16 element perfect filter, skip first two entries. */ /* Use the 16 element perfect filter, skip first two entries. */
void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16; void __iomem *filter_addr = ioaddr + PerfFilterTable + 2 * 16;
u16 *eaddrs; __be16 *eaddrs;
for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2; for (i = 2, mclist = dev->mc_list; mclist && i < dev->mc_count + 2;
i++, mclist = mclist->next) { i++, mclist = mclist->next) {
eaddrs = (u16 *)mclist->dmi_addr; eaddrs = (__be16 *)mclist->dmi_addr;
writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 4; writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 4;
writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 8; writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 8;
} }
eaddrs = (u16 *)dev->dev_addr; eaddrs = (__be16 *)dev->dev_addr;
while (i++ < 16) { while (i++ < 16) {
writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
} }
rx_mode |= AcceptBroadcast|PerfectFilter; rx_mode |= AcceptBroadcast|PerfectFilter;
} else { } else {
/* Must use a multicast hash table. */ /* Must use a multicast hash table. */
void __iomem *filter_addr; void __iomem *filter_addr;
u16 *eaddrs; __be16 *eaddrs;
u16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */ __le16 mc_filter[32] __attribute__ ((aligned(sizeof(long)))); /* Multicast hash filter */
memset(mc_filter, 0, sizeof(mc_filter)); memset(mc_filter, 0, sizeof(mc_filter));
for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count; for (i = 0, mclist = dev->mc_list; mclist && i < dev->mc_count;
...@@ -1794,17 +1794,17 @@ static void set_rx_mode(struct net_device *dev) ...@@ -1794,17 +1794,17 @@ static void set_rx_mode(struct net_device *dev)
/* The chip uses the upper 9 CRC bits /* The chip uses the upper 9 CRC bits
as index into the hash table */ as index into the hash table */
int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23; int bit_nr = ether_crc_le(ETH_ALEN, mclist->dmi_addr) >> 23;
__u32 *fptr = (__u32 *) &mc_filter[(bit_nr >> 4) & ~1]; __le32 *fptr = (__le32 *) &mc_filter[(bit_nr >> 4) & ~1];
*fptr |= cpu_to_le32(1 << (bit_nr & 31)); *fptr |= cpu_to_le32(1 << (bit_nr & 31));
} }
/* Clear the perfect filter list, skip first two entries. */ /* Clear the perfect filter list, skip first two entries. */
filter_addr = ioaddr + PerfFilterTable + 2 * 16; filter_addr = ioaddr + PerfFilterTable + 2 * 16;
eaddrs = (u16 *)dev->dev_addr; eaddrs = (__be16 *)dev->dev_addr;
for (i = 2; i < 16; i++) { for (i = 2; i < 16; i++) {
writew(cpu_to_be16(eaddrs[0]), filter_addr); filter_addr += 4; writew(be16_to_cpu(eaddrs[0]), filter_addr); filter_addr += 4;
writew(cpu_to_be16(eaddrs[1]), filter_addr); filter_addr += 4; writew(be16_to_cpu(eaddrs[1]), filter_addr); filter_addr += 4;
writew(cpu_to_be16(eaddrs[2]), filter_addr); filter_addr += 8; writew(be16_to_cpu(eaddrs[2]), filter_addr); filter_addr += 8;
} }
for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++) for (filter_addr = ioaddr + HashTable, i = 0; i < 32; filter_addr+= 16, i++)
writew(mc_filter[i], filter_addr); writew(mc_filter[i], filter_addr);
......
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