Commit 8edbede9 authored by Richard Röjfors's avatar Richard Röjfors Committed by Mauro Carvalho Chehab

V4L/DVB: mfd: Add support for the timberdale FPGA

The timberdale FPGA is found on the Intel in-Vehicle Infotainment reference board
russelville.

The driver is a PCI driver which chunks up the I/O memory and distributes interrupts
to a number of platform devices for each IP inside the FPGA.
Signed-off-by: default avatarRichard Röjfors <richard.rojfors@pelagicore.com>
Signed-off-by: default avatarSamuel Ortiz <sameo@linux.intel.com>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent d44d1f3b
...@@ -348,6 +348,16 @@ config AB4500_CORE ...@@ -348,6 +348,16 @@ config AB4500_CORE
read/write functions for the devices to get access to this chip. read/write functions for the devices to get access to this chip.
This chip embeds various other multimedia funtionalities as well. This chip embeds various other multimedia funtionalities as well.
config MFD_TIMBERDALE
tristate "Support for the Timberdale FPGA"
select MFD_CORE
depends on PCI
---help---
This is the core driver for the timberdale FPGA. This device is a
multifunction device which exposes numerous platform devices.
The timberdale FPGA can be found on the Intel Atom development board
for in-vehicle infontainment, called Russellville.
endmenu endmenu
menu "Multimedia Capabilities Port drivers" menu "Multimedia Capabilities Port drivers"
......
...@@ -54,5 +54,6 @@ obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o ...@@ -54,5 +54,6 @@ obj-$(CONFIG_PCF50633_GPIO) += pcf50633-gpio.o
obj-$(CONFIG_AB3100_CORE) += ab3100-core.o obj-$(CONFIG_AB3100_CORE) += ab3100-core.o
obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o obj-$(CONFIG_AB3100_OTP) += ab3100-otp.o
obj-$(CONFIG_AB4500_CORE) += ab4500-core.o obj-$(CONFIG_AB4500_CORE) += ab4500-core.o
obj-$(CONFIG_MFD_TIMBERDALE) += timberdale.o
obj-$(CONFIG_MFD_88PM8607) += 88pm8607.o obj-$(CONFIG_MFD_88PM8607) += 88pm8607.o
obj-$(CONFIG_PMIC_ADP5520) += adp5520.o obj-$(CONFIG_PMIC_ADP5520) += adp5520.o
\ No newline at end of file
This diff is collapsed.
/*
* timberdale.h timberdale FPGA MFD driver defines
* Copyright (c) 2009 Intel Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
/* Supports:
* Timberdale FPGA
*/
#ifndef MFD_TIMBERDALE_H
#define MFD_TIMBERDALE_H
#define DRV_VERSION "0.1"
/* This driver only support versions >= 3.8 and < 4.0 */
#define TIMB_SUPPORTED_MAJOR 3
/* This driver only support minor >= 8 */
#define TIMB_REQUIRED_MINOR 8
/* Registers of the control area */
#define TIMB_REV_MAJOR 0x00
#define TIMB_REV_MINOR 0x04
#define TIMB_HW_CONFIG 0x08
#define TIMB_SW_RST 0x40
/* bits in the TIMB_HW_CONFIG register */
#define TIMB_HW_CONFIG_SPI_8BIT 0x80
#define TIMB_HW_VER_MASK 0x0f
#define TIMB_HW_VER0 0x00
#define TIMB_HW_VER1 0x01
#define TIMB_HW_VER2 0x02
#define TIMB_HW_VER3 0x03
#define OCORESOFFSET 0x0
#define OCORESEND 0x1f
#define SPIOFFSET 0x80
#define SPIEND 0xff
#define UARTLITEOFFSET 0x100
#define UARTLITEEND 0x10f
#define RDSOFFSET 0x180
#define RDSEND 0x183
#define ETHOFFSET 0x300
#define ETHEND 0x3ff
#define GPIOOFFSET 0x400
#define GPIOEND 0x7ff
#define CHIPCTLOFFSET 0x800
#define CHIPCTLEND 0x8ff
#define CHIPCTLSIZE (CHIPCTLEND - CHIPCTLOFFSET)
#define INTCOFFSET 0xc00
#define INTCEND 0xfff
#define INTCSIZE (INTCEND - INTCOFFSET)
#define MOSTOFFSET 0x1000
#define MOSTEND 0x13ff
#define UARTOFFSET 0x1400
#define UARTEND 0x17ff
#define XIICOFFSET 0x1800
#define XIICEND 0x19ff
#define I2SOFFSET 0x1C00
#define I2SEND 0x1fff
#define LOGIWOFFSET 0x30000
#define LOGIWEND 0x37fff
#define MLCOREOFFSET 0x40000
#define MLCOREEND 0x43fff
#define DMAOFFSET 0x01000000
#define DMAEND 0x013fffff
/* SDHC0 is placed in PCI bar 1 */
#define SDHC0OFFSET 0x00
#define SDHC0END 0xff
/* SDHC1 is placed in PCI bar 2 */
#define SDHC1OFFSET 0x00
#define SDHC1END 0xff
#define PCI_VENDOR_ID_TIMB 0x10ee
#define PCI_DEVICE_ID_TIMB 0xa123
#define IRQ_TIMBERDALE_INIC 0
#define IRQ_TIMBERDALE_MLB 1
#define IRQ_TIMBERDALE_GPIO 2
#define IRQ_TIMBERDALE_I2C 3
#define IRQ_TIMBERDALE_UART 4
#define IRQ_TIMBERDALE_DMA 5
#define IRQ_TIMBERDALE_I2S 6
#define IRQ_TIMBERDALE_TSC_INT 7
#define IRQ_TIMBERDALE_SDHC 8
#define IRQ_TIMBERDALE_ADV7180 9
#define IRQ_TIMBERDALE_ETHSW_IF 10
#define IRQ_TIMBERDALE_SPI 11
#define IRQ_TIMBERDALE_UARTLITE 12
#define IRQ_TIMBERDALE_MLCORE 13
#define IRQ_TIMBERDALE_MLCORE_BUF 14
#define IRQ_TIMBERDALE_RDS 15
#define TIMBERDALE_NR_IRQS 16
#define GPIO_PIN_ASCB 8
#define GPIO_PIN_INIC_RST 14
#define GPIO_PIN_BT_RST 15
#define GPIO_NR_PINS 16
#endif
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