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Commit 8f07b1d5 authored by Arnd Bergmann's avatar Arnd Bergmann
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Merge tag 'renesas-boards-for-v3.10' of... 

Merge tag 'renesas-boards-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards

From Simon Horman <horms+renesas@verge.net.au>:

Renesas ARM-based SoC board updates for v3.10

This is based on a merge of the following:

git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-pinmux-for-v3.10
git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas.git renesas-soc-for-v3.10

* tag 'renesas-boards-for-v3.10' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (218 commits)
  ARM: shmobile: kzm9g: correct smsc regulator registration
  ARM: shmobile: marzen: Use gic_iid macro for ICCIAR / interrupt ID
  ARM: shmobile: kzm9g: Trim reference DT_MACHINE_START
  ARM: shmobile: kzm9g: Remove warning about SMP
  ARM: shmobile: simplify kzm9g Kconfig dependencies
  ARM: shmobile: SDHI and MMCIF interfaces to kzm9g-reference
  ARM: shmobile: parse DT and configure pinmux early on kzm9g-reference
  ARM: shmobile: kzm9g: Reference DT implementation
  ARM: shmobile: marzen: Reference DT implementation
  ARM: shmobile: mark mackerel sh_mmcif_device __maybe_unused
  ARM: shmobile: streamline mackerel SD and MMC devices
  ARM: shmobile: switch SDHI0 to GPIO regulator on armadillo800eva
  ARM: shmobile: use GPIO SD-card detection on armadillo800eva
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parents f6161aa1 48296a13
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Documentation/devicetree/bindings/gpio/gpio.txt
View file @ 8f07b1d5
......@@ -98,7 +98,7 @@ announce the pinrange to the pin ctrl subsystem. For example,
compatible = "fsl,qe-pario-bank-e", "fsl,qe-pario-bank";
reg = <0x1460 0x18>;
gpio-controller;
gpio-ranges = <&pinctrl1 20 10>, <&pinctrl2 50 20>;
gpio-ranges = <&pinctrl1 0 20 10>, <&pinctrl2 10 50 20>;
}
......@@ -107,8 +107,8 @@ where,
Next values specify the base pin and number of pins for the range
handled by 'qe_pio_e' gpio. In the given example from base pin 20 to
pin 29 under pinctrl1 and pin 50 to pin 69 under pinctrl2 is handled
by this gpio controller.
pin 29 under pinctrl1 with gpio offset 0 and pin 50 to pin 69 under
pinctrl2 with gpio offset 10 is handled by this gpio controller.
The pinctrl node must have "#gpio-range-cells" property to show number of
arguments to pass with phandle from gpio controllers node.
Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
View file @ 8f07b1d5
One-register-per-pin type device tree based pinctrl driver
Required properties:
- compatible : "pinctrl-single"
- compatible : "pinctrl-single" or "pinconf-single".
"pinctrl-single" means that pinconf isn't supported.
"pinconf-single" means that generic pinconf is supported.
- reg : offset and length of the register set for the mux registers
......@@ -14,9 +16,61 @@ Optional properties:
- pinctrl-single,function-off : function off mode for disabled state if
available and same for all registers; if not specified, disabling of
pin functions is ignored
- pinctrl-single,bit-per-mux : boolean to indicate that one register controls
more than one pin
- pinctrl-single,drive-strength : array of value that are used to configure
drive strength in the pinmux register. They're value of drive strength
current and drive strength mask.
/* drive strength current, mask */
pinctrl-single,power-source = <0x30 0xf0>;
- pinctrl-single,bias-pullup : array of value that are used to configure the
input bias pullup in the pinmux register.
/* input, enabled pullup bits, disabled pullup bits, mask */
pinctrl-single,bias-pullup = <0 1 0 1>;
- pinctrl-single,bias-pulldown : array of value that are used to configure the
input bias pulldown in the pinmux register.
/* input, enabled pulldown bits, disabled pulldown bits, mask */
pinctrl-single,bias-pulldown = <2 2 0 2>;
* Two bits to control input bias pullup and pulldown: User should use
pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. One bit means
pullup, and the other one bit means pulldown.
* Three bits to control input bias enable, pullup and pulldown. User should
use pinctrl-single,bias-pullup & pinctrl-single,bias-pulldown. Input bias
enable bit should be included in pullup or pulldown bits.
* Although driver could set PIN_CONFIG_BIAS_DISABLE, there's no property as
pinctrl-single,bias-disable. Because pinctrl single driver could implement
it by calling pulldown, pullup disabled.
- pinctrl-single,input-schmitt : array of value that are used to configure
input schmitt in the pinmux register. In some silicons, there're two input
schmitt value (rising-edge & falling-edge) in the pinmux register.
/* input schmitt value, mask */
pinctrl-single,input-schmitt = <0x30 0x70>;
- pinctrl-single,input-schmitt-enable : array of value that are used to
configure input schmitt enable or disable in the pinmux register.
/* input, enable bits, disable bits, mask */
pinctrl-single,input-schmitt-enable = <0x30 0x40 0 0x70>;
- pinctrl-single,gpio-range : list of value that are used to configure a GPIO
range. They're value of subnode phandle, pin base in pinctrl device, pin
number in this range, GPIO function value of this GPIO range.
The number of parameters is depend on #pinctrl-single,gpio-range-cells
property.
/* pin base, nr pins & gpio function */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1>;
This driver assumes that there is only one register for each pin (unless the
pinctrl-single,bit-per-mux is set), and uses the common pinctrl bindings as
specified in the pinctrl-bindings.txt document in this directory.
......@@ -42,6 +96,20 @@ Where 0xdc is the offset from the pinctrl register base address for the
device pinctrl register, 0x18 is the desired value, and 0xff is the sub mask to
be used when applying this change to the register.
Optional sub-node: In case some pins could be configured as GPIO in the pinmux
register, those pins could be defined as a GPIO range. This sub-node is required
by pinctrl-single,gpio-range property.
Required properties in sub-node:
- #pinctrl-single,gpio-range-cells : the number of parameters after phandle in
pinctrl-single,gpio-range property.
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
Example:
/* SoC common file */
......@@ -76,6 +144,29 @@ control_devconf0: pinmux@48002274 {
pinctrl-single,function-mask = <0x5F>;
};
/* third controller instance for pins in gpio domain */
pmx_gpio: pinmux@d401e000 {
compatible = "pinconf-single";
reg = <0xd401e000 0x0330>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <7>;
/* sparse GPIO range could be supported */
pinctrl-single,gpio-range = <&range 0 3 0 &range 3 9 1
&range 12 1 0 &range 13 29 1
&range 43 1 0 &range 44 49 1
&range 94 1 1 &range 96 2 1>;
range: gpio-range {
#pinctrl-single,gpio-range-cells = <3>;
};
};
/* board specific .dts file */
&pmx_core {
......@@ -96,6 +187,15 @@ control_devconf0: pinmux@48002274 {
>;
};
uart0_pins: pinmux_uart0_pins {
pinctrl-single,pins = <
0x208 0 /* UART0_RXD (IOCFG138) */
0x20c 0 /* UART0_TXD (IOCFG139) */
>;
pinctrl-single,bias-pulldown = <0 2 2>;
pinctrl-single,bias-pullup = <0 1 1>;
};
/* map uart2 pins */
uart2_pins: pinmux_uart2_pins {
pinctrl-single,pins = <
......@@ -122,6 +222,11 @@ control_devconf0: pinmux@48002274 {
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&uart2_pins>;
......
arch/arm/boot/dts/Makefile
View file @ 8f07b1d5
......@@ -136,7 +136,9 @@ dtb-$(CONFIG_ARCH_U8500) += snowball.dtb \
ccu9540.dtb
dtb-$(CONFIG_ARCH_SHMOBILE) += emev2-kzm9d.dtb \
r8a7740-armadillo800eva.dtb \
r8a7779-marzen-reference.dtb \
sh73a0-kzm9g.dtb \
sh73a0-kzm9g-reference.dtb \
sh7372-mackerel.dtb
dtb-$(CONFIG_ARCH_SOCFPGA) += socfpga_cyclone5.dtb \
socfpga_vt.dtb
......
arch/arm/boot/dts/r8a7779-marzen-reference.dts 0 → 100644
View file @ 8f07b1d5
/*
* Reference Device Tree Source for the Marzen board
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
/include/ "r8a7779.dtsi"
/ {
model = "marzen";
compatible = "renesas,marzen-reference", "renesas,r8a7779";
chosen {
bootargs = "console=ttySC2,115200 earlyprintk=sh-sci.2,115200 ignore_loglevel root=/dev/nfs ip=on";
};
memory {
device_type = "memory";
reg = <0x60000000 0x40000000>;
};
fixedregulator3v3: fixedregulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-3.3V";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
lan0@18000000 {
compatible = "smsc,lan9220", "smsc,lan9115";
reg = <0x18000000 0x100>;
phy-mode = "mii";
interrupt-parent = <&gic>;
interrupts = <0 28 0x4>;
reg-io-width = <4>;
vddvario-supply = <&fixedregulator3v3>;
vdd33a-supply = <&fixedregulator3v3>;
};
};
arch/arm/boot/dts/r8a7779.dtsi 0 → 100644
View file @ 8f07b1d5
/*
* Device Tree Source for Renesas r8a7779
*
* Copyright (C) 2013 Renesas Solutions Corp.
* Copyright (C) 2013 Simon Horman
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/include/ "skeleton.dtsi"
/ {
compatible = "renesas,r8a7779";
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
};
};
gic: interrupt-controller@f0001000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
reg = <0xf0001000 0x1000>,
<0xf0000100 0x100>;
};
i2c0: i2c@0xffc70000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc70000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 79 0x4>;
};
i2c1: i2c@0xffc71000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc71000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 82 0x4>;
};
i2c2: i2c@0xffc72000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc72000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 80 0x4>;
};
i2c3: i2c@0xffc73000 {
#address-cells = <1>;
#size-cells = <0>;
compatible = "renesas,rmobile-iic";
reg = <0xffc73000 0x1000>;
interrupt-parent = <&gic>;
interrupts = <0 81 0x4>;
};
thermal@ffc48000 {
compatible = "renesas,rcar-thermal";
reg = <0xffc48000 0x38>;
};
sata: sata@fc600000 {
compatible = "renesas,rcar-sata";
reg = <0xfc600000 0x2000>;
interrupt-parent = <&gic>;
interrupts = <0 100 0x4>;
};
};
arch/arm/boot/dts/sh73a0-kzm9g-reference.dts 0 → 100644
View file @ 8f07b1d5
/*
* Device Tree Source for the KZM-A9-GT board
*
* Copyright (C) 2012 Horms Solutions Ltd.
*
* Based on sh73a0-kzm9g.dts
* Copyright (C) 2012 Renesas Solutions Corp.
*
* This file is licensed under the terms of the GNU General Public License
* version 2. This program is licensed "as is" without any warranty of any
* kind, whether express or implied.
*/
/dts-v1/;
/include/ "sh73a0-reference.dtsi"
/ {
model = "KZM-A9-GT";
compatible = "renesas,kzm9g-reference", "renesas,sh73a0";
chosen {
bootargs = "console=tty0 console=ttySC4,115200 root=/dev/nfs ip=dhcp ignore_loglevel earlyprintk=sh-sci.4,115200";
};
memory {
device_type = "memory";
reg = <0x41000000 0x1e800000>;
};
reg_1p8v: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "fixed-1.8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
regulator-boot-on;
};
reg_2p8v: regulator@1 {
compatible = "regulator-fixed";
regulator-name = "fixed-2.8V";
regulator-min-microvolt = <2800000>;
regulator-max-microvolt = <2800000>;
regulator-always-on;
regulator-boot-on;
};
sdhi0: sdhi@0xee100000 {
compatible = "renesas,shmobile-sdhi";
reg = <0xee100000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 83 4
0 84 4
0 85 4>;
vmmc-supply = <&reg_2p8v>;
bus-width = <4>;
toshiba,mmc-has-idle-wait;
};
sdhi2: sdhi@0xee140000 {
compatible = "renesas,shmobile-sdhi";
reg = <0xee140000 0x100>;
interrupt-parent = <&gic>;
interrupts = <0 104 4
0 105 4>;
vmmc-supply = <&reg_2p8v>;
bus-width = <4>;
broken-cd;
toshiba,mmc-wrprotect-disable;
toshiba,mmc-has-idle-wait;
};
};
&mmcif {
bus-width = <8>;
vmmc-supply = <&reg_1p8v>;
};
arch/arm/boot/dts/spear1310.dtsi
View file @ 8f07b1d5
......@@ -89,7 +89,7 @@ gmac4: eth@5c700000 {
pinmux: pinmux@e0700000 {
compatible = "st,spear1310-pinmux";
reg = <0xe0700000 0x1000>;
#gpio-range-cells = <2>;
#gpio-range-cells = <3>;
};
apb {
......@@ -212,7 +212,7 @@ gpiopinctrl: gpio@d8400000 {
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 246>;
gpio-ranges = <&pinmux 0 0 246>;
status = "disabled";
st-plgpio,ngpio = <246>;
......
arch/arm/boot/dts/spear1340.dtsi
View file @ 8f07b1d5
......@@ -63,7 +63,7 @@ i2s-rec@b2000000 {
pinmux: pinmux@e0700000 {
compatible = "st,spear1340-pinmux";
reg = <0xe0700000 0x1000>;
#gpio-range-cells = <2>;
#gpio-range-cells = <3>;
};
pwm: pwm@e0180000 {
......@@ -127,7 +127,7 @@ gpiopinctrl: gpio@e2800000 {
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 252>;
gpio-ranges = <&pinmux 0 0 252>;
status = "disabled";
st-plgpio,ngpio = <250>;
......
arch/arm/boot/dts/spear310.dtsi
View file @ 8f07b1d5
......@@ -25,7 +25,7 @@ ahb {
pinmux: pinmux@b4000000 {
compatible = "st,spear310-pinmux";
reg = <0xb4000000 0x1000>;
#gpio-range-cells = <2>;
#gpio-range-cells = <3>;
};
fsmc: flash@44000000 {
......@@ -102,7 +102,7 @@ gpiopinctrl: gpio@b4000000 {
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 102>;
gpio-ranges = <&pinmux 0 0 102>;
status = "disabled";
st-plgpio,ngpio = <102>;
......
arch/arm/boot/dts/spear320.dtsi
View file @ 8f07b1d5
......@@ -24,7 +24,7 @@ ahb {
pinmux: pinmux@b3000000 {
compatible = "st,spear320-pinmux";
reg = <0xb3000000 0x1000>;
#gpio-range-cells = <2>;
#gpio-range-cells = <3>;
};
clcd@90000000 {
......@@ -130,7 +130,7 @@ gpiopinctrl: gpio@b3000000 {
interrupt-controller;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pinmux 0 102>;
gpio-ranges = <&pinmux 0 0 102>;
status = "disabled";
st-plgpio,ngpio = <102>;
......
arch/arm/mach-shmobile/Kconfig
View file @ 8f07b1d5
......@@ -102,6 +102,19 @@ config MACH_MARZEN
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
config MACH_MARZEN_REFERENCE
bool "MARZEN board - Reference Device Tree Implementation"
depends on ARCH_R8A7779
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select USE_OF
---help---
Use reference implementation of Marzen board support
which makes use of device tree at the expense
of not supporting a number of devices.
This is intended to aid developers
config MACH_KZM9D
bool "KZM9D board"
depends on ARCH_EMEV2
......@@ -116,6 +129,20 @@ config MACH_KZM9G
select SND_SOC_AK4642 if SND_SIMPLE_CARD
select USE_OF
config MACH_KZM9G_REFERENCE
bool "KZM-A9-GT board - Reference Device Tree Implementation"
depends on ARCH_SH73A0
select ARCH_REQUIRE_GPIOLIB
select REGULATOR_FIXED_VOLTAGE if REGULATOR
select SND_SOC_AK4642 if SND_SIMPLE_CARD
select USE_OF
---help---
Use reference implementation of KZM-A9-GT board support
which makes as greater use of device tree at the expense
of not supporting a number of devices.
This is intended to aid developers
comment "SH-Mobile System Configuration"
config CPU_HAS_INTEVT
......
arch/arm/mach-shmobile/Makefile
View file @ 8f07b1d5
......@@ -14,10 +14,9 @@ obj-$(CONFIG_ARCH_EMEV2) += setup-emev2.o clock-emev2.o
# SMP objects
smp-y := platsmp.o headsmp.o
smp-$(CONFIG_HOTPLUG_CPU) += hotplug.o
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-sh73a0.o
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o
smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o
smp-$(CONFIG_ARCH_SH73A0) += smp-sh73a0.o headsmp-scu.o
smp-$(CONFIG_ARCH_R8A7779) += smp-r8a7779.o headsmp-scu.o
smp-$(CONFIG_ARCH_EMEV2) += smp-emev2.o headsmp-scu.o
# IRQ objects
obj-$(CONFIG_ARCH_SH7372) += entry-intc.o
......@@ -39,9 +38,11 @@ obj-$(CONFIG_MACH_MACKEREL) += board-mackerel.o
obj-$(CONFIG_MACH_KOTA2) += board-kota2.o
obj-$(CONFIG_MACH_BONITO) += board-bonito.o
obj-$(CONFIG_MACH_MARZEN) += board-marzen.o
obj-$(CONFIG_MACH_MARZEN_REFERENCE) += board-marzen-reference.o
obj-$(CONFIG_MACH_ARMADILLO800EVA) += board-armadillo800eva.o
obj-$(CONFIG_MACH_KZM9D) += board-kzm9d.o
obj-$(CONFIG_MACH_KZM9G) += board-kzm9g.o
obj-$(CONFIG_MACH_KZM9G_REFERENCE) += board-kzm9g-reference.o
# Framework support
obj-$(CONFIG_SMP) += $(smp-y)
arch/arm/mach-shmobile/board-ag5evm.c
View file @ 8f07b1d5
......@@ -23,6 +23,8 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
......@@ -304,9 +306,9 @@ static int lcd_backlight_set_brightness(int brightness)
if (brightness == 0) {
/* Reset the chip */
gpio_set_value(GPIO_PORT235, 0);
gpio_set_value(235, 0);
mdelay(24);
gpio_set_value(GPIO_PORT235, 1);
gpio_set_value(235, 1);
return 0;
}
......@@ -406,7 +408,7 @@ static struct sh_mobile_sdhi_info sdhi0_info = {
.tmio_flags = TMIO_MMC_HAS_IDLE_WAIT | TMIO_MMC_USE_GPIO_CD,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
.cd_gpio = GPIO_PORT251,
.cd_gpio = 251,
};
static struct resource sdhi0_resources[] = {
......@@ -461,7 +463,7 @@ static struct regulator_init_data cn4_power_init_data = {
static struct fixed_voltage_config cn4_power_info = {
.supply_name = "CN4 SD/MMC Vdd",
.microvolts = 3300000,
.gpio = GPIO_PORT114,
.gpio = 114,
.enable_high = 1,
.init_data = &cn4_power_init_data,
};
......@@ -479,10 +481,10 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
static int power_gpio = -EINVAL;
if (power_gpio < 0) {
int ret = gpio_request_one(GPIO_PORT114, GPIOF_OUT_INIT_LOW,
int ret = gpio_request_one(114, GPIOF_OUT_INIT_LOW,
"sdhi1_power");
if (!ret)
power_gpio = GPIO_PORT114;
power_gpio = 114;
}
/*
......@@ -493,7 +495,7 @@ static void ag5evm_sdhi1_set_pwr(struct platform_device *pdev, int state)
* regulator driver. We have to live with the race in case the driver
* gets unloaded and the GPIO freed between these two steps.
*/
gpio_set_value(GPIO_PORT114, state);
gpio_set_value(114, state);
}
static struct sh_mobile_sdhi_info sh_sdhi1_info = {
......@@ -550,6 +552,77 @@ static struct platform_device *ag5evm_devices[] __initdata = {
&sdhi1_device,
};
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map ag5evm_pinctrl_map[] = {
/* FSIA */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_mclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_out", "fsia"),
/* I2C2 & I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.2", "pfc-sh73a0",
"i2c2_0", "i2c2"),
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_0", "i2c3"),
/* IrDA */
PIN_MAP_MUX_GROUP_DEFAULT("sh_irda.0", "pfc-sh73a0",
"irda_0", "irda"),
/* KEYSC */
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out04", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out5", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out6_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out7_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out8_0", "keysc"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_out9_2", "keysc"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_keysc.0", "pfc-sh73a0",
"keysc_in8", pin_pullup_conf),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_data_0", "scifa2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-sh73a0",
"scifa2_ctrl_0", "scifa2"),
/* SDHI0 (CN15 [SD I/F]) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_wp", "sdhi0"),
/* SDHI1 (CN4 [WLAN I/F]) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_ctrl", "sdhi1"),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"sdhi1_data4", pin_pullup_conf),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mobile_sdhi.1", "pfc-sh73a0",
"PORT263", pin_pullup_conf),
};
static void __init ag5evm_init(void)
{
regulator_register_always_on(0, "fixed-1.8V", fixed1v8_power_consumers,
......@@ -558,96 +631,27 @@ static void __init ag5evm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 3300000);
regulator_register_fixed(3, dummy_supplies, ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(ag5evm_pinctrl_map,
ARRAY_SIZE(ag5evm_pinctrl_map));
sh73a0_pinmux_init();
/* enable SCIFA2 */
gpio_request(GPIO_FN_SCIFA2_TXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RXD1, NULL);
gpio_request(GPIO_FN_SCIFA2_RTS1_, NULL);
gpio_request(GPIO_FN_SCIFA2_CTS1_, NULL);
/* enable KEYSC */
gpio_request(GPIO_FN_KEYIN0_PU, NULL);
gpio_request(GPIO_FN_KEYIN1_PU, NULL);
gpio_request(GPIO_FN_KEYIN2_PU, NULL);
gpio_request(GPIO_FN_KEYIN3_PU, NULL);
gpio_request(GPIO_FN_KEYIN4_PU, NULL);
gpio_request(GPIO_FN_KEYIN5_PU, NULL);
gpio_request(GPIO_FN_KEYIN6_PU, NULL);
gpio_request(GPIO_FN_KEYIN7_PU, NULL);
gpio_request(GPIO_FN_KEYOUT0, NULL);
gpio_request(GPIO_FN_KEYOUT1, NULL);
gpio_request(GPIO_FN_KEYOUT2, NULL);
gpio_request(GPIO_FN_KEYOUT3, NULL);
gpio_request(GPIO_FN_KEYOUT4, NULL);
gpio_request(GPIO_FN_KEYOUT5, NULL);
gpio_request(GPIO_FN_PORT59_KEYOUT6, NULL);
gpio_request(GPIO_FN_PORT58_KEYOUT7, NULL);
gpio_request(GPIO_FN_KEYOUT8, NULL);
gpio_request(GPIO_FN_PORT149_KEYOUT9, NULL);
/* enable I2C channel 2 and 3 */
gpio_request(GPIO_FN_PORT236_I2C_SDA2, NULL);
gpio_request(GPIO_FN_PORT237_I2C_SCL2, NULL);
gpio_request(GPIO_FN_PORT248_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT249_I2C_SDA3, NULL);
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
gpio_request_one(GPIO_PORT208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
gpio_request_one(208, GPIOF_OUT_INIT_HIGH, NULL); /* Reset */
/* enable SMSC911X */
gpio_request_one(GPIO_PORT144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(GPIO_PORT145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* FSI A */
gpio_request(GPIO_FN_FSIACK, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
/* IrDA */
gpio_request(GPIO_FN_PORT241_IRDA_OUT, NULL);
gpio_request(GPIO_FN_PORT242_IRDA_IN, NULL);
gpio_request(GPIO_FN_PORT243_IRDA_FIRSEL, NULL);
gpio_request_one(144, GPIOF_IN, NULL); /* PINTA2 */
gpio_request_one(145, GPIOF_OUT_INIT_HIGH, NULL); /* RESET */
/* LCD panel */
gpio_request_one(GPIO_PORT217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
gpio_request_one(217, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
mdelay(1);
gpio_set_value(GPIO_PORT217, 1);
gpio_set_value(217, 1);
mdelay(100);
/* LCD backlight controller */
gpio_request_one(GPIO_PORT235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
gpio_request_one(235, GPIOF_OUT_INIT_LOW, NULL); /* RESET */
lcd_backlight_set_brightness(0);
/* enable SDHI0 on CN15 [SD I/F] */
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
/* enable SDHI1 on CN4 [WLAN I/F] */
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHICMD1_PU, NULL);
gpio_request(GPIO_FN_SDHID1_3_PU, NULL);
gpio_request(GPIO_FN_SDHID1_2_PU, NULL);
gpio_request(GPIO_FN_SDHID1_1_PU, NULL);
gpio_request(GPIO_FN_SDHID1_0_PU, NULL);
#ifdef CONFIG_CACHE_L2X0
/* Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x00460000, 0xc2000fff);
......
arch/arm/mach-shmobile/board-ap4evb.c
View file @ 8f07b1d5
......@@ -34,6 +34,7 @@
#include <linux/i2c.h>
#include <linux/i2c/tsc2007.h>
#include <linux/io.h>
#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
......@@ -273,11 +274,11 @@ static struct platform_device smc911x_device = {
/*
* The card detect pin of the top SD/MMC slot (CN7) is active low and is
* connected to GPIO A22 of SH7372 (GPIO_PORT41).
* connected to GPIO A22 of SH7372 (GPIO 41).
*/
static int slot_cn7_get_cd(struct platform_device *pdev)
{
return !gpio_get_value(GPIO_PORT41);
return !gpio_get_value(41);
}
/* MERAM */
static struct sh_mobile_meram_info meram_info = {
......@@ -838,22 +839,22 @@ static struct platform_device fsi_hdmi_device = {
static struct gpio_led ap4evb_leds[] = {
{
.name = "led4",
.gpio = GPIO_PORT185,
.gpio = 185,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led2",
.gpio = GPIO_PORT186,
.gpio = 186,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led3",
.gpio = GPIO_PORT187,
.gpio = 187,
.default_state = LEDS_GPIO_DEFSTATE_ON,
},
{
.name = "led1",
.gpio = GPIO_PORT188,
.gpio = 188,
.default_state = LEDS_GPIO_DEFSTATE_ON,
}
};
......@@ -1026,10 +1027,10 @@ static void __init hdmi_init_pm_clock(void)
/* TouchScreen */
#ifdef CONFIG_AP4EVB_QHD
# define GPIO_TSC_IRQ GPIO_FN_IRQ28_123
# define GPIO_TSC_PORT GPIO_PORT123
# define GPIO_TSC_PORT 123
#else /* WVGA */
# define GPIO_TSC_IRQ GPIO_FN_IRQ7_40
# define GPIO_TSC_PORT GPIO_PORT40
# define GPIO_TSC_PORT 40
#endif
#define IRQ28 evt2irq(0x3380) /* IRQ28A */
......@@ -1084,6 +1085,28 @@ static struct i2c_board_info i2c1_devices[] = {
};
static const struct pinctrl_map ap4evb_pinctrl_map[] = {
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh7372",
"mmc0_ctrl_0", "mmc0"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh7372",
"sdhi0_wp", "sdhi0"),
/* SDHI1 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_data4", "sdhi1"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.1", "pfc-sh7372",
"sdhi1_ctrl", "sdhi1"),
};
#define GPIO_PORT9CR IOMEM(0xE6051009)
#define GPIO_PORT10CR IOMEM(0xE605100A)
#define USCCR1 IOMEM(0xE6058144)
......@@ -1110,6 +1133,8 @@ static void __init ap4evb_init(void)
/* External clock source */
clk_set_rate(&sh7372_dv_clki_clk, 27000000);
pinctrl_register_mappings(ap4evb_pinctrl_map,
ARRAY_SIZE(ap4evb_pinctrl_map));
sh7372_pinmux_init();
/* enable SCIFA0 */
......@@ -1121,40 +1146,10 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_IRQ6_39, NULL);
/* enable Debug switch (S6) */
gpio_request_one(GPIO_PORT32, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(GPIO_PORT33, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(GPIO_PORT34, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(GPIO_PORT35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* SDHI0 */
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
/* SDHI1 */
gpio_request(GPIO_FN_SDHICMD1, NULL);
gpio_request(GPIO_FN_SDHICLK1, NULL);
gpio_request(GPIO_FN_SDHID1_3, NULL);
gpio_request(GPIO_FN_SDHID1_2, NULL);
gpio_request(GPIO_FN_SDHID1_1, NULL);
gpio_request(GPIO_FN_SDHID1_0, NULL);
/* MMCIF */
gpio_request(GPIO_FN_MMCD0_0, NULL);
gpio_request(GPIO_FN_MMCD0_1, NULL);
gpio_request(GPIO_FN_MMCD0_2, NULL);
gpio_request(GPIO_FN_MMCD0_3, NULL);
gpio_request(GPIO_FN_MMCD0_4, NULL);
gpio_request(GPIO_FN_MMCD0_5, NULL);
gpio_request(GPIO_FN_MMCD0_6, NULL);
gpio_request(GPIO_FN_MMCD0_7, NULL);
gpio_request(GPIO_FN_MMCCMD0, NULL);
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request_one(32, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(33, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(34, GPIOF_IN | GPIOF_EXPORT, NULL);
gpio_request_one(35, GPIOF_IN | GPIOF_EXPORT, NULL);
/* USB enable */
gpio_request(GPIO_FN_VBUS0_1, NULL);
......@@ -1172,15 +1167,15 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
gpio_request_one(GPIO_PORT161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request_one(161, GPIOF_OUT_INIT_LOW, NULL); /* slave */
gpio_request(GPIO_PORT9, NULL);
gpio_request(GPIO_PORT10, NULL);
gpio_request(9, NULL);
gpio_request(10, NULL);
gpio_direction_none(GPIO_PORT9CR); /* FSIAOBT needs no direction */
gpio_direction_none(GPIO_PORT10CR); /* FSIAOLR needs no direction */
/* card detect pin for MMC slot (CN7) */
gpio_request_one(GPIO_PORT41, GPIOF_IN, NULL);
gpio_request_one(41, GPIOF_IN, NULL);
/* setup FSI2 port B (HDMI) */
gpio_request(GPIO_FN_FSIBCK, NULL);
......@@ -1268,8 +1263,8 @@ static void __init ap4evb_init(void)
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request_one(GPIO_PORT189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
gpio_request_one(GPIO_PORT151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
gpio_request_one(189, GPIOF_OUT_INIT_HIGH, NULL); /* backlight */
gpio_request_one(151, GPIOF_OUT_INIT_HIGH, NULL); /* LCDDON */
lcdc_info.clock_source = LCDC_CLK_BUS;
lcdc_info.ch[0].interface_type = RGB18;
......
arch/arm/mach-shmobile/board-bonito.c
View file @ 8f07b1d5
......@@ -24,6 +24,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/pinctrl/machine.h>
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/regulator/fixed.h>
......@@ -288,6 +289,16 @@ static struct platform_device lcdc0_device = {
},
};
static const struct pinctrl_map lcdc0_pinctrl_map[] = {
/* LCD0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_data24_1", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_lclk_1", "lcd0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-r8a7740",
"lcd0_sync", "lcd0"),
};
/*
* SMSC 9221
*/
......@@ -392,8 +403,8 @@ static void __init bonito_init(void)
/*
* base board settings
*/
gpio_request_one(GPIO_PORT176, GPIOF_IN, NULL);
if (!gpio_get_value(GPIO_PORT176)) {
gpio_request_one(176, GPIOF_IN, NULL);
if (!gpio_get_value(176)) {
u16 bsw2;
u16 bsw3;
u16 bsw4;
......@@ -430,38 +441,11 @@ static void __init bonito_init(void)
*/
if (BIT_ON(bsw2, 3) && /* S38.1 = OFF */
BIT_ON(bsw2, 2)) { /* S38.2 = OFF */
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request(GPIO_FN_LCD0_D0, NULL);
gpio_request(GPIO_FN_LCD0_D1, NULL);
gpio_request(GPIO_FN_LCD0_D2, NULL);
gpio_request(GPIO_FN_LCD0_D3, NULL);
gpio_request(GPIO_FN_LCD0_D4, NULL);
gpio_request(GPIO_FN_LCD0_D5, NULL);
gpio_request(GPIO_FN_LCD0_D6, NULL);
gpio_request(GPIO_FN_LCD0_D7, NULL);
gpio_request(GPIO_FN_LCD0_D8, NULL);
gpio_request(GPIO_FN_LCD0_D9, NULL);
gpio_request(GPIO_FN_LCD0_D10, NULL);
gpio_request(GPIO_FN_LCD0_D11, NULL);
gpio_request(GPIO_FN_LCD0_D12, NULL);
gpio_request(GPIO_FN_LCD0_D13, NULL);
gpio_request(GPIO_FN_LCD0_D14, NULL);
gpio_request(GPIO_FN_LCD0_D15, NULL);
gpio_request(GPIO_FN_LCD0_D16, NULL);
gpio_request(GPIO_FN_LCD0_D17, NULL);
gpio_request(GPIO_FN_LCD0_D18_PORT163, NULL);
gpio_request(GPIO_FN_LCD0_D19_PORT162, NULL);
gpio_request(GPIO_FN_LCD0_D20_PORT161, NULL);
gpio_request(GPIO_FN_LCD0_D21_PORT158, NULL);
gpio_request(GPIO_FN_LCD0_D22_PORT160, NULL);
gpio_request(GPIO_FN_LCD0_D23_PORT159, NULL);
gpio_request(GPIO_FN_LCD0_DCK, NULL);
gpio_request(GPIO_FN_LCD0_VSYN, NULL);
gpio_request(GPIO_FN_LCD0_HSYN, NULL);
gpio_request(GPIO_FN_LCD0_DISP, NULL);
gpio_request(GPIO_FN_LCD0_LCLK_PORT165, NULL);
gpio_request_one(GPIO_PORT61, GPIOF_OUT_INIT_HIGH,
pinctrl_register_mappings(lcdc0_pinctrl_map,
ARRAY_SIZE(lcdc0_pinctrl_map));
gpio_request(GPIO_FN_LCDC0_SELECT, NULL);
gpio_request_one(61, GPIOF_OUT_INIT_HIGH,
NULL); /* LCDDON */
/* backlight on */
......
arch/arm/mach-shmobile/board-kota2.c
View file @ 8f07b1d5
This diff is collapsed.
arch/arm/mach-shmobile/board-kzm9g-reference.c 0 → 100644
View file @ 8f07b1d5
/*
* KZM-A9-GT board support - Reference Device Tree Implementation
*
* Copyright (C) 2012 Horms Solutions Ltd.
*
* Based on board-kzm9g.c
* Copyright (C) 2012 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/delay.h>
#include <linux/gpio.h>
#include <linux/io.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/input.h>
#include <linux/of_platform.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <mach/sh73a0.h>
#include <mach/common.h>
#include <asm/hardware/cache-l2x0.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map kzm_pinctrl_map[] = {
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_1", "i2c3"),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA4 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_data", "scifa4"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_ctrl", "scifa4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_wp", "sdhi0"),
/* SDHI2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_ctrl", "sdhi2"),
};
static void __init kzm_init(void)
{
sh73a0_add_standard_devices_dt();
pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
sh73a0_pinmux_init();
/* enable SD */
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
l2x0_init(IOMEM(0xf0100000), 0x40460000, 0x82000fff);
#endif
}
static const char *kzm9g_boards_compat_dt[] __initdata = {
"renesas,kzm9g-reference",
NULL,
};
DT_MACHINE_START(KZM9G_DT, "kzm9g-reference")
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
.init_early = sh73a0_init_delay,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = irqchip_init,
.init_machine = kzm_init,
.init_time = shmobile_timer_init,
.dt_compat = kzm9g_boards_compat_dt,
MACHINE_END
arch/arm/mach-shmobile/board-kzm9g.c
View file @ 8f07b1d5
......@@ -30,6 +30,8 @@
#include <linux/mmc/sh_mmcif.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/pinctrl/machine.h>
#include <linux/pinctrl/pinconf-generic.h>
#include <linux/platform_device.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
......@@ -61,8 +63,8 @@
/* Dummy supplies, where voltage doesn't matter */
static struct regulator_consumer_supply dummy_supplies[] = {
REGULATOR_SUPPLY("vddvario", "smsc911x"),
REGULATOR_SUPPLY("vdd33a", "smsc911x"),
REGULATOR_SUPPLY("vddvario", "smsc911x.0"),
REGULATOR_SUPPLY("vdd33a", "smsc911x.0"),
};
/*
......@@ -433,7 +435,7 @@ static struct sh_mobile_sdhi_info sdhi2_info = {
TMIO_MMC_WRPROTECT_DISABLE,
.tmio_caps = MMC_CAP_SD_HIGHSPEED,
.tmio_ocr_mask = MMC_VDD_27_28 | MMC_VDD_28_29,
.cd_gpio = GPIO_PORT13,
.cd_gpio = 13,
};
static struct resource sdhi2_resources[] = {
......@@ -599,6 +601,64 @@ static struct platform_device *kzm_devices[] __initdata = {
&fsi_ak4648_device,
};
static unsigned long pin_pullup_conf[] = {
PIN_CONF_PACKED(PIN_CONFIG_BIAS_PULL_UP, 0),
};
static const struct pinctrl_map kzm_pinctrl_map[] = {
/* FSIA (AK4648) */
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_mclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_sclk_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_in", "fsia"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_fsi2.0", "pfc-sh73a0",
"fsia_data_out", "fsia"),
/* I2C3 */
PIN_MAP_MUX_GROUP_DEFAULT("i2c-sh_mobile.3", "pfc-sh73a0",
"i2c3_1", "i2c3"),
/* LCD */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_data24", "lcd"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_lcdc_fb.0", "pfc-sh73a0",
"lcd_sync", "lcd"),
/* MMCIF */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", "mmc0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_ctrl_0", "mmc0"),
PIN_MAP_CONFIGS_PIN_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"PORT279", pin_pullup_conf),
PIN_MAP_CONFIGS_GROUP_DEFAULT("sh_mmcif.0", "pfc-sh73a0",
"mmc0_data8_0", pin_pullup_conf),
/* SCIFA4 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_data", "scifa4"),
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-sh73a0",
"scifa4_ctrl", "scifa4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-sh73a0",
"sdhi0_wp", "sdhi0"),
/* SDHI2 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_data4", "sdhi2"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.2", "pfc-sh73a0",
"sdhi2_ctrl", "sdhi2"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x.0", "pfc-sh73a0",
"bsc_cs4", "bsc"),
/* USB */
PIN_MAP_MUX_GROUP_DEFAULT("renesas_usbhs", "pfc-sh73a0",
"usb_vbus", "usb"),
};
/*
* FIXME
*
......@@ -660,100 +720,26 @@ static void __init kzm_init(void)
ARRAY_SIZE(fixed2v8_power_consumers), 2800000);
regulator_register_fixed(2, dummy_supplies, ARRAY_SIZE(dummy_supplies));
sh73a0_pinmux_init();
/* enable SCIFA4 */
gpio_request(GPIO_FN_SCIFA4_TXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RXD, NULL);
gpio_request(GPIO_FN_SCIFA4_RTS_, NULL);
gpio_request(GPIO_FN_SCIFA4_CTS_, NULL);
pinctrl_register_mappings(kzm_pinctrl_map, ARRAY_SIZE(kzm_pinctrl_map));
/* CS4 for SMSC/USB */
gpio_request(GPIO_FN_CS4_, NULL); /* CS4 */
sh73a0_pinmux_init();
/* SMSC */
gpio_request_one(GPIO_PORT224, GPIOF_IN, NULL); /* IRQ3 */
gpio_request_one(224, GPIOF_IN, NULL); /* IRQ3 */
/* LCDC */
gpio_request(GPIO_FN_LCDD23, NULL);
gpio_request(GPIO_FN_LCDD22, NULL);
gpio_request(GPIO_FN_LCDD21, NULL);
gpio_request(GPIO_FN_LCDD20, NULL);
gpio_request(GPIO_FN_LCDD19, NULL);
gpio_request(GPIO_FN_LCDD18, NULL);
gpio_request(GPIO_FN_LCDD17, NULL);
gpio_request(GPIO_FN_LCDD16, NULL);
gpio_request(GPIO_FN_LCDD15, NULL);
gpio_request(GPIO_FN_LCDD14, NULL);
gpio_request(GPIO_FN_LCDD13, NULL);
gpio_request(GPIO_FN_LCDD12, NULL);
gpio_request(GPIO_FN_LCDD11, NULL);
gpio_request(GPIO_FN_LCDD10, NULL);
gpio_request(GPIO_FN_LCDD9, NULL);
gpio_request(GPIO_FN_LCDD8, NULL);
gpio_request(GPIO_FN_LCDD7, NULL);
gpio_request(GPIO_FN_LCDD6, NULL);
gpio_request(GPIO_FN_LCDD5, NULL);
gpio_request(GPIO_FN_LCDD4, NULL);
gpio_request(GPIO_FN_LCDD3, NULL);
gpio_request(GPIO_FN_LCDD2, NULL);
gpio_request(GPIO_FN_LCDD1, NULL);
gpio_request(GPIO_FN_LCDD0, NULL);
gpio_request(GPIO_FN_LCDDISP, NULL);
gpio_request(GPIO_FN_LCDDCK, NULL);
gpio_request_one(GPIO_PORT222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
gpio_request_one(GPIO_PORT226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
gpio_request_one(222, GPIOF_OUT_INIT_HIGH, NULL); /* LCDCDON */
gpio_request_one(226, GPIOF_OUT_INIT_HIGH, NULL); /* SC */
/* Touchscreen */
gpio_request_one(GPIO_PORT223, GPIOF_IN, NULL); /* IRQ8 */
/* enable MMCIF */
gpio_request(GPIO_FN_MMCCLK0, NULL);
gpio_request(GPIO_FN_MMCCMD0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_0_PU, NULL);
gpio_request(GPIO_FN_MMCD0_1_PU, NULL);
gpio_request(GPIO_FN_MMCD0_2_PU, NULL);
gpio_request(GPIO_FN_MMCD0_3_PU, NULL);
gpio_request(GPIO_FN_MMCD0_4_PU, NULL);
gpio_request(GPIO_FN_MMCD0_5_PU, NULL);
gpio_request(GPIO_FN_MMCD0_6_PU, NULL);
gpio_request(GPIO_FN_MMCD0_7_PU, NULL);
gpio_request_one(223, GPIOF_IN, NULL); /* IRQ8 */
/* enable SD */
gpio_request(GPIO_FN_SDHIWP0, NULL);
gpio_request(GPIO_FN_SDHICD0, NULL);
gpio_request(GPIO_FN_SDHICMD0, NULL);
gpio_request(GPIO_FN_SDHICLK0, NULL);
gpio_request(GPIO_FN_SDHID0_3, NULL);
gpio_request(GPIO_FN_SDHID0_2, NULL);
gpio_request(GPIO_FN_SDHID0_1, NULL);
gpio_request(GPIO_FN_SDHID0_0, NULL);
gpio_request(GPIO_FN_SDHI0_VCCQ_MC0_ON, NULL);
gpio_request_one(GPIO_PORT15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
gpio_request_one(15, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* enable Micro SD */
gpio_request(GPIO_FN_SDHID2_0, NULL);
gpio_request(GPIO_FN_SDHID2_1, NULL);
gpio_request(GPIO_FN_SDHID2_2, NULL);
gpio_request(GPIO_FN_SDHID2_3, NULL);
gpio_request(GPIO_FN_SDHICMD2, NULL);
gpio_request(GPIO_FN_SDHICLK2, NULL);
gpio_request_one(GPIO_PORT14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
/* I2C 3 */
gpio_request(GPIO_FN_PORT27_I2C_SCL3, NULL);
gpio_request(GPIO_FN_PORT28_I2C_SDA3, NULL);
/* enable FSI2 port A (ak4648) */
gpio_request(GPIO_FN_FSIACK, NULL);
gpio_request(GPIO_FN_FSIAILR, NULL);
gpio_request(GPIO_FN_FSIAIBT, NULL);
gpio_request(GPIO_FN_FSIAISLD, NULL);
gpio_request(GPIO_FN_FSIAOSLD, NULL);
/* enable USB */
gpio_request(GPIO_FN_VBUS_0, NULL);
gpio_request_one(14, GPIOF_OUT_INIT_HIGH, NULL); /* power */
#ifdef CONFIG_CACHE_L2X0
/* Early BRESP enable, Shared attribute override enable, 64K*8way */
......
arch/arm/mach-shmobile/board-mackerel.c
View file @ 8f07b1d5
This diff is collapsed.
arch/arm/mach-shmobile/board-marzen-reference.c 0 → 100644
View file @ 8f07b1d5
/*
* marzen board support - Reference DT implementation
*
* Copyright (C) 2011 Renesas Solutions Corp.
* Copyright (C) 2011 Magnus Damm
* Copyright (C) 2013 Simon Horman
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <linux/pinctrl/machine.h>
#include <mach/r8a7779.h>
#include <mach/common.h>
#include <mach/irqs.h>
#include <asm/irq.h>
#include <asm/mach/arch.h>
static const struct pinctrl_map marzen_pinctrl_map[] = {
/* SCIF2 (CN18: DEBUG0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
"scif2_data_c", "scif2"),
/* SCIF4 (CN19: DEBUG1) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
"scif4_data", "scif4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_wp", "sdhi0"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"intc_irq1_b", "intc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"lbsc_ex_cs0", "lbsc"),
};
static void __init marzen_init(void)
{
pinctrl_register_mappings(marzen_pinctrl_map,
ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
r8a7779_add_standard_devices_dt();
}
static const char *marzen_boards_compat_dt[] __initdata = {
"renesas,marzen-reference",
NULL,
};
DT_MACHINE_START(MARZEN, "marzen")
.smp = smp_ops(r8a7779_smp_ops),
.map_io = r8a7779_map_io,
.init_early = r8a7779_init_delay,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = r8a7779_init_irq_dt,
.init_machine = marzen_init,
.init_time = shmobile_timer_init,
.dt_compat = marzen_boards_compat_dt,
MACHINE_END
arch/arm/mach-shmobile/board-marzen.c
View file @ 8f07b1d5
......@@ -25,13 +25,14 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/gpio.h>
#include <linux/dma-mapping.h>
#include <linux/pinctrl/machine.h>
#include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h>
#include <linux/smsc911x.h>
#include <linux/spi/spi.h>
#include <linux/spi/sh_hspi.h>
#include <linux/mmc/host.h>
#include <linux/mmc/sh_mobile_sdhi.h>
#include <linux/mfd/tmio.h>
#include <linux/usb/otg.h>
......@@ -66,7 +67,7 @@ static struct resource smsc911x_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(28), /* IRQ 1 */
.start = gic_iid(0x3c), /* IRQ 1 */
.flags = IORESOURCE_IRQ,
},
};
......@@ -96,7 +97,7 @@ static struct resource sdhi0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(104),
.start = gic_iid(0x88),
.flags = IORESOURCE_IRQ,
},
};
......@@ -214,7 +215,7 @@ static struct resource ehci0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(44),
.start = gic_iid(0x4c),
.flags = IORESOURCE_IRQ,
},
};
......@@ -238,7 +239,7 @@ static struct resource ehci1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(45),
.start = gic_iid(0x4d),
.flags = IORESOURCE_IRQ,
},
};
......@@ -268,7 +269,7 @@ static struct resource ohci0_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(44),
.start = gic_iid(0x4c),
.flags = IORESOURCE_IRQ,
},
};
......@@ -292,7 +293,7 @@ static struct resource ohci1_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(45),
.start = gic_iid(0x4d),
.flags = IORESOURCE_IRQ,
},
};
......@@ -326,6 +327,41 @@ void __init marzen_init_late(void)
ARRAY_SIZE(marzen_late_devices));
}
static const struct pinctrl_map marzen_pinctrl_map[] = {
/* HSPI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh-hspi.0", "pfc-r8a7779",
"hspi0", "hspi0"),
/* SCIF2 (CN18: DEBUG0) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.2", "pfc-r8a7779",
"scif2_data_c", "scif2"),
/* SCIF4 (CN19: DEBUG1) */
PIN_MAP_MUX_GROUP_DEFAULT("sh-sci.4", "pfc-r8a7779",
"scif4_data", "scif4"),
/* SDHI0 */
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_data4", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_ctrl", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_cd", "sdhi0"),
PIN_MAP_MUX_GROUP_DEFAULT("sh_mobile_sdhi.0", "pfc-r8a7779",
"sdhi0_wp", "sdhi0"),
/* SMSC */
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"intc_irq1_b", "intc"),
PIN_MAP_MUX_GROUP_DEFAULT("smsc911x", "pfc-r8a7779",
"lbsc_ex_cs0", "lbsc"),
/* USB0 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
"usb0", "usb0"),
/* USB1 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.0", "pfc-r8a7779",
"usb1", "usb1"),
/* USB2 */
PIN_MAP_MUX_GROUP_DEFAULT("ehci-platform.1", "pfc-r8a7779",
"usb2", "usb2"),
};
static void __init marzen_init(void)
{
regulator_register_always_on(0, "fixed-3.3V", fixed3v3_power_consumers,
......@@ -333,44 +369,10 @@ static void __init marzen_init(void)
regulator_register_fixed(1, dummy_supplies,
ARRAY_SIZE(dummy_supplies));
pinctrl_register_mappings(marzen_pinctrl_map,
ARRAY_SIZE(marzen_pinctrl_map));
r8a7779_pinmux_init();
/* SCIF2 (CN18: DEBUG0) */
gpio_request(GPIO_FN_TX2_C, NULL);
gpio_request(GPIO_FN_RX2_C, NULL);
/* SCIF4 (CN19: DEBUG1) */
gpio_request(GPIO_FN_TX4, NULL);
gpio_request(GPIO_FN_RX4, NULL);
/* LAN89218 */
gpio_request(GPIO_FN_EX_CS0, NULL); /* nCS */
gpio_request(GPIO_FN_IRQ1_B, NULL); /* IRQ + PME */
/* SD0 (CN20) */
gpio_request(GPIO_FN_SD0_CLK, NULL);
gpio_request(GPIO_FN_SD0_CMD, NULL);
gpio_request(GPIO_FN_SD0_DAT0, NULL);
gpio_request(GPIO_FN_SD0_DAT1, NULL);
gpio_request(GPIO_FN_SD0_DAT2, NULL);
gpio_request(GPIO_FN_SD0_DAT3, NULL);
gpio_request(GPIO_FN_SD0_CD, NULL);
gpio_request(GPIO_FN_SD0_WP, NULL);
/* HSPI 0 */
gpio_request(GPIO_FN_HSPI_CLK0, NULL);
gpio_request(GPIO_FN_HSPI_CS0, NULL);
gpio_request(GPIO_FN_HSPI_TX0, NULL);
gpio_request(GPIO_FN_HSPI_RX0, NULL);
/* USB (CN21) */
gpio_request(GPIO_FN_USB_OVC0, NULL);
gpio_request(GPIO_FN_USB_OVC1, NULL);
gpio_request(GPIO_FN_USB_OVC2, NULL);
/* USB (CN22) */
gpio_request(GPIO_FN_USB_PENC2, NULL);
r8a7779_add_standard_devices();
platform_add_devices(marzen_devices, ARRAY_SIZE(marzen_devices));
}
......
arch/arm/mach-shmobile/clock-r8a7740.c
View file @ 8f07b1d5
......@@ -593,29 +593,42 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_mobile_ceu.1", &mstp_clks[MSTP128]),
CLKDEV_DEV_ID("sh-sci.4", &mstp_clks[MSTP200]),
CLKDEV_DEV_ID("e6c80000.sci", &mstp_clks[MSTP200]),
CLKDEV_DEV_ID("sh-sci.3", &mstp_clks[MSTP201]),
CLKDEV_DEV_ID("e6c70000.sci", &mstp_clks[MSTP201]),
CLKDEV_DEV_ID("sh-sci.2", &mstp_clks[MSTP202]),
CLKDEV_DEV_ID("e6c60000.sci", &mstp_clks[MSTP202]),
CLKDEV_DEV_ID("sh-sci.1", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("e6c50000.sci", &mstp_clks[MSTP203]),
CLKDEV_DEV_ID("sh-sci.0", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("e6c40000.sci", &mstp_clks[MSTP204]),
CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP206]),
CLKDEV_DEV_ID("e6c30000.sci", &mstp_clks[MSTP206]),
CLKDEV_DEV_ID("sh-sci.5", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("e6cb0000.sci", &mstp_clks[MSTP207]),
CLKDEV_DEV_ID("sh-dma-engine.3", &mstp_clks[MSTP214]),
CLKDEV_DEV_ID("sh-dma-engine.2", &mstp_clks[MSTP216]),
CLKDEV_DEV_ID("sh-dma-engine.1", &mstp_clks[MSTP217]),
CLKDEV_DEV_ID("sh-dma-engine.0", &mstp_clks[MSTP218]),
CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP222]),
CLKDEV_DEV_ID("e6cd0000.sci", &mstp_clks[MSTP222]),
CLKDEV_DEV_ID("sh-sci.6", &mstp_clks[MSTP230]),
CLKDEV_DEV_ID("e6cc0000.sci", &mstp_clks[MSTP230]),
CLKDEV_DEV_ID("sh_cmt.10", &mstp_clks[MSTP329]),
CLKDEV_DEV_ID("sh_fsi2", &mstp_clks[MSTP328]),
CLKDEV_DEV_ID("i2c-sh_mobile.1", &mstp_clks[MSTP323]),
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP320]),
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("e6850000.sdhi", &mstp_clks[MSTP314]),
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("e6860000.sdhi", &mstp_clks[MSTP313]),
CLKDEV_DEV_ID("sh_mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
CLKDEV_DEV_ID("sh-eth", &mstp_clks[MSTP309]),
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
/* ICK */
CLKDEV_ICK_ID("host", "renesas_usbhs", &mstp_clks[MSTP416]),
......
arch/arm/mach-shmobile/clock-r8a7779.c
View file @ 8f07b1d5
......@@ -87,7 +87,8 @@ static struct clk div4_clks[DIV4_NR] = {
};
enum { MSTP323, MSTP322, MSTP321, MSTP320,
MSTP101, MSTP100,
MSTP115,
MSTP103, MSTP101, MSTP100,
MSTP030,
MSTP029, MSTP028, MSTP027, MSTP026, MSTP025, MSTP024, MSTP023, MSTP022, MSTP021,
MSTP016, MSTP015, MSTP014,
......@@ -99,6 +100,8 @@ static struct clk mstp_clks[MSTP_NR] = {
[MSTP322] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 22, 0), /* SDHI1 */
[MSTP321] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 21, 0), /* SDHI2 */
[MSTP320] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR3, 20, 0), /* SDHI3 */
[MSTP115] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 15, 0), /* SATA */
[MSTP103] = SH_CLK_MSTP32(&div4_clks[DIV4_S], MSTPCR1, 3, 0), /* DU */
[MSTP101] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 1, 0), /* USB2 */
[MSTP100] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR1, 0, 0), /* USB0/1 */
[MSTP030] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 30, 0), /* I2C0 */
......@@ -156,6 +159,8 @@ static struct clk_lookup lookups[] = {
CLKDEV_CON_ID("peripheral_clk", &div4_clks[DIV4_P]),
/* MSTP32 clocks */
CLKDEV_DEV_ID("sata_rcar", &mstp_clks[MSTP115]), /* SATA */
CLKDEV_DEV_ID("fc600000.sata", &mstp_clks[MSTP115]), /* SATA w/DT */
CLKDEV_DEV_ID("ehci-platform.1", &mstp_clks[MSTP101]), /* USB EHCI port2 */
CLKDEV_DEV_ID("ohci-platform.1", &mstp_clks[MSTP101]), /* USB OHCI port2 */
CLKDEV_DEV_ID("ehci-platform.0", &mstp_clks[MSTP100]), /* USB EHCI port0/1 */
......@@ -180,6 +185,7 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP322]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP321]), /* SDHI2 */
CLKDEV_DEV_ID("sh_mobile_sdhi.3", &mstp_clks[MSTP320]), /* SDHI3 */
CLKDEV_DEV_ID("rcar-du.0", &mstp_clks[MSTP103]), /* DU */
};
void __init r8a7779_clock_init(void)
......
arch/arm/mach-shmobile/clock-sh73a0.c
View file @ 8f07b1d5
......@@ -265,12 +265,12 @@ enum { DIV4_I, DIV4_ZG, DIV4_M3, DIV4_B, DIV4_M1, DIV4_M2,
static struct clk div4_clks[DIV4_NR] = {
[DIV4_I] = DIV4(FRQCRA, 20, 0xdff, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = DIV4(FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
[DIV4_ZG] = SH_CLK_DIV4(&pll0_clk, FRQCRA, 16, 0xd7f, CLK_ENABLE_ON_INIT),
[DIV4_M3] = DIV4(FRQCRA, 12, 0x1dff, CLK_ENABLE_ON_INIT),
[DIV4_B] = DIV4(FRQCRA, 8, 0xdff, CLK_ENABLE_ON_INIT),
[DIV4_M1] = DIV4(FRQCRA, 4, 0x1dff, 0),
[DIV4_M2] = DIV4(FRQCRA, 0, 0x1dff, 0),
[DIV4_Z] = DIV4(FRQCRB, 24, 0x97f, 0),
[DIV4_Z] = SH_CLK_DIV4(&pll0_clk, FRQCRB, 24, 0x97f, 0),
[DIV4_ZTR] = DIV4(FRQCRB, 20, 0xdff, 0),
[DIV4_ZT] = DIV4(FRQCRB, 16, 0xdff, 0),
[DIV4_ZX] = DIV4(FRQCRB, 12, 0xdff, 0),
......@@ -581,10 +581,13 @@ static struct clk_lookup lookups[] = {
CLKDEV_DEV_ID("e6822000.i2c", &mstp_clks[MSTP323]), /* I2C1 */
CLKDEV_DEV_ID("renesas_usbhs", &mstp_clks[MSTP322]), /* USB */
CLKDEV_DEV_ID("sh_mobile_sdhi.0", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("ee100000.sdhi", &mstp_clks[MSTP314]), /* SDHI0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.1", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("ee120000.sdhi", &mstp_clks[MSTP313]), /* SDHI1 */
CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP312]), /* MMCIF0 */
CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]), /* MMCIF0 */
CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP311]), /* SDHI2 */
CLKDEV_DEV_ID("ee140000.sdhi", &mstp_clks[MSTP311]), /* SDHI2 */
CLKDEV_DEV_ID("leds-renesas-tpu.12", &mstp_clks[MSTP303]), /* TPU1 */
CLKDEV_DEV_ID("leds-renesas-tpu.21", &mstp_clks[MSTP302]), /* TPU2 */
CLKDEV_DEV_ID("leds-renesas-tpu.30", &mstp_clks[MSTP301]), /* TPU3 */
......
arch/arm/mach-shmobile/headsmp-sh73a0.S → arch/arm/mach-shmobile/headsmp-scu.S
View file @ 8f07b1d5
/*
* SMP support for SoC sh73a0
* Shared SCU setup for mach-shmobile
*
* Copyright (C) 2012 Bastian Hecht
*
......@@ -35,11 +35,12 @@
* the physical address as the MMU is still turned off.
*/
.align 12
ENTRY(sh73a0_secondary_vector)
ENTRY(shmobile_secondary_vector_scu)
mrc p15, 0, r0, c0, c0, 5 @ read MIPDR
and r0, r0, #3 @ mask out cpu ID
lsl r0, r0, #3 @ we will shift by cpu_id * 8 bits
mov r1, #0xf0000000 @ SCU base address
ldr r1, 2f
ldr r1, [r1] @ SCU base address
ldr r2, [r1, #8] @ SCU Power Status Register
mov r3, #3
bic r2, r2, r3, lsl r0 @ Clear bits of our CPU (Run Mode)
......@@ -47,4 +48,10 @@ ENTRY(sh73a0_secondary_vector)
ldr pc, 1f
1: .long shmobile_invalidate_start - PAGE_OFFSET + PLAT_PHYS_OFFSET
ENDPROC(sh73a0_secondary_vector)
2: .long shmobile_scu_base - PAGE_OFFSET + PLAT_PHYS_OFFSET
ENDPROC(shmobile_secondary_vector_scu)
.text
.globl shmobile_scu_base
shmobile_scu_base:
.space 4
arch/arm/mach-shmobile/hotplug.c deleted 100644 → 0
View file @ f6161aa1
/*
* SMP support for R-Mobile / SH-Mobile
*
* Copyright (C) 2010 Magnus Damm
*
* Based on realview, Copyright (C) 2002 ARM Ltd, All Rights Reserved
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/errno.h>
#include <linux/smp.h>
#include <linux/cpumask.h>
#include <linux/delay.h>
#include <linux/of.h>
#include <mach/common.h>
#include <mach/r8a7779.h>
#include <mach/emev2.h>
#include <asm/cacheflush.h>
#include <asm/mach-types.h>
static cpumask_t dead_cpus;
void shmobile_cpu_die(unsigned int cpu)
{
/* hardware shutdown code running on the CPU that is being offlined */
flush_cache_all();
dsb();
/* notify platform_cpu_kill() that hardware shutdown is finished */
cpumask_set_cpu(cpu, &dead_cpus);
/* wait for SoC code in platform_cpu_kill() to shut off CPU core
* power. CPU bring up starts from the reset vector.
*/
while (1) {
/*
* here's the WFI
*/
asm(".word 0xe320f003\n"
:
:
: "memory", "cc");
}
}
int shmobile_cpu_disable(unsigned int cpu)
{
cpumask_clear_cpu(cpu, &dead_cpus);
/*
* we don't allow CPU 0 to be shutdown (it is still too special
* e.g. clock tick interrupts)
*/
return cpu == 0 ? -EPERM : 0;
}
int shmobile_cpu_disable_any(unsigned int cpu)
{
cpumask_clear_cpu(cpu, &dead_cpus);
return 0;
}
int shmobile_cpu_is_dead(unsigned int cpu)
{
return cpumask_test_cpu(cpu, &dead_cpus);
}
arch/arm/mach-shmobile/include/mach/common.h
View file @ 8f07b1d5
......@@ -8,6 +8,7 @@ extern void shmobile_setup_delay(unsigned int max_cpu_core_mhz,
struct twd_local_timer;
extern void shmobile_setup_console(void);
extern void shmobile_secondary_vector(void);
extern void shmobile_secondary_vector_scu(void);
struct clk;
extern int shmobile_clk_init(void);
extern void shmobile_handle_irq_intc(struct pt_regs *);
......@@ -33,23 +34,23 @@ extern int sh7372_do_idle_sysc(unsigned long sleep_mode);
extern struct clk sh7372_extal1_clk;
extern struct clk sh7372_extal2_clk;
extern void sh73a0_init_delay(void);
extern void sh73a0_init_irq(void);
extern void sh73a0_init_irq_dt(void);
extern void sh73a0_map_io(void);
extern void sh73a0_earlytimer_init(void);
extern void sh73a0_add_early_devices(void);
extern void sh73a0_add_early_devices_dt(void);
extern void sh73a0_add_standard_devices(void);
extern void sh73a0_add_standard_devices_dt(void);
extern void sh73a0_clock_init(void);
extern void sh73a0_pinmux_init(void);
extern void sh73a0_pm_init(void);
extern void sh73a0_secondary_vector(void);
extern struct clk sh73a0_extal1_clk;
extern struct clk sh73a0_extal2_clk;
extern struct clk sh73a0_extcki_clk;
extern struct clk sh73a0_extalr_clk;
extern void r8a7740_meram_workaround(void);
extern void r8a7740_init_irq(void);
extern void r8a7740_map_io(void);
extern void r8a7740_add_early_devices(void);
......@@ -58,16 +59,17 @@ extern void r8a7740_clock_init(u8 md_ck);
extern void r8a7740_pinmux_init(void);
extern void r8a7740_pm_init(void);
extern void r8a7779_init_delay(void);
extern void r8a7779_init_irq(void);
extern void r8a7779_init_irq_dt(void);
extern void r8a7779_map_io(void);
extern void r8a7779_earlytimer_init(void);
extern void r8a7779_add_early_devices(void);
extern void r8a7779_add_standard_devices(void);
extern void r8a7779_add_standard_devices_dt(void);
extern void r8a7779_clock_init(void);
extern void r8a7779_pinmux_init(void);
extern void r8a7779_pm_init(void);
extern void r8a7740_meram_workaround(void);
extern void r8a7779_register_twd(void);
#ifdef CONFIG_SUSPEND
......@@ -82,16 +84,7 @@ int shmobile_cpuidle_init(void);
static inline int shmobile_cpuidle_init(void) { return 0; }
#endif
extern void shmobile_cpu_die(unsigned int cpu);
extern int shmobile_cpu_disable(unsigned int cpu);
extern int shmobile_cpu_disable_any(unsigned int cpu);
#ifdef CONFIG_HOTPLUG_CPU
extern int shmobile_cpu_is_dead(unsigned int cpu);
#else
static inline int shmobile_cpu_is_dead(unsigned int cpu) { return 1; }
#endif
extern void __iomem *shmobile_scu_base;
extern void shmobile_smp_init_cpus(unsigned int ncores);
static inline void __init shmobile_init_late(void)
......
arch/arm/mach-shmobile/include/mach/irqs.h
View file @ 8f07b1d5
......@@ -5,6 +5,7 @@
/* GIC */
#define gic_spi(nr) ((nr) + 32)
#define gic_iid(nr) (nr) /* ICCIAR / interrupt ID */
/* INTCS */
#define INTCS_VECT_BASE 0x3400
......
arch/arm/mach-shmobile/include/mach/r8a7740.h
View file @ 8f07b1d5
......@@ -241,48 +241,9 @@ enum {
/* LCD0 */
GPIO_FN_LCDC0_SELECT,
GPIO_FN_LCD0_D0, GPIO_FN_LCD0_D1, GPIO_FN_LCD0_D2,
GPIO_FN_LCD0_D3, GPIO_FN_LCD0_D4, GPIO_FN_LCD0_D5,
GPIO_FN_LCD0_D6, GPIO_FN_LCD0_D7, GPIO_FN_LCD0_D8,
GPIO_FN_LCD0_D9, GPIO_FN_LCD0_D10, GPIO_FN_LCD0_D11,
GPIO_FN_LCD0_D12, GPIO_FN_LCD0_D13, GPIO_FN_LCD0_D14,
GPIO_FN_LCD0_D15, GPIO_FN_LCD0_D16, GPIO_FN_LCD0_D17,
GPIO_FN_LCD0_DON, GPIO_FN_LCD0_VCPWC, GPIO_FN_LCD0_VEPWC,
GPIO_FN_LCD0_DCK, GPIO_FN_LCD0_VSYN, /* for RGB */
GPIO_FN_LCD0_HSYN, GPIO_FN_LCD0_DISP, /* for RGB */
GPIO_FN_LCD0_WR, GPIO_FN_LCD0_RD, /* for SYS */
GPIO_FN_LCD0_CS, GPIO_FN_LCD0_RS, /* for SYS */
GPIO_FN_LCD0_D18_PORT163, GPIO_FN_LCD0_D19_PORT162,
GPIO_FN_LCD0_D20_PORT161, GPIO_FN_LCD0_D21_PORT158,
GPIO_FN_LCD0_D22_PORT160, GPIO_FN_LCD0_D23_PORT159,
GPIO_FN_LCD0_LCLK_PORT165, /* MSEL5CR_6_1 */
GPIO_FN_LCD0_D18_PORT40, GPIO_FN_LCD0_D19_PORT4,
GPIO_FN_LCD0_D20_PORT3, GPIO_FN_LCD0_D21_PORT2,
GPIO_FN_LCD0_D22_PORT0, GPIO_FN_LCD0_D23_PORT1,
GPIO_FN_LCD0_LCLK_PORT102, /* MSEL5CR_6_0 */
/* LCD1 */
GPIO_FN_LCDC1_SELECT,
GPIO_FN_LCD1_D0, GPIO_FN_LCD1_D1, GPIO_FN_LCD1_D2,
GPIO_FN_LCD1_D3, GPIO_FN_LCD1_D4, GPIO_FN_LCD1_D5,
GPIO_FN_LCD1_D6, GPIO_FN_LCD1_D7, GPIO_FN_LCD1_D8,
GPIO_FN_LCD1_D9, GPIO_FN_LCD1_D10, GPIO_FN_LCD1_D11,
GPIO_FN_LCD1_D12, GPIO_FN_LCD1_D13, GPIO_FN_LCD1_D14,
GPIO_FN_LCD1_D15, GPIO_FN_LCD1_D16, GPIO_FN_LCD1_D17,
GPIO_FN_LCD1_D18, GPIO_FN_LCD1_D19, GPIO_FN_LCD1_D20,
GPIO_FN_LCD1_D21, GPIO_FN_LCD1_D22, GPIO_FN_LCD1_D23,
GPIO_FN_LCD1_DON, GPIO_FN_LCD1_VCPWC,
GPIO_FN_LCD1_LCLK, GPIO_FN_LCD1_VEPWC,
GPIO_FN_LCD1_DCK, GPIO_FN_LCD1_VSYN, /* for RGB */
GPIO_FN_LCD1_HSYN, GPIO_FN_LCD1_DISP, /* for RGB */
GPIO_FN_LCD1_WR, GPIO_FN_LCD1_RD, /* for SYS */
GPIO_FN_LCD1_CS, GPIO_FN_LCD1_RS, /* for SYS */
/* RSPI */
GPIO_FN_RSPI_SSL0_A, GPIO_FN_RSPI_SSL1_A,
......@@ -346,26 +307,6 @@ enum {
GPIO_FN_SIM_D_PORT22, /* SIM_D Port 22/199 */
GPIO_FN_SIM_D_PORT199,
/* SDHI0 */
GPIO_FN_SDHI0_D0, GPIO_FN_SDHI0_D1, GPIO_FN_SDHI0_D2,
GPIO_FN_SDHI0_D3, GPIO_FN_SDHI0_CD, GPIO_FN_SDHI0_WP,
GPIO_FN_SDHI0_CMD, GPIO_FN_SDHI0_CLK,
/* SDHI1 */
GPIO_FN_SDHI1_D0, GPIO_FN_SDHI1_D1, GPIO_FN_SDHI1_D2,
GPIO_FN_SDHI1_D3, GPIO_FN_SDHI1_CD, GPIO_FN_SDHI1_WP,
GPIO_FN_SDHI1_CMD, GPIO_FN_SDHI1_CLK,
/* SDHI2 */
GPIO_FN_SDHI2_D0, GPIO_FN_SDHI2_D1, GPIO_FN_SDHI2_D2,
GPIO_FN_SDHI2_D3, GPIO_FN_SDHI2_CLK, GPIO_FN_SDHI2_CMD,
GPIO_FN_SDHI2_CD_PORT24, /* MSEL5CR_19_0 */
GPIO_FN_SDHI2_WP_PORT25,
GPIO_FN_SDHI2_WP_PORT177, /* MSEL5CR_19_1 */
GPIO_FN_SDHI2_CD_PORT202,
/* MSIOF2 */
GPIO_FN_MSIOF2_TXD, GPIO_FN_MSIOF2_RXD, GPIO_FN_MSIOF2_TSCK,
GPIO_FN_MSIOF2_SS2, GPIO_FN_MSIOF2_TSYNC, GPIO_FN_MSIOF2_SS1,
......@@ -417,21 +358,6 @@ enum {
GPIO_FN_MEMC_DREQ1,
GPIO_FN_MEMC_A0,
/* MMC */
GPIO_FN_MMC0_D0_PORT68, GPIO_FN_MMC0_D1_PORT69,
GPIO_FN_MMC0_D2_PORT70, GPIO_FN_MMC0_D3_PORT71,
GPIO_FN_MMC0_D4_PORT72, GPIO_FN_MMC0_D5_PORT73,
GPIO_FN_MMC0_D6_PORT74, GPIO_FN_MMC0_D7_PORT75,
GPIO_FN_MMC0_CLK_PORT66,
GPIO_FN_MMC0_CMD_PORT67, /* MSEL4CR_15_0 */
GPIO_FN_MMC1_D0_PORT149, GPIO_FN_MMC1_D1_PORT148,
GPIO_FN_MMC1_D2_PORT147, GPIO_FN_MMC1_D3_PORT146,
GPIO_FN_MMC1_D4_PORT145, GPIO_FN_MMC1_D5_PORT144,
GPIO_FN_MMC1_D6_PORT143, GPIO_FN_MMC1_D7_PORT142,
GPIO_FN_MMC1_CLK_PORT103,
GPIO_FN_MMC1_CMD_PORT104, /* MSEL4CR_15_1 */
/* MSIOF0 */
GPIO_FN_MSIOF0_SS1, GPIO_FN_MSIOF0_SS2,
GPIO_FN_MSIOF0_RXD, GPIO_FN_MSIOF0_TXD,
......
arch/arm/mach-shmobile/include/mach/sh7372.h
View file @ 8f07b1d5
......@@ -294,21 +294,6 @@ enum {
GPIO_FN_D12_NAF12, GPIO_FN_D13_NAF13, GPIO_FN_D14_NAF14,
GPIO_FN_D15_NAF15,
/*
* MMCIF(1) (PORT 84, 85, 86, 87, 88, 89,
* 90, 91, 92, 99)
*/
GPIO_FN_MMCD0_0, GPIO_FN_MMCD0_1, GPIO_FN_MMCD0_2,
GPIO_FN_MMCD0_3, GPIO_FN_MMCD0_4, GPIO_FN_MMCD0_5,
GPIO_FN_MMCD0_6, GPIO_FN_MMCD0_7,
GPIO_FN_MMCCMD0, GPIO_FN_MMCCLK0,
/* MMCIF(2) (PORT 54, 55, 56, 57, 58, 59, 60, 61, 66, 67) */
GPIO_FN_MMCD1_0, GPIO_FN_MMCD1_1, GPIO_FN_MMCD1_2,
GPIO_FN_MMCD1_3, GPIO_FN_MMCD1_4, GPIO_FN_MMCD1_5,
GPIO_FN_MMCD1_6, GPIO_FN_MMCD1_7,
GPIO_FN_MMCCLK1, GPIO_FN_MMCCMD1,
/* SPU2 (PORT 65) */
GPIO_FN_VINT_I,
......@@ -416,20 +401,6 @@ enum {
/* HDMI (PORT 169, 170) */
GPIO_FN_HDMI_HPD, GPIO_FN_HDMI_CEC,
/* SDHI0 (PORT 171, 172, 173, 174, 175, 176, 177, 178) */
GPIO_FN_SDHICLK0, GPIO_FN_SDHICD0,
GPIO_FN_SDHICMD0, GPIO_FN_SDHIWP0,
GPIO_FN_SDHID0_0, GPIO_FN_SDHID0_1,
GPIO_FN_SDHID0_2, GPIO_FN_SDHID0_3,
/* SDHI1 (PORT 179, 180, 181, 182, 183, 184) */
GPIO_FN_SDHICLK1, GPIO_FN_SDHICMD1, GPIO_FN_SDHID1_0,
GPIO_FN_SDHID1_1, GPIO_FN_SDHID1_2, GPIO_FN_SDHID1_3,
/* SDHI2 (PORT 185, 186, 187, 188, 189, 190) */
GPIO_FN_SDHICLK2, GPIO_FN_SDHICMD2, GPIO_FN_SDHID2_0,
GPIO_FN_SDHID2_1, GPIO_FN_SDHID2_2, GPIO_FN_SDHID2_3,
/* SDENC see MSEL4CR 19 */
GPIO_FN_SDENC_CPG,
GPIO_FN_SDENC_DV_CLKI,
......
arch/arm/mach-shmobile/intc-r8a7779.c
View file @ 8f07b1d5
......@@ -24,6 +24,7 @@
#include <linux/io.h>
#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <linux/irqchip.h>
#include <mach/intc.h>
#include <mach/r8a7779.h>
#include <asm/mach-types.h>
......@@ -43,13 +44,8 @@ static int r8a7779_set_wake(struct irq_data *data, unsigned int on)
return 0; /* always allow wakeup */
}
void __init r8a7779_init_irq(void)
static void __init r8a7779_init_irq_common(void)
{
void __iomem *gic_dist_base = IOMEM(0xf0001000);
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
/* use GIC to handle interrupts */
gic_init(0, 29, gic_dist_base, gic_cpu_base);
gic_arch_extn.irq_set_wake = r8a7779_set_wake;
/* route all interrupts to ARM */
......@@ -63,3 +59,22 @@ void __init r8a7779_init_irq(void)
__raw_writel(0xbffffffc, INT2SMSKCR3);
__raw_writel(0x003fee3f, INT2SMSKCR4);
}
void __init r8a7779_init_irq(void)
{
void __iomem *gic_dist_base = IOMEM(0xf0001000);
void __iomem *gic_cpu_base = IOMEM(0xf0000100);
/* use GIC to handle interrupts */
gic_init(0, 29, gic_dist_base, gic_cpu_base);
r8a7779_init_irq_common();
}
#ifdef CONFIG_OF
void __init r8a7779_init_irq_dt(void)
{
irqchip_init();
r8a7779_init_irq_common();
}
#endif
arch/arm/mach-shmobile/intc-sh73a0.c
View file @ 8f07b1d5
......@@ -460,11 +460,3 @@ void __init sh73a0_init_irq(void)
sh73a0_pint1_cascade.handler = sh73a0_pint1_demux;
setup_irq(gic_spi(34), &sh73a0_pint1_cascade);
}
#ifdef CONFIG_OF
void __init sh73a0_init_irq_dt(void)
{
irqchip_init();
gic_arch_extn.irq_set_wake = sh73a0_set_wake;
}
#endif
arch/arm/mach-shmobile/setup-emev2.c
View file @ 8f07b1d5
......@@ -404,7 +404,7 @@ void __init emev2_add_standard_devices(void)
ARRAY_SIZE(emev2_late_devices));
}
void __init emev2_init_delay(void)
static void __init emev2_init_delay(void)
{
shmobile_setup_delay(533, 1, 3); /* Cortex-A9 @ 533MHz */
}
......@@ -439,7 +439,7 @@ static const struct of_dev_auxdata emev2_auxdata_lookup[] __initconst = {
{ }
};
void __init emev2_add_standard_devices_dt(void)
static void __init emev2_add_standard_devices_dt(void)
{
of_platform_populate(NULL, of_default_bus_match_table,
emev2_auxdata_lookup, NULL);
......
arch/arm/mach-shmobile/setup-r8a7779.c
View file @ 8f07b1d5
......@@ -21,6 +21,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/of_platform.h>
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/input.h>
......@@ -28,6 +29,7 @@
#include <linux/serial_sci.h>
#include <linux/sh_intc.h>
#include <linux/sh_timer.h>
#include <linux/dma-mapping.h>
#include <mach/hardware.h>
#include <mach/irqs.h>
#include <mach/r8a7779.h>
......@@ -91,7 +93,7 @@ static struct plat_sci_port scif0_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_spi(88)),
.irqs = SCIx_IRQ_MUXED(gic_iid(0x78)),
};
static struct platform_device scif0_device = {
......@@ -108,7 +110,7 @@ static struct plat_sci_port scif1_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_spi(89)),
.irqs = SCIx_IRQ_MUXED(gic_iid(0x79)),
};
static struct platform_device scif1_device = {
......@@ -125,7 +127,7 @@ static struct plat_sci_port scif2_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_spi(90)),
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7a)),
};
static struct platform_device scif2_device = {
......@@ -142,7 +144,7 @@ static struct plat_sci_port scif3_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_spi(91)),
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7b)),
};
static struct platform_device scif3_device = {
......@@ -159,7 +161,7 @@ static struct plat_sci_port scif4_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_spi(92)),
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7c)),
};
static struct platform_device scif4_device = {
......@@ -176,7 +178,7 @@ static struct plat_sci_port scif5_platform_data = {
.scscr = SCSCR_RE | SCSCR_TE | SCSCR_CKE1,
.scbrr_algo_id = SCBRR_ALGO_2,
.type = PORT_SCIF,
.irqs = SCIx_IRQ_MUXED(gic_spi(93)),
.irqs = SCIx_IRQ_MUXED(gic_iid(0x7d)),
};
static struct platform_device scif5_device = {
......@@ -203,7 +205,7 @@ static struct resource tmu00_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(32),
.start = gic_iid(0x40),
.flags = IORESOURCE_IRQ,
},
};
......@@ -233,7 +235,7 @@ static struct resource tmu01_resources[] = {
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_spi(33),
.start = gic_iid(0x41),
.flags = IORESOURCE_IRQ,
},
};
......@@ -255,7 +257,7 @@ static struct resource rcar_i2c0_res[] = {
.end = 0xffc70fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(79),
.start = gic_iid(0x6f),
.flags = IORESOURCE_IRQ,
},
};
......@@ -273,7 +275,7 @@ static struct resource rcar_i2c1_res[] = {
.end = 0xffc71fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(82),
.start = gic_iid(0x72),
.flags = IORESOURCE_IRQ,
},
};
......@@ -291,7 +293,7 @@ static struct resource rcar_i2c2_res[] = {
.end = 0xffc72fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(80),
.start = gic_iid(0x70),
.flags = IORESOURCE_IRQ,
},
};
......@@ -309,7 +311,7 @@ static struct resource rcar_i2c3_res[] = {
.end = 0xffc73fff,
.flags = IORESOURCE_MEM,
}, {
.start = gic_spi(81),
.start = gic_iid(0x71),
.flags = IORESOURCE_IRQ,
},
};
......@@ -321,7 +323,31 @@ static struct platform_device i2c3_device = {
.num_resources = ARRAY_SIZE(rcar_i2c3_res),
};
static struct platform_device *r8a7779_early_devices[] __initdata = {
static struct resource sata_resources[] = {
[0] = {
.name = "rcar-sata",
.start = 0xfc600000,
.end = 0xfc601fff,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = gic_iid(0x84),
.flags = IORESOURCE_IRQ,
},
};
static struct platform_device sata_device = {
.name = "sata_rcar",
.id = -1,
.resource = sata_resources,
.num_resources = ARRAY_SIZE(sata_resources),
.dev = {
.dma_mask = &sata_device.dev.coherent_dma_mask,
.coherent_dma_mask = DMA_BIT_MASK(32),
},
};
static struct platform_device *r8a7779_devices_dt[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
......@@ -330,13 +356,14 @@ static struct platform_device *r8a7779_early_devices[] __initdata = {
&scif5_device,
&tmu00_device,
&tmu01_device,
};
static struct platform_device *r8a7779_late_devices[] __initdata = {
&i2c0_device,
&i2c1_device,
&i2c2_device,
&i2c3_device,
};
static struct platform_device *r8a7779_late_devices[] __initdata = {
&sata_device,
};
void __init r8a7779_add_standard_devices(void)
......@@ -349,8 +376,8 @@ void __init r8a7779_add_standard_devices(void)
r8a7779_init_pm_domains();
platform_add_devices(r8a7779_early_devices,
ARRAY_SIZE(r8a7779_early_devices));
platform_add_devices(r8a7779_devices_dt,
ARRAY_SIZE(r8a7779_devices_dt));
platform_add_devices(r8a7779_late_devices,
ARRAY_SIZE(r8a7779_late_devices));
}
......@@ -367,8 +394,8 @@ void __init r8a7779_earlytimer_init(void)
void __init r8a7779_add_early_devices(void)
{
early_platform_add_devices(r8a7779_early_devices,
ARRAY_SIZE(r8a7779_early_devices));
early_platform_add_devices(r8a7779_devices_dt,
ARRAY_SIZE(r8a7779_devices_dt));
/* Early serial console setup is not included here due to
* memory map collisions. The SCIF serial ports in r8a7779
......@@ -386,3 +413,40 @@ void __init r8a7779_add_early_devices(void)
* command line in case of the marzen board.
*/
}
#ifdef CONFIG_USE_OF
void __init r8a7779_init_delay(void)
{
shmobile_setup_delay(1000, 2, 4); /* Cortex-A9 @ 1000MHz */
}
static const struct of_dev_auxdata r8a7779_auxdata_lookup[] __initconst = {
{},
};
void __init r8a7779_add_standard_devices_dt(void)
{
/* clocks are setup late during boot in the case of DT */
r8a7779_clock_init();
platform_add_devices(r8a7779_devices_dt,
ARRAY_SIZE(r8a7779_devices_dt));
of_platform_populate(NULL, of_default_bus_match_table,
r8a7779_auxdata_lookup, NULL);
}
static const char *r8a7779_compat_dt[] __initdata = {
"renesas,r8a7779",
NULL,
};
DT_MACHINE_START(R8A7779_DT, "Generic R8A7779 (Flattened Device Tree)")
.map_io = r8a7779_map_io,
.init_early = r8a7779_init_delay,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = r8a7779_init_irq_dt,
.init_machine = r8a7779_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = r8a7779_compat_dt,
MACHINE_END
#endif /* CONFIG_USE_OF */
arch/arm/mach-shmobile/setup-sh73a0.c
View file @ 8f07b1d5
......@@ -22,6 +22,7 @@
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/irqchip.h>
#include <linux/platform_device.h>
#include <linux/of_platform.h>
#include <linux/delay.h>
......@@ -810,7 +811,7 @@ static struct platform_device ipmmu_device = {
.num_resources = ARRAY_SIZE(ipmmu_resources),
};
static struct platform_device *sh73a0_early_devices_dt[] __initdata = {
static struct platform_device *sh73a0_devices_dt[] __initdata = {
&scif0_device,
&scif1_device,
&scif2_device,
......@@ -847,8 +848,8 @@ void __init sh73a0_add_standard_devices(void)
/* Clear software reset bit on SY-DMAC module */
__raw_writel(__raw_readl(SRCR2) & ~(1 << 18), SRCR2);
platform_add_devices(sh73a0_early_devices_dt,
ARRAY_SIZE(sh73a0_early_devices_dt));
platform_add_devices(sh73a0_devices_dt,
ARRAY_SIZE(sh73a0_devices_dt));
platform_add_devices(sh73a0_early_devices,
ARRAY_SIZE(sh73a0_early_devices));
platform_add_devices(sh73a0_late_devices,
......@@ -867,8 +868,8 @@ void __init sh73a0_earlytimer_init(void)
void __init sh73a0_add_early_devices(void)
{
early_platform_add_devices(sh73a0_early_devices_dt,
ARRAY_SIZE(sh73a0_early_devices_dt));
early_platform_add_devices(sh73a0_devices_dt,
ARRAY_SIZE(sh73a0_devices_dt));
early_platform_add_devices(sh73a0_early_devices,
ARRAY_SIZE(sh73a0_early_devices));
......@@ -878,23 +879,9 @@ void __init sh73a0_add_early_devices(void)
#ifdef CONFIG_USE_OF
/* Please note that the clock initialisation shcheme used in
* sh73a0_add_early_devices_dt() and sh73a0_add_standard_devices_dt()
* does not work with SMP as there is a yet to be resolved lock-up in
* workqueue initialisation.
*
* CONFIG_SMP should be disabled when using this code.
*/
void __init sh73a0_add_early_devices_dt(void)
void __init sh73a0_init_delay(void)
{
shmobile_setup_delay(1196, 44, 46); /* Cortex-A9 @ 1196MHz */
early_platform_add_devices(sh73a0_early_devices_dt,
ARRAY_SIZE(sh73a0_early_devices_dt));
/* setup early console here as well */
shmobile_setup_console();
}
static const struct of_dev_auxdata sh73a0_auxdata_lookup[] __initconst = {
......@@ -906,8 +893,8 @@ void __init sh73a0_add_standard_devices_dt(void)
/* clocks are setup late during boot in the case of DT */
sh73a0_clock_init();
platform_add_devices(sh73a0_early_devices_dt,
ARRAY_SIZE(sh73a0_early_devices_dt));
platform_add_devices(sh73a0_devices_dt,
ARRAY_SIZE(sh73a0_devices_dt));
of_platform_populate(NULL, of_default_bus_match_table,
sh73a0_auxdata_lookup, NULL);
}
......@@ -918,10 +905,11 @@ static const char *sh73a0_boards_compat_dt[] __initdata = {
};
DT_MACHINE_START(SH73A0_DT, "Generic SH73A0 (Flattened Device Tree)")
.smp = smp_ops(sh73a0_smp_ops),
.map_io = sh73a0_map_io,
.init_early = sh73a0_add_early_devices_dt,
.init_early = sh73a0_init_delay,
.nr_irqs = NR_IRQS_LEGACY,
.init_irq = sh73a0_init_irq_dt,
.init_irq = irqchip_init,
.init_machine = sh73a0_add_standard_devices_dt,
.init_time = shmobile_timer_init,
.dt_compat = sh73a0_boards_compat_dt,
......
arch/arm/mach-shmobile/smp-emev2.c
View file @ 8f07b1d5
......@@ -28,63 +28,9 @@
#include <mach/emev2.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/cacheflush.h>
#define EMEV2_SCU_BASE 0x1e000000
static DEFINE_SPINLOCK(scu_lock);
static void __iomem *scu_base;
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
{
unsigned long tmp;
/* we assume this code is running on a different cpu
* than the one that is changing coherency setting */
spin_lock(&scu_lock);
tmp = readl(scu_base + 8);
tmp &= ~clr;
tmp |= set;
writel(tmp, scu_base + 8);
spin_unlock(&scu_lock);
}
static unsigned int __init emev2_get_core_count(void)
{
if (!scu_base) {
scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
emev2_clock_init(); /* need ioremapped SMU */
}
WARN_ON_ONCE(!scu_base);
return scu_base ? scu_get_core_count(scu_base) : 1;
}
static int emev2_platform_cpu_kill(unsigned int cpu)
{
return 0; /* not supported yet */
}
static int __maybe_unused emev2_cpu_kill(unsigned int cpu)
{
int k;
/* this function is running on another CPU than the offline target,
* here we need wait for shutdown code in platform_cpu_die() to
* finish before asking SoC-specific code to power off the CPU core.
*/
for (k = 0; k < 1000; k++) {
if (shmobile_cpu_is_dead(cpu))
return emev2_platform_cpu_kill(cpu);
mdelay(1);
}
return 0;
}
static void __cpuinit emev2_secondary_init(unsigned int cpu)
{
gic_secondary_init(0);
......@@ -92,31 +38,30 @@ static void __cpuinit emev2_secondary_init(unsigned int cpu)
static int __cpuinit emev2_boot_secondary(unsigned int cpu, struct task_struct *idle)
{
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
/* Tell ROM loader about our vector (in headsmp.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector));
arch_send_wakeup_ipi_mask(cpumask_of(cpu));
arch_send_wakeup_ipi_mask(cpumask_of(cpu_logical_map(cpu)));
return 0;
}
static void __init emev2_smp_prepare_cpus(unsigned int max_cpus)
{
int cpu = cpu_logical_map(0);
scu_enable(shmobile_scu_base);
scu_enable(scu_base);
/* Tell ROM loader about our vector (in headsmp-scu.S) */
emev2_set_boot_vector(__pa(shmobile_secondary_vector_scu));
/* enable cache coherency on CPU0 */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
/* enable cache coherency on booting CPU */
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
}
static void __init emev2_smp_init_cpus(void)
{
unsigned int ncores = emev2_get_core_count();
unsigned int ncores;
/* setup EMEV2 specific SCU base */
shmobile_scu_base = ioremap(EMEV2_SCU_BASE, PAGE_SIZE);
emev2_clock_init(); /* need ioremapped SMU */
ncores = shmobile_scu_base ? scu_get_core_count(shmobile_scu_base) : 1;
shmobile_smp_init_cpus(ncores);
}
......@@ -126,9 +71,4 @@ struct smp_operations emev2_smp_ops __initdata = {
.smp_prepare_cpus = emev2_smp_prepare_cpus,
.smp_secondary_init = emev2_secondary_init,
.smp_boot_secondary = emev2_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = emev2_cpu_kill,
.cpu_die = shmobile_cpu_die,
.cpu_disable = shmobile_cpu_disable,
#endif
};
arch/arm/mach-shmobile/smp-r8a7779.c
View file @ 8f07b1d5
......@@ -26,11 +26,13 @@
#include <linux/irqchip/arm-gic.h>
#include <mach/common.h>
#include <mach/r8a7779.h>
#include <asm/cacheflush.h>
#include <asm/smp_plat.h>
#include <asm/smp_scu.h>
#include <asm/smp_twd.h>
#define AVECR IOMEM(0xfe700040)
#define R8A7779_SCU_BASE 0xf0000000
static struct r8a7779_pm_ch r8a7779_ch_cpu1 = {
.chan_offs = 0x40, /* PWRSR0 .. PWRER0 */
......@@ -56,44 +58,14 @@ static struct r8a7779_pm_ch *r8a7779_ch_cpu[4] = {
[3] = &r8a7779_ch_cpu3,
};
static void __iomem *scu_base_addr(void)
{
return (void __iomem *)0xf0000000;
}
static DEFINE_SPINLOCK(scu_lock);
static unsigned long tmp;
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, R8A7779_SCU_BASE + 0x600, 29);
void __init r8a7779_register_twd(void)
{
twd_local_timer_register(&twd_local_timer);
}
#endif
static void modify_scu_cpu_psr(unsigned long set, unsigned long clr)
{
void __iomem *scu_base = scu_base_addr();
spin_lock(&scu_lock);
tmp = __raw_readl(scu_base + 8);
tmp &= ~clr;
tmp |= set;
spin_unlock(&scu_lock);
/* disable cache coherency after releasing the lock */
__raw_writel(tmp, scu_base + 8);
}
static unsigned int __init r8a7779_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
return scu_get_core_count(scu_base);
}
static int r8a7779_platform_cpu_kill(unsigned int cpu)
{
struct r8a7779_pm_ch *ch = NULL;
......@@ -101,9 +73,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
cpu = cpu_logical_map(cpu);
/* disable cache coherency */
modify_scu_cpu_psr(3 << (cpu * 8), 0);
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
......@@ -113,25 +82,6 @@ static int r8a7779_platform_cpu_kill(unsigned int cpu)
return ret ? ret : 1;
}
static int __maybe_unused r8a7779_cpu_kill(unsigned int cpu)
{
int k;
/* this function is running on another CPU than the offline target,
* here we need wait for shutdown code in platform_cpu_die() to
* finish before asking SoC-specific code to power off the CPU core.
*/
for (k = 0; k < 1000; k++) {
if (shmobile_cpu_is_dead(cpu))
return r8a7779_platform_cpu_kill(cpu);
mdelay(1);
}
return 0;
}
static void __cpuinit r8a7779_secondary_init(unsigned int cpu)
{
gic_secondary_init(0);
......@@ -144,9 +94,6 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
cpu = cpu_logical_map(cpu);
/* enable cache coherency */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
if (cpu < ARRAY_SIZE(r8a7779_ch_cpu))
ch = r8a7779_ch_cpu[cpu];
......@@ -158,15 +105,13 @@ static int __cpuinit r8a7779_boot_secondary(unsigned int cpu, struct task_struct
static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
{
int cpu = cpu_logical_map(0);
scu_enable(shmobile_scu_base);
scu_enable(scu_base_addr());
/* Map the reset vector (in headsmp-scu.S) */
__raw_writel(__pa(shmobile_secondary_vector_scu), AVECR);
/* Map the reset vector (in headsmp.S) */
__raw_writel(__pa(shmobile_secondary_vector), AVECR);
/* enable cache coherency on CPU0 */
modify_scu_cpu_psr(0, 3 << (cpu * 8));
/* enable cache coherency on booting CPU */
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
r8a7779_pm_init();
......@@ -178,10 +123,60 @@ static void __init r8a7779_smp_prepare_cpus(unsigned int max_cpus)
static void __init r8a7779_smp_init_cpus(void)
{
unsigned int ncores = r8a7779_get_core_count();
/* setup r8a7779 specific SCU base */
shmobile_scu_base = IOMEM(R8A7779_SCU_BASE);
shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
}
shmobile_smp_init_cpus(ncores);
#ifdef CONFIG_HOTPLUG_CPU
static int r8a7779_scu_psr_core_disabled(int cpu)
{
unsigned long mask = 3 << (cpu * 8);
if ((__raw_readl(shmobile_scu_base + 8) & mask) == mask)
return 1;
return 0;
}
static int r8a7779_cpu_kill(unsigned int cpu)
{
int k;
/* this function is running on another CPU than the offline target,
* here we need wait for shutdown code in platform_cpu_die() to
* finish before asking SoC-specific code to power off the CPU core.
*/
for (k = 0; k < 1000; k++) {
if (r8a7779_scu_psr_core_disabled(cpu))
return r8a7779_platform_cpu_kill(cpu);
mdelay(1);
}
return 0;
}
static void r8a7779_cpu_die(unsigned int cpu)
{
dsb();
flush_cache_all();
/* disable cache coherency */
scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
/* Endless loop until power off from r8a7779_cpu_kill() */
while (1)
cpu_do_idle();
}
static int r8a7779_cpu_disable(unsigned int cpu)
{
/* only CPU1->3 have power domains, do not allow hotplug of CPU0 */
return cpu == 0 ? -EPERM : 0;
}
#endif /* CONFIG_HOTPLUG_CPU */
struct smp_operations r8a7779_smp_ops __initdata = {
.smp_init_cpus = r8a7779_smp_init_cpus,
......@@ -190,7 +185,7 @@ struct smp_operations r8a7779_smp_ops __initdata = {
.smp_boot_secondary = r8a7779_boot_secondary,
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = r8a7779_cpu_kill,
.cpu_die = shmobile_cpu_die,
.cpu_disable = shmobile_cpu_disable,
.cpu_die = r8a7779_cpu_die,
.cpu_disable = r8a7779_cpu_disable,
#endif
};
arch/arm/mach-shmobile/smp-sh73a0.c
View file @ 8f07b1d5
......@@ -39,26 +39,16 @@
#define PSTR_SHUTDOWN_MODE 3
static void __iomem *scu_base_addr(void)
{
return (void __iomem *)0xf0000000;
}
#define SH73A0_SCU_BASE 0xf0000000
#ifdef CONFIG_HAVE_ARM_TWD
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, SH73A0_SCU_BASE + 0x600, 29);
void __init sh73a0_register_twd(void)
{
twd_local_timer_register(&twd_local_timer);
}
#endif
static unsigned int __init sh73a0_get_core_count(void)
{
void __iomem *scu_base = scu_base_addr();
return scu_get_core_count(scu_base);
}
static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
{
gic_secondary_init(0);
......@@ -78,21 +68,22 @@ static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct
static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
{
scu_enable(scu_base_addr());
scu_enable(shmobile_scu_base);
/* Map the reset vector (in headsmp-sh73a0.S) */
/* Map the reset vector (in headsmp-scu.S) */
__raw_writel(0, APARMBAREA); /* 4k */
__raw_writel(__pa(sh73a0_secondary_vector), SBAR);
__raw_writel(__pa(shmobile_secondary_vector_scu), SBAR);
/* enable cache coherency on booting CPU */
scu_power_mode(scu_base_addr(), SCU_PM_NORMAL);
scu_power_mode(shmobile_scu_base, SCU_PM_NORMAL);
}
static void __init sh73a0_smp_init_cpus(void)
{
unsigned int ncores = sh73a0_get_core_count();
/* setup sh73a0 specific SCU base */
shmobile_scu_base = IOMEM(SH73A0_SCU_BASE);
shmobile_smp_init_cpus(ncores);
shmobile_smp_init_cpus(scu_get_core_count(shmobile_scu_base));
}
#ifdef CONFIG_HOTPLUG_CPU
......@@ -128,11 +119,16 @@ static void sh73a0_cpu_die(unsigned int cpu)
flush_cache_all();
/* Set power off mode. This takes the CPU out of the MP cluster */
scu_power_mode(scu_base_addr(), SCU_PM_POWEROFF);
scu_power_mode(shmobile_scu_base, SCU_PM_POWEROFF);
/* Enter shutdown mode */
cpu_do_idle();
}
static int sh73a0_cpu_disable(unsigned int cpu)
{
return 0; /* CPU0 and CPU1 supported */
}
#endif /* CONFIG_HOTPLUG_CPU */
struct smp_operations sh73a0_smp_ops __initdata = {
......@@ -143,6 +139,6 @@ struct smp_operations sh73a0_smp_ops __initdata = {
#ifdef CONFIG_HOTPLUG_CPU
.cpu_kill = sh73a0_cpu_kill,
.cpu_die = sh73a0_cpu_die,
.cpu_disable = shmobile_cpu_disable_any,
.cpu_disable = sh73a0_cpu_disable,
#endif
};
arch/sh/kernel/cpu/sh2a/pinmux-sh7203.c
View file @ 8f07b1d5
......@@ -8,12 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7203_pfc_resources[] = {
[0] = {
.start = 0xfffe3800,
.end = 0xfffe3a9f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7203", NULL, 0);
return sh_pfc_register("pfc-sh7203", sh7203_pfc_resources,
ARRAY_SIZE(sh7203_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh2a/pinmux-sh7264.c
View file @ 8f07b1d5
......@@ -8,12 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7264_pfc_resources[] = {
[0] = {
.start = 0xfffe3800,
.end = 0xfffe393f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7264", NULL, 0);
return sh_pfc_register("pfc-sh7264", sh7264_pfc_resources,
ARRAY_SIZE(sh7264_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh2a/pinmux-sh7269.c
View file @ 8f07b1d5
......@@ -13,8 +13,17 @@
#include <linux/kernel.h>
#include <cpu/pfc.h>
static struct resource sh7269_pfc_resources[] = {
[0] = {
.start = 0xfffe3800,
.end = 0xfffe391f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7269", NULL, 0);
return sh_pfc_register("pfc-sh7269", sh7269_pfc_resources,
ARRAY_SIZE(sh7269_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh3/pinmux-sh7720.c
View file @ 8f07b1d5
......@@ -8,13 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7720_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405016f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7720", NULL, 0);
return sh_pfc_register("pfc-sh7720", sh7720_pfc_resources,
ARRAY_SIZE(sh7720_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-sh7722.c
View file @ 8f07b1d5
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7722_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405018f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7722", NULL, 0);
return sh_pfc_register("pfc-sh7722", sh7722_pfc_resources,
ARRAY_SIZE(sh7722_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-sh7723.c
View file @ 8f07b1d5
......@@ -8,13 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7723_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405016f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7723", NULL, 0);
return sh_pfc_register("pfc-sh7723", sh7723_pfc_resources,
ARRAY_SIZE(sh7723_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-sh7724.c
View file @ 8f07b1d5
......@@ -13,12 +13,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7724_pfc_resources[] = {
[0] = {
.start = 0xa4050100,
.end = 0xa405016f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7724", NULL, 0);
return sh_pfc_register("pfc-sh7724", sh7724_pfc_resources,
ARRAY_SIZE(sh7724_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-sh7757.c
View file @ 8f07b1d5
......@@ -13,12 +13,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7757_pfc_resources[] = {
[0] = {
.start = 0xffec0000,
.end = 0xffec008f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7757", NULL, 0);
return sh_pfc_register("pfc-sh7757", sh7757_pfc_resources,
ARRAY_SIZE(sh7757_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-sh7785.c
View file @ 8f07b1d5
......@@ -8,13 +8,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7785_pfc_resources[] = {
[0] = {
.start = 0xffe70000,
.end = 0xffe7008f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7785", NULL, 0);
return sh_pfc_register("pfc-sh7785", sh7785_pfc_resources,
ARRAY_SIZE(sh7785_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-sh7786.c
View file @ 8f07b1d5
......@@ -13,13 +13,23 @@
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static struct resource sh7786_pfc_resources[] = {
[0] = {
.start = 0xffcc0000,
.end = 0xffcc008f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-sh7786", NULL, 0);
return sh_pfc_register("pfc-sh7786", sh7786_pfc_resources,
ARRAY_SIZE(sh7786_pfc_resources));
}
arch_initcall(plat_pinmux_setup);
arch/sh/kernel/cpu/sh4a/pinmux-shx3.c
View file @ 8f07b1d5
......@@ -7,12 +7,23 @@
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*/
#include <linux/bug.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <cpu/pfc.h>
static int __init shx3_pinmux_setup(void)
static struct resource shx3_pfc_resources[] = {
[0] = {
.start = 0xffc70000,
.end = 0xffc7001f,
.flags = IORESOURCE_MEM,
},
};
static int __init plat_pinmux_setup(void)
{
return sh_pfc_register("pfc-shx3", NULL, 0);
return sh_pfc_register("pfc-shx3", shx3_pfc_resources,
ARRAY_SIZE(shx3_pfc_resources));
}
arch_initcall(shx3_pinmux_setup);
arch_initcall(plat_pinmux_setup);
drivers/gpio/gpio-pl061.c
View file @ 8f07b1d5
This diff is collapsed.
drivers/gpio/gpiolib-of.c
View file @ 8f07b1d5
......@@ -193,7 +193,7 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!np)
return;
do {
for (;; index++) {
ret = of_parse_phandle_with_args(np, "gpio-ranges",
"#gpio-range-cells", index, &pinspec);
if (ret)
......@@ -203,27 +203,15 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
if (!pctldev)
break;
/*
* This assumes that the n GPIO pins are consecutive in the
* GPIO number space, and that the pins are also consecutive
* in their local number space. Currently it is not possible
* to add different ranges for one and the same GPIO chip,
* as the code assumes that we have one consecutive range
* on both, mapping 1-to-1.
*
* TODO: make the OF bindings handle multiple sparse ranges
* on the same GPIO chip.
*/
ret = gpiochip_add_pin_range(chip,
pinctrl_dev_get_devname(pctldev),
0, /* offset in gpiochip */
pinspec.args[0],
pinspec.args[1]);
pinspec.args[1],
pinspec.args[2]);
if (ret)
break;
} while (index++);
}
}
#else
......
drivers/pinctrl/Kconfig
View file @ 8f07b1d5
......@@ -166,6 +166,7 @@ config PINCTRL_SINGLE
depends on OF
select PINMUX
select PINCONF
select GENERIC_PINCONF
help
This selects the device tree based generic pinctrl driver.
......
drivers/pinctrl/core.c
View file @ 8f07b1d5
......@@ -27,6 +27,7 @@
#include <linux/pinctrl/consumer.h>
#include <linux/pinctrl/pinctrl.h>
#include <linux/pinctrl/machine.h>
#include <asm-generic/gpio.h>
#include "core.h"
#include "devicetree.h"
#include "pinmux.h"
......@@ -276,6 +277,39 @@ pinctrl_match_gpio_range(struct pinctrl_dev *pctldev, unsigned gpio)
return NULL;
}
/**
* pinctrl_ready_for_gpio_range() - check if other GPIO pins of
* the same GPIO chip are in range
* @gpio: gpio pin to check taken from the global GPIO pin space
*
* This function is complement of pinctrl_match_gpio_range(). If the return
* value of pinctrl_match_gpio_range() is NULL, this function could be used
* to check whether pinctrl device is ready or not. Maybe some GPIO pins
* of the same GPIO chip don't have back-end pinctrl interface.
* If the return value is true, it means that pinctrl device is ready & the
* certain GPIO pin doesn't have back-end pinctrl device. If the return value
* is false, it means that pinctrl device may not be ready.
*/
static bool pinctrl_ready_for_gpio_range(unsigned gpio)
{
struct pinctrl_dev *pctldev;
struct pinctrl_gpio_range *range = NULL;
struct gpio_chip *chip = gpio_to_chip(gpio);
/* Loop over the pin controllers */
list_for_each_entry(pctldev, &pinctrldev_list, node) {
/* Loop over the ranges */
list_for_each_entry(range, &pctldev->gpio_ranges, node) {
/* Check if any gpio range overlapped with gpio chip */
if (range->base + range->npins - 1 < chip->base ||
range->base > chip->base + chip->ngpio - 1)
continue;
return true;
}
}
return false;
}
/**
* pinctrl_get_device_gpio_range() - find device for GPIO range
* @gpio: the pin to locate the pin controller for
......@@ -443,6 +477,8 @@ int pinctrl_request_gpio(unsigned gpio)
ret = pinctrl_get_device_gpio_range(gpio, &pctldev, &range);
if (ret) {
if (pinctrl_ready_for_gpio_range(gpio))
ret = 0;
mutex_unlock(&pinctrl_mutex);
return ret;
}
......@@ -979,9 +1015,8 @@ static int devm_pinctrl_match(struct device *dev, void *res, void *data)
*/
void devm_pinctrl_put(struct pinctrl *p)
{
WARN_ON(devres_destroy(p->dev, devm_pinctrl_release,
WARN_ON(devres_release(p->dev, devm_pinctrl_release,
devm_pinctrl_match, p));
pinctrl_put(p);
}
EXPORT_SYMBOL_GPL(devm_pinctrl_put);
......
drivers/pinctrl/devicetree.c
View file @ 8f07b1d5
......@@ -41,7 +41,7 @@ static void dt_free_map(struct pinctrl_dev *pctldev,
struct pinctrl_map *map, unsigned num_maps)
{
if (pctldev) {
struct pinctrl_ops *ops = pctldev->desc->pctlops;
const struct pinctrl_ops *ops = pctldev->desc->pctlops;
ops->dt_free_map(pctldev, map, num_maps);
} else {
/* There is no pctldev for PIN_MAP_TYPE_DUMMY_STATE */
......@@ -122,7 +122,7 @@ static int dt_to_map_one_config(struct pinctrl *p, const char *statename,
{
struct device_node *np_pctldev;
struct pinctrl_dev *pctldev;
struct pinctrl_ops *ops;
const struct pinctrl_ops *ops;
int ret;
struct pinctrl_map *map;
unsigned num_maps;
......
drivers/pinctrl/mvebu/pinctrl-mvebu.c
View file @ 8f07b1d5
......@@ -263,7 +263,7 @@ static void mvebu_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
return;
}
static struct pinconf_ops mvebu_pinconf_ops = {
static const struct pinconf_ops mvebu_pinconf_ops = {
.pin_config_group_get = mvebu_pinconf_group_get,
.pin_config_group_set = mvebu_pinconf_group_set,
.pin_config_group_dbg_show = mvebu_pinconf_group_dbg_show,
......@@ -369,7 +369,7 @@ static int mvebu_pinmux_gpio_set_direction(struct pinctrl_dev *pctldev,
return -ENOTSUPP;
}
static struct pinmux_ops mvebu_pinmux_ops = {
static const struct pinmux_ops mvebu_pinmux_ops = {
.get_functions_count = mvebu_pinmux_get_funcs_count,
.get_function_name = mvebu_pinmux_get_func_name,
.get_function_groups = mvebu_pinmux_get_groups,
......@@ -470,7 +470,7 @@ static void mvebu_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
kfree(map);
}
static struct pinctrl_ops mvebu_pinctrl_ops = {
static const struct pinctrl_ops mvebu_pinctrl_ops = {
.get_groups_count = mvebu_pinctrl_get_groups_count,
.get_group_name = mvebu_pinctrl_get_group_name,
.get_group_pins = mvebu_pinctrl_get_group_pins,
......
drivers/pinctrl/pinconf-generic.c
View file @ 8f07b1d5
......@@ -12,6 +12,7 @@
#define pr_fmt(fmt) "generic pinconfig core: " fmt
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/slab.h>
......@@ -120,4 +121,17 @@ void pinconf_generic_dump_group(struct pinctrl_dev *pctldev,
}
}
void pinconf_generic_dump_config(struct pinctrl_dev *pctldev,
struct seq_file *s, unsigned long config)
{
int i;
for(i = 0; i < ARRAY_SIZE(conf_items); i++) {
if (pinconf_to_config_param(config) != conf_items[i].param)
continue;
seq_printf(s, "%s: 0x%x", conf_items[i].display,
pinconf_to_config_argument(config));
}
}
EXPORT_SYMBOL_GPL(pinconf_generic_dump_config);
#endif
drivers/pinctrl/pinconf.c
View file @ 8f07b1d5
......@@ -622,7 +622,7 @@ static const struct file_operations pinconf_dbg_pinname_fops = {
static int pinconf_dbg_state_print(struct seq_file *s, void *d)
{
if (strlen(dbg_state_name))
seq_printf(s, "%s\n", dbg_pinname);
seq_printf(s, "%s\n", dbg_state_name);
else
seq_printf(s, "No pin state set\n");
return 0;
......@@ -670,7 +670,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
struct pinctrl_maps *maps_node;
struct pinctrl_map const *map;
struct pinctrl_dev *pctldev = NULL;
struct pinconf_ops *confops = NULL;
const struct pinconf_ops *confops = NULL;
int i, j;
bool found = false;
......
drivers/pinctrl/pinconf.h
View file @ 8f07b1d5
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drivers/pinctrl/pinctrl-abx500.c
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drivers/pinctrl/pinctrl-exynos5440.c
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drivers/pinctrl/sh-pfc/Kconfig
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drivers/pinctrl/sh-pfc/pfc-r8a7779.c
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drivers/pinctrl/sh-pfc/pfc-sh7203.c
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drivers/pinctrl/sh-pfc/pfc-sh7264.c
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drivers/pinctrl/sh-pfc/pfc-sh7269.c
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