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Commit 8f1c76f6 authored by James Simmons's avatar James Simmons
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Fixed bug for large logos. Also had to make a patch to handle X server... 

Fixed bug for large logos. Also had to make a patch to handle X server reversing the image order programming verses how the riva fbdev driver does it.
parent fafa93c5
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Showing with 203 additions and 112 deletions
drivers/video/fbcon.c
View file @ 8f1c76f6
...@@ -682,7 +682,7 @@ static void fbcon_setup(int con, int init, int logo) ...@@ -682,7 +682,7 @@ static void fbcon_setup(int con, int init, int logo)
} }
scr_memsetw((unsigned short *)conp->vc_origin, scr_memsetw((unsigned short *)conp->vc_origin,
conp->vc_video_erase_char, conp->vc_video_erase_char,
conp->vc_size_row * logo_lines); old_cols * logo_lines);
} }
/* /*
......
drivers/video/riva/fbdev.c
View file @ 8f1c76f6
...@@ -262,6 +262,25 @@ static struct fb_var_screeninfo rivafb_default_var = { ...@@ -262,6 +262,25 @@ static struct fb_var_screeninfo rivafb_default_var = {
vmode: FB_VMODE_NONINTERLACED vmode: FB_VMODE_NONINTERLACED
}; };
static u8 byte_rev[256] = {
0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0, 0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8, 0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4, 0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec, 0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2, 0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea, 0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6, 0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee, 0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1, 0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9, 0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5, 0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed, 0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3, 0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb, 0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7, 0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef, 0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
};
/* from GGI */ /* from GGI */
static const struct riva_regs reg_template = { static const struct riva_regs reg_template = {
{0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */ {0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, /* ATTR */
...@@ -283,8 +302,6 @@ static const struct riva_regs reg_template = { ...@@ -283,8 +302,6 @@ static const struct riva_regs reg_template = {
0xEB /* MISC */ 0xEB /* MISC */
}; };
/* ------------------------------------------------------------------------- * /* ------------------------------------------------------------------------- *
* *
* MMIO access macros * MMIO access macros
...@@ -949,6 +966,15 @@ void riva_setup_accel(struct riva_par *par) ...@@ -949,6 +966,15 @@ void riva_setup_accel(struct riva_par *par)
wait_for_idle(par); wait_for_idle(par);
} }
static inline void reverse_order(u32 *l)
{
u8 *a = (u8 *)l;
*a++ = byte_rev[*a];
/* *a++ = byte_rev[*a];
*a++ = byte_rev[*a];*/
*a = byte_rev[*a];
}
static void rivafb_fillrect(struct fb_info *info, struct fb_fillrect *rect) static void rivafb_fillrect(struct fb_info *info, struct fb_fillrect *rect)
{ {
struct riva_par *par = (struct riva_par *) info->par; struct riva_par *par = (struct riva_par *) info->par;
...@@ -1016,7 +1042,8 @@ static void rivafb_imageblit(struct fb_info *info, struct fb_image *image) ...@@ -1016,7 +1042,8 @@ static void rivafb_imageblit(struct fb_info *info, struct fb_image *image)
cdat2 = *image->data++; cdat2 = *image->data++;
else else
cdat2 = *((u16*)image->data)++; cdat2 = *((u16*)image->data)++;
d[j] = cdat2; reverse_order(&cdat2);
d[j] = cdat2;
} }
} }
} }
......
drivers/video/riva/riva_tbl.h
View file @ 8f1c76f6
...@@ -48,9 +48,6 @@ ...@@ -48,9 +48,6 @@
/* /*
* RIVA Fixed Functionality Init Tables. * RIVA Fixed Functionality Init Tables.
*/ */
/* Bit order changed to MSB. -- JM */
static unsigned RivaTablePMC[][2] = static unsigned RivaTablePMC[][2] =
{ {
{0x00000050, 0x00000000}, {0x00000050, 0x00000000},
...@@ -219,37 +216,37 @@ static unsigned nv3TablePRAMIN_8BPP[][2] = ...@@ -219,37 +216,37 @@ static unsigned nv3TablePRAMIN_8BPP[][2] =
{ {
/* 0xXXXXX3XX For MSB mono format */ /* 0xXXXXX3XX For MSB mono format */
/* 0xXXXXX2XX For LSB mono format */ /* 0xXXXXX2XX For LSB mono format */
{0x00000D04, 0x10110303}, {0x00000D04, 0x10110203},
{0x00000D08, 0x10110303}, {0x00000D08, 0x10110203},
{0x00000D0C, 0x1011030B}, {0x00000D0C, 0x1011020B},
{0x00000D10, 0x10118303}, {0x00000D10, 0x10118203},
{0x00000D14, 0x10110303}, {0x00000D14, 0x10110203},
{0x00000D18, 0x10110303}, {0x00000D18, 0x10110203},
{0x00000D1C, 0x10419308} {0x00000D1C, 0x10419208}
}; };
static unsigned nv3TablePRAMIN_15BPP[][2] = static unsigned nv3TablePRAMIN_15BPP[][2] =
{ {
/* 0xXXXXX2XX For MSB mono format */ /* 0xXXXXX2XX For MSB mono format */
/* 0xXXXXX3XX For LSB mono format */ /* 0xXXXXX3XX For LSB mono format */
{0x00000D04, 0x10110300}, {0x00000D04, 0x10110200},
{0x00000D08, 0x10110300}, {0x00000D08, 0x10110200},
{0x00000D0C, 0x10110308}, {0x00000D0C, 0x10110208},
{0x00000D10, 0x10118300}, {0x00000D10, 0x10118200},
{0x00000D14, 0x10110300}, {0x00000D14, 0x10110200},
{0x00000D18, 0x10110300}, {0x00000D18, 0x10110200},
{0x00000D1C, 0x10419308} {0x00000D1C, 0x10419208}
}; };
static unsigned nv3TablePRAMIN_32BPP[][2] = static unsigned nv3TablePRAMIN_32BPP[][2] =
{ {
/* 0xXXXXX3XX For MSB mono format */ /* 0xXXXXX3XX For MSB mono format */
/* 0xXXXXX2XX For LSB mono format */ /* 0xXXXXX2XX For LSB mono format */
{0x00000D04, 0x10110301}, {0x00000D04, 0x10110201},
{0x00000D08, 0x10110301}, {0x00000D08, 0x10110201},
{0x00000D0C, 0x10110309}, {0x00000D0C, 0x10110209},
{0x00000D10, 0x10118301}, {0x00000D10, 0x10118201},
{0x00000D14, 0x10110301}, {0x00000D14, 0x10110201},
{0x00000D18, 0x10110301}, {0x00000D18, 0x10110201},
{0x00000D1C, 0x10419308} {0x00000D1C, 0x10419208}
}; };
static unsigned nv4TableFIFO[][2] = static unsigned nv4TableFIFO[][2] =
{ {
...@@ -446,14 +443,14 @@ static unsigned nv4TablePRAMIN_8BPP[][2] = ...@@ -446,14 +443,14 @@ static unsigned nv4TablePRAMIN_8BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000301}, {0x00000509, 0x00000302},
{0x0000050D, 0x00000301}, {0x0000050D, 0x00000302},
{0x00000511, 0x00000201}, {0x00000511, 0x00000202},
{0x00000515, 0x00000301}, {0x00000515, 0x00000302},
{0x00000519, 0x00000301}, {0x00000519, 0x00000302},
{0x0000051D, 0x00000301}, {0x0000051D, 0x00000302},
{0x0000052D, 0x00000301}, {0x0000052D, 0x00000302},
{0x0000052E, 0x00000301}, {0x0000052E, 0x00000302},
{0x00000535, 0x00000000}, {0x00000535, 0x00000000},
{0x00000539, 0x00000000} {0x00000539, 0x00000000}
}; };
...@@ -461,46 +458,46 @@ static unsigned nv4TablePRAMIN_15BPP[][2] = ...@@ -461,46 +458,46 @@ static unsigned nv4TablePRAMIN_15BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000901}, {0x00000509, 0x00000902},
{0x0000050D, 0x00000901}, {0x0000050D, 0x00000902},
{0x00000511, 0x00000801}, {0x00000511, 0x00000802},
{0x00000515, 0x00000901}, {0x00000515, 0x00000902},
{0x00000519, 0x00000901}, {0x00000519, 0x00000902},
{0x0000051D, 0x00000901}, {0x0000051D, 0x00000902},
{0x0000052D, 0x00000901}, {0x0000052D, 0x00000902},
{0x0000052E, 0x00000901}, {0x0000052E, 0x00000902},
{0x00000535, 0x00000701}, {0x00000535, 0x00000702},
{0x00000539, 0x00000701} {0x00000539, 0x00000702}
}; };
static unsigned nv4TablePRAMIN_16BPP[][2] = static unsigned nv4TablePRAMIN_16BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000C01}, {0x00000509, 0x00000C02},
{0x0000050D, 0x00000C01}, {0x0000050D, 0x00000C02},
{0x00000511, 0x00000B01}, {0x00000511, 0x00000B02},
{0x00000515, 0x00000C01}, {0x00000515, 0x00000C02},
{0x00000519, 0x00000C01}, {0x00000519, 0x00000C02},
{0x0000051D, 0x00000C01}, {0x0000051D, 0x00000C02},
{0x0000052D, 0x00000C01}, {0x0000052D, 0x00000C02},
{0x0000052E, 0x00000C01}, {0x0000052E, 0x00000C02},
{0x00000535, 0x00000701}, {0x00000535, 0x00000702},
{0x00000539, 0x00000701} {0x00000539, 0x00000702}
}; };
static unsigned nv4TablePRAMIN_32BPP[][2] = static unsigned nv4TablePRAMIN_32BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000E01}, {0x00000509, 0x00000E02},
{0x0000050D, 0x00000E01}, {0x0000050D, 0x00000E02},
{0x00000511, 0x00000D01}, {0x00000511, 0x00000D02},
{0x00000515, 0x00000E01}, {0x00000515, 0x00000E02},
{0x00000519, 0x00000E01}, {0x00000519, 0x00000E02},
{0x0000051D, 0x00000E01}, {0x0000051D, 0x00000E02},
{0x0000052D, 0x00000E01}, {0x0000052D, 0x00000E02},
{0x0000052E, 0x00000E01}, {0x0000052E, 0x00000E02},
{0x00000535, 0x00000E01}, {0x00000535, 0x00000E02},
{0x00000539, 0x00000E01} {0x00000539, 0x00000E02}
}; };
static unsigned nv10TableFIFO[][2] = static unsigned nv10TableFIFO[][2] =
{ {
...@@ -891,14 +888,14 @@ static unsigned nv10TablePRAMIN_8BPP[][2] = ...@@ -891,14 +888,14 @@ static unsigned nv10TablePRAMIN_8BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000301}, {0x00000509, 0x00000302},
{0x0000050D, 0x00000301}, {0x0000050D, 0x00000302},
{0x00000511, 0x00000201}, {0x00000511, 0x00000202},
{0x00000515, 0x00000301}, {0x00000515, 0x00000302},
{0x00000519, 0x00000301}, {0x00000519, 0x00000302},
{0x0000051D, 0x00000301}, {0x0000051D, 0x00000302},
{0x0000052D, 0x00000301}, {0x0000052D, 0x00000302},
{0x0000052E, 0x00000301}, {0x0000052E, 0x00000302},
{0x00000535, 0x00000000}, {0x00000535, 0x00000000},
{0x00000539, 0x00000000}, {0x00000539, 0x00000000},
{0x0000053D, 0x00000000} {0x0000053D, 0x00000000}
...@@ -907,48 +904,48 @@ static unsigned nv10TablePRAMIN_15BPP[][2] = ...@@ -907,48 +904,48 @@ static unsigned nv10TablePRAMIN_15BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000901}, {0x00000509, 0x00000902},
{0x0000050D, 0x00000901}, {0x0000050D, 0x00000902},
{0x00000511, 0x00000801}, {0x00000511, 0x00000802},
{0x00000515, 0x00000901}, {0x00000515, 0x00000902},
{0x00000519, 0x00000901}, {0x00000519, 0x00000902},
{0x0000051D, 0x00000901}, {0x0000051D, 0x00000902},
{0x0000052D, 0x00000901}, {0x0000052D, 0x00000902},
{0x0000052E, 0x00000901}, {0x0000052E, 0x00000902},
{0x00000535, 0x00000901}, {0x00000535, 0x00000902},
{0x00000539, 0x00000901}, {0x00000539, 0x00000902},
{0x0000053D, 0x00000901} {0x0000053D, 0x00000902}
}; };
static unsigned nv10TablePRAMIN_16BPP[][2] = static unsigned nv10TablePRAMIN_16BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000C01}, {0x00000509, 0x00000C02},
{0x0000050D, 0x00000C01}, {0x0000050D, 0x00000C02},
{0x00000511, 0x00000B01}, {0x00000511, 0x00000B02},
{0x00000515, 0x00000C01}, {0x00000515, 0x00000C02},
{0x00000519, 0x00000C01}, {0x00000519, 0x00000C02},
{0x0000051D, 0x00000C01}, {0x0000051D, 0x00000C02},
{0x0000052D, 0x00000C01}, {0x0000052D, 0x00000C02},
{0x0000052E, 0x00000C01}, {0x0000052E, 0x00000C02},
{0x00000535, 0x00000C01}, {0x00000535, 0x00000C02},
{0x00000539, 0x00000C01}, {0x00000539, 0x00000C02},
{0x0000053D, 0x00000C01} {0x0000053D, 0x00000C02}
}; };
static unsigned nv10TablePRAMIN_32BPP[][2] = static unsigned nv10TablePRAMIN_32BPP[][2] =
{ {
/* 0xXXXXXX01 For MSB mono format */ /* 0xXXXXXX01 For MSB mono format */
/* 0xXXXXXX02 For LSB mono format */ /* 0xXXXXXX02 For LSB mono format */
{0x00000509, 0x00000E01}, {0x00000509, 0x00000E02},
{0x0000050D, 0x00000E01}, {0x0000050D, 0x00000E02},
{0x00000511, 0x00000D01}, {0x00000511, 0x00000D02},
{0x00000515, 0x00000E01}, {0x00000515, 0x00000E02},
{0x00000519, 0x00000E01}, {0x00000519, 0x00000E02},
{0x0000051D, 0x00000E01}, {0x0000051D, 0x00000E02},
{0x0000052D, 0x00000E01}, {0x0000052D, 0x00000E02},
{0x0000052E, 0x00000E01}, {0x0000052E, 0x00000E02},
{0x00000535, 0x00000E01}, {0x00000535, 0x00000E02},
{0x00000539, 0x00000E01}, {0x00000539, 0x00000E02},
{0x0000053D, 0x00000E01} {0x0000053D, 0x00000E02}
}; };
include/video/aty128.h
View file @ 8f1c76f6
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#define CLOCK_CNTL_DATA 0x000c #define CLOCK_CNTL_DATA 0x000c
#define BIOS_0_SCRATCH 0x0010 #define BIOS_0_SCRATCH 0x0010
#define BUS_CNTL 0x0030 #define BUS_CNTL 0x0030
#define BUS_CNTL1 0x0034
#define GEN_INT_CNTL 0x0040 #define GEN_INT_CNTL 0x0040
#define CRTC_GEN_CNTL 0x0050 #define CRTC_GEN_CNTL 0x0050
#define CRTC_EXT_CNTL 0x0054 #define CRTC_EXT_CNTL 0x0054
...@@ -24,6 +25,7 @@ ...@@ -24,6 +25,7 @@
#define GEN_RESET_CNTL 0x00f0 #define GEN_RESET_CNTL 0x00f0
#define CONFIG_MEMSIZE 0x00f8 #define CONFIG_MEMSIZE 0x00f8
#define MEM_CNTL 0x0140 #define MEM_CNTL 0x0140
#define MEM_POWER_MISC 0x015c
#define AGP_BASE 0x0170 #define AGP_BASE 0x0170
#define AGP_CNTL 0x0174 #define AGP_CNTL 0x0174
#define AGP_APER_OFFSET 0x0178 #define AGP_APER_OFFSET 0x0178
...@@ -37,6 +39,9 @@ ...@@ -37,6 +39,9 @@
#define CRTC_H_SYNC_STRT_WID 0x0204 #define CRTC_H_SYNC_STRT_WID 0x0204
#define CRTC_V_TOTAL_DISP 0x0208 #define CRTC_V_TOTAL_DISP 0x0208
#define CRTC_V_SYNC_STRT_WID 0x020c #define CRTC_V_SYNC_STRT_WID 0x020c
#define CRTC_VLINE_CRNT_VLINE 0x0210
#define CRTC_CRNT_FRAME 0x0214
#define CRTC_GUI_TRIG_VLINE 0x0218
#define CRTC_OFFSET 0x0224 #define CRTC_OFFSET 0x0224
#define CRTC_OFFSET_CNTL 0x0228 #define CRTC_OFFSET_CNTL 0x0228
#define CRTC_PITCH 0x022c #define CRTC_PITCH 0x022c
...@@ -48,6 +53,20 @@ ...@@ -48,6 +53,20 @@
#define DDA_ON_OFF 0x02e4 #define DDA_ON_OFF 0x02e4
#define VGA_DDA_CONFIG 0x02e8 #define VGA_DDA_CONFIG 0x02e8
#define VGA_DDA_ON_OFF 0x02ec #define VGA_DDA_ON_OFF 0x02ec
#define CRTC2_H_TOTAL_DISP 0x0300
#define CRTC2_H_SYNC_STRT_WID 0x0304
#define CRTC2_V_TOTAL_DISP 0x0308
#define CRTC2_V_SYNC_STRT_WID 0x030c
#define CRTC2_VLINE_CRNT_VLINE 0x0310
#define CRTC2_CRNT_FRAME 0x0314
#define CRTC2_GUI_TRIG_VLINE 0x0318
#define CRTC2_OFFSET 0x0324
#define CRTC2_OFFSET_CNTL 0x0328
#define CRTC2_PITCH 0x032c
#define DDA2_CONFIG 0x03e0
#define DDA2_ON_OFF 0x03e4
#define CRTC2_GEN_CNTL 0x03f8
#define CRTC2_STATUS 0x03fc
#define OV0_SCALE_CNTL 0x0420 #define OV0_SCALE_CNTL 0x0420
#define SUBPIC_CNTL 0x0540 #define SUBPIC_CNTL 0x0540
#define PM4_BUFFER_OFFSET 0x0700 #define PM4_BUFFER_OFFSET 0x0700
...@@ -237,6 +256,10 @@ ...@@ -237,6 +256,10 @@
#define AGP_PLL_CNTL 0x0010 #define AGP_PLL_CNTL 0x0010
#define FCP_CNTL 0x0012 #define FCP_CNTL 0x0012
#define PLL_TEST_CNTL 0x0013 #define PLL_TEST_CNTL 0x0013
#define P2PLL_CNTL 0x002a
#define P2PLL_REF_DIV 0x002b
#define P2PLL_DIV_0 0x002b
#define POWER_MANAGEMENT 0x002f
#define PPLL_RESET 0x01 #define PPLL_RESET 0x01
#define PPLL_ATOMIC_UPDATE_EN 0x10000 #define PPLL_ATOMIC_UPDATE_EN 0x10000
...@@ -254,6 +277,14 @@ ...@@ -254,6 +277,14 @@
/* CRTC control values (CRTC_GEN_CNTL) */ /* CRTC control values (CRTC_GEN_CNTL) */
#define CRTC_CSYNC_EN 0x00000010 #define CRTC_CSYNC_EN 0x00000010
#define CRTC2_DBL_SCAN_EN 0x00000001
#define CRTC2_DISPLAY_DIS 0x00800000
#define CRTC2_FIFO_EXTSENSE 0x00200000
#define CRTC2_ICON_EN 0x00100000
#define CRTC2_CUR_EN 0x00010000
#define CRTC2_EN 0x02000000
#define CRTC2_DISP_REQ_EN_B 0x04000000
#define CRTC_PIX_WIDTH_MASK 0x00000700 #define CRTC_PIX_WIDTH_MASK 0x00000700
#define CRTC_PIX_WIDTH_4BPP 0x00000100 #define CRTC_PIX_WIDTH_4BPP 0x00000100
#define CRTC_PIX_WIDTH_8BPP 0x00000200 #define CRTC_PIX_WIDTH_8BPP 0x00000200
...@@ -262,15 +293,19 @@ ...@@ -262,15 +293,19 @@
#define CRTC_PIX_WIDTH_24BPP 0x00000500 #define CRTC_PIX_WIDTH_24BPP 0x00000500
#define CRTC_PIX_WIDTH_32BPP 0x00000600 #define CRTC_PIX_WIDTH_32BPP 0x00000600
/* DAC_CNTL bit constants */ /* DAC_CNTL bit constants */
#define DAC_8BIT_EN 0x00000100 #define DAC_8BIT_EN 0x00000100
#define DAC_MASK 0xFF000000 #define DAC_MASK 0xFF000000
#define DAC_BLANKING 0x00000004 #define DAC_BLANKING 0x00000004
#define DAC_RANGE_CNTL 0x00000003 #define DAC_RANGE_CNTL 0x00000003
#define DAC_RANGE_CNTL 0x00000003 #define DAC_CLK_SEL 0x00000010
#define DAC_PALETTE_ACCESS_CNTL 0x00000020 #define DAC_PALETTE_ACCESS_CNTL 0x00000020
#define DAC_PALETTE2_SNOOP_EN 0x00000040
#define DAC_PDWN 0x00008000 #define DAC_PDWN 0x00008000
/* CRTC_EXT_CNTL */
#define CRT_CRTC_ON 0x00008000
/* GEN_RESET_CNTL bit constants */ /* GEN_RESET_CNTL bit constants */
#define SOFT_RESET_GUI 0x00000001 #define SOFT_RESET_GUI 0x00000001
#define SOFT_RESET_VCLK 0x00000100 #define SOFT_RESET_VCLK 0x00000100
...@@ -279,8 +314,8 @@ ...@@ -279,8 +314,8 @@
#define SOFT_RESET_DISPENG_XCLK 0x00000800 #define SOFT_RESET_DISPENG_XCLK 0x00000800
/* PC_GUI_CTLSTAT bit constants */ /* PC_GUI_CTLSTAT bit constants */
#define PC_BUSY_INIT 0x10000000 #define PC_BUSY_INIT 0x10000000
#define PC_BUSY_GUI 0x20000000 #define PC_BUSY_GUI 0x20000000
#define PC_BUSY_NGUI 0x40000000 #define PC_BUSY_NGUI 0x40000000
#define PC_BUSY 0x80000000 #define PC_BUSY 0x80000000
...@@ -348,5 +383,37 @@ ...@@ -348,5 +383,37 @@
#define LVDS_BL_MOD_EN 0x00010000 #define LVDS_BL_MOD_EN 0x00010000
#define LVDS_DIGION 0x00040000 #define LVDS_DIGION 0x00040000
#define LVDS_BLON 0x00080000 #define LVDS_BLON 0x00080000
#define LVDS_ON 0x00000001
#define LVDS_DISPLAY_DIS 0x00000002
#define LVDS_PANEL_TYPE_2PIX_PER_CLK 0x00000004
#define LVDS_PANEL_24BITS_TFT 0x00000008
#define LVDS_FRAME_MOD_NO 0x00000000
#define LVDS_FRAME_MOD_2_LEVELS 0x00000010
#define LVDS_FRAME_MOD_4_LEVELS 0x00000020
#define LVDS_RST_FM 0x00000040
#define LVDS_EN 0x00000080
/* CRTC2_GEN_CNTL constants */
#define CRTC2_EN 0x02000000
/* POWER_MANAGEMENT constants */
#define PWR_MGT_ON 0x00000001
#define PWR_MGT_MODE_MASK 0x00000006
#define PWR_MGT_MODE_PIN 0x00000000
#define PWR_MGT_MODE_REGISTER 0x00000002
#define PWR_MGT_MODE_TIMER 0x00000004
#define PWR_MGT_MODE_PCI 0x00000006
#define PWR_MGT_AUTO_PWR_UP_EN 0x00000008
#define PWR_MGT_ACTIVITY_PIN_ON 0x00000010
#define PWR_MGT_STANDBY_POL 0x00000020
#define PWR_MGT_SUSPEND_POL 0x00000040
#define PWR_MGT_SELF_REFRESH 0x00000080
#define PWR_MGT_ACTIVITY_PIN_EN 0x00000100
#define PWR_MGT_KEYBD_SNOOP 0x00000200
#define PWR_MGT_TRISTATE_MEM_EN 0x00000800
#define PWR_MGT_SELW4MS 0x00001000
#define PWR_MGT_SLOWDOWN_MCLK 0x00002000
#define PMI_PMSCR_REG 0x60
#endif /* REG_RAGE128_H */ #endif /* REG_RAGE128_H */
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