Commit 8fef9d96 authored by Max Thrun's avatar Max Thrun Committed by Mauro Carvalho Chehab

V4L/DVB: gspca - ov534: Fix Auto White Balance control

Set only the needed bits for AWB, and enable it by default.
Signed-off-by: default avatarMax Thrun <bear24rw@gmail.com>
Signed-off-by: default avatarAntonio Ospite <ospite@studenti.unina.it>
Signed-off-by: default avatarJean-François Moine <moinejf@free.fr>
Signed-off-by: default avatarMauro Carvalho Chehab <mchehab@redhat.com>
parent 18cf8c91
...@@ -171,7 +171,7 @@ static const struct ctrl sd_ctrls[] = { ...@@ -171,7 +171,7 @@ static const struct ctrl sd_ctrls[] = {
.minimum = 0, .minimum = 0,
.maximum = 1, .maximum = 1,
.step = 1, .step = 1,
#define AWB_DEF 0 #define AWB_DEF 1
.default_value = AWB_DEF, .default_value = AWB_DEF,
}, },
.set = sd_setawb, .set = sd_setawb,
...@@ -723,10 +723,17 @@ static void setawb(struct gspca_dev *gspca_dev) ...@@ -723,10 +723,17 @@ static void setawb(struct gspca_dev *gspca_dev)
{ {
struct sd *sd = (struct sd *) gspca_dev; struct sd *sd = (struct sd *) gspca_dev;
if (sd->awb) if (sd->awb) {
sccb_reg_write(gspca_dev, 0x63, 0xe0); /* AWB on */ sccb_reg_write(gspca_dev, 0x13,
else sccb_reg_read(gspca_dev, 0x13) | 0x02);
sccb_reg_write(gspca_dev, 0x63, 0xaa); /* AWB off */ sccb_reg_write(gspca_dev, 0x63,
sccb_reg_read(gspca_dev, 0x63) | 0xc0);
} else {
sccb_reg_write(gspca_dev, 0x13,
sccb_reg_read(gspca_dev, 0x13) & ~0x02);
sccb_reg_write(gspca_dev, 0x63,
sccb_reg_read(gspca_dev, 0x63) & ~0xc0);
}
} }
static void setaec(struct gspca_dev *gspca_dev) static void setaec(struct gspca_dev *gspca_dev)
...@@ -805,9 +812,7 @@ static int sd_config(struct gspca_dev *gspca_dev, ...@@ -805,9 +812,7 @@ static int sd_config(struct gspca_dev *gspca_dev,
#else #else
gspca_dev->ctrl_inac |= (1 << AWB_IDX); gspca_dev->ctrl_inac |= (1 << AWB_IDX);
#endif #endif
#if AWB_DEF != 0 sd->awb = AWB_DEF;
sd->awb = AWB_DEF
#endif
sd->aec = AEC_DEF; sd->aec = AEC_DEF;
#if SHARPNESS_DEF != 0 #if SHARPNESS_DEF != 0
sd->sharpness = SHARPNESS_DEF; sd->sharpness = SHARPNESS_DEF;
......
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