Commit 92a76f6d authored by Adam Buchbinder's avatar Adam Buchbinder Committed by Ralf Baechle

MIPS: Fix misspellings in comments.

Signed-off-by: default avatarAdam Buchbinder <adam.buchbinder@gmail.com>
Cc: linux-mips@linux-mips.org
Cc: trivial@kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12617/Signed-off-by: default avatarRalf Baechle <ralf@linux-mips.org>
parent 091bc3a4
...@@ -261,7 +261,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid, ...@@ -261,7 +261,7 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
au1x_dma_chan_t *cp; au1x_dma_chan_t *cp;
/* /*
* We do the intialization on the first channel allocation. * We do the initialization on the first channel allocation.
* We have to wait because of the interrupt handler initialization * We have to wait because of the interrupt handler initialization
* which can't be done successfully during board set up. * which can't be done successfully during board set up.
*/ */
...@@ -964,7 +964,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr) ...@@ -964,7 +964,7 @@ u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr)
dp->dscr_source1 = dscr->dscr_source1; dp->dscr_source1 = dscr->dscr_source1;
dp->dscr_cmd1 = dscr->dscr_cmd1; dp->dscr_cmd1 = dscr->dscr_cmd1;
nbytes = dscr->dscr_cmd1; nbytes = dscr->dscr_cmd1;
/* Allow the caller to specifiy if an interrupt is generated */ /* Allow the caller to specify if an interrupt is generated */
dp->dscr_cmd0 &= ~DSCR_CMD0_IE; dp->dscr_cmd0 &= ~DSCR_CMD0_IE;
dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V; dp->dscr_cmd0 |= dscr->dscr_cmd0 | DSCR_CMD0_V;
ctp->chan_ptr->ddma_dbell = 0; ctp->chan_ptr->ddma_dbell = 0;
......
...@@ -68,7 +68,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -68,7 +68,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
gmx_rx_int_en.s.pause_drp = 1; gmx_rx_int_en.s.pause_drp = 1;
/* Skipping gmx_rx_int_en.s.reserved_16_18 */ /* Skipping gmx_rx_int_en.s.reserved_16_18 */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -89,7 +89,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -89,7 +89,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -112,7 +112,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -112,7 +112,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -134,7 +134,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -134,7 +134,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -156,7 +156,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -156,7 +156,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -179,7 +179,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -179,7 +179,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
/*gmx_rx_int_en.s.phy_spd = 1; */ /*gmx_rx_int_en.s.phy_spd = 1; */
/*gmx_rx_int_en.s.phy_link = 1; */ /*gmx_rx_int_en.s.phy_link = 1; */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
...@@ -209,7 +209,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block) ...@@ -209,7 +209,7 @@ void __cvmx_interrupt_gmxx_rxx_int_en_enable(int index, int block)
gmx_rx_int_en.s.pause_drp = 1; gmx_rx_int_en.s.pause_drp = 1;
/* Skipping gmx_rx_int_en.s.reserved_16_18 */ /* Skipping gmx_rx_int_en.s.reserved_16_18 */
/*gmx_rx_int_en.s.ifgerr = 1; */ /*gmx_rx_int_en.s.ifgerr = 1; */
/*gmx_rx_int_en.s.coldet = 1; // Collsion detect */ /*gmx_rx_int_en.s.coldet = 1; // Collision detect */
/*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */ /*gmx_rx_int_en.s.falerr = 1; // False carrier error or extend error after slottime */
/*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */ /*gmx_rx_int_en.s.rsverr = 1; // RGMII reserved opcodes */
/*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */ /*gmx_rx_int_en.s.pcterr = 1; // Bad Preamble / Protocol */
......
...@@ -189,7 +189,7 @@ void cvmx_pko_initialize_global(void) ...@@ -189,7 +189,7 @@ void cvmx_pko_initialize_global(void)
/* /*
* Set the size of the PKO command buffers to an odd number of * Set the size of the PKO command buffers to an odd number of
* 64bit words. This allows the normal two word send to stay * 64bit words. This allows the normal two word send to stay
* aligned and never span a comamnd word buffer. * aligned and never span a command word buffer.
*/ */
config.u64 = 0; config.u64 = 0;
config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL; config.s.pool = CVMX_FPA_OUTPUT_BUFFER_POOL;
......
...@@ -331,7 +331,7 @@ static int octeon_update_boot_vector(unsigned int cpu) ...@@ -331,7 +331,7 @@ static int octeon_update_boot_vector(unsigned int cpu)
} }
if (!(avail_coremask & (1 << coreid))) { if (!(avail_coremask & (1 << coreid))) {
/* core not available, assume, that catched by simple-executive */ /* core not available, assume, that caught by simple-executive */
cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid); cvmx_write_csr(CVMX_CIU_PP_RST, 1 << coreid);
cvmx_write_csr(CVMX_CIU_PP_RST, 0); cvmx_write_csr(CVMX_CIU_PP_RST, 0);
} }
......
...@@ -5,7 +5,7 @@ ...@@ -5,7 +5,7 @@
* Written by Ralf Baechle and Andreas Busse, modified for DECstation * Written by Ralf Baechle and Andreas Busse, modified for DECstation
* support by Paul Antoine and Harald Koerfgen. * support by Paul Antoine and Harald Koerfgen.
* *
* completly rewritten: * completely rewritten:
* Copyright (C) 1998 Harald Koerfgen * Copyright (C) 1998 Harald Koerfgen
* *
* Rewritten extensively for controller-driven IRQ support * Rewritten extensively for controller-driven IRQ support
......
...@@ -9,7 +9,7 @@ ...@@ -9,7 +9,7 @@
* PROM library functions for acquiring/using memory descriptors given to us * PROM library functions for acquiring/using memory descriptors given to us
* from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set * from the ARCS firmware. This is only used when CONFIG_ARC_MEMORY is set
* because on some machines like SGI IP27 the ARC memory configuration data * because on some machines like SGI IP27 the ARC memory configuration data
* completly bogus and alternate easier to use mechanisms are available. * completely bogus and alternate easier to use mechanisms are available.
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h> #include <linux/kernel.h>
......
...@@ -141,7 +141,7 @@ ...@@ -141,7 +141,7 @@
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can safely execute C code.
*/ */
.macro smp_slave_setup .macro smp_slave_setup
.endm .endm
......
...@@ -16,7 +16,7 @@ ...@@ -16,7 +16,7 @@
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can safely execute C code.
*/ */
.macro smp_slave_setup .macro smp_slave_setup
.endm .endm
......
...@@ -11,7 +11,7 @@ ...@@ -11,7 +11,7 @@
#define __ASM_MACH_IP27_IRQ_H #define __ASM_MACH_IP27_IRQ_H
/* /*
* A hardwired interrupt number is completly stupid for this system - a * A hardwired interrupt number is completely stupid for this system - a
* large configuration might have thousands if not tenthousands of * large configuration might have thousands if not tenthousands of
* interrupts. * interrupts.
*/ */
......
...@@ -81,7 +81,7 @@ ...@@ -81,7 +81,7 @@
.endm .endm
/* /*
* Do SMP slave processor setup necessary before we can savely execute C code. * Do SMP slave processor setup necessary before we can safely execute C code.
*/ */
.macro smp_slave_setup .macro smp_slave_setup
GET_NASID_ASM t1 GET_NASID_ASM t1
......
...@@ -27,7 +27,7 @@ enum jz_gpio_function { ...@@ -27,7 +27,7 @@ enum jz_gpio_function {
/* /*
Usually a driver for a SoC component has to request several gpio pins and Usually a driver for a SoC component has to request several gpio pins and
configure them as funcion pins. configure them as function pins.
jz_gpio_bulk_request can be used to ease this process. jz_gpio_bulk_request can be used to ease this process.
Usually one would do something like: Usually one would do something like:
......
...@@ -28,7 +28,7 @@ extern void __iomem *mips_cm_l2sync_base; ...@@ -28,7 +28,7 @@ extern void __iomem *mips_cm_l2sync_base;
* This function returns the physical base address of the Coherence Manager * This function returns the physical base address of the Coherence Manager
* global control block, or 0 if no Coherence Manager is present. It provides * global control block, or 0 if no Coherence Manager is present. It provides
* a default implementation which reads the CMGCRBase register where available, * a default implementation which reads the CMGCRBase register where available,
* and may be overriden by platforms which determine this address in a * and may be overridden by platforms which determine this address in a
* different way by defining a function with the same prototype except for the * different way by defining a function with the same prototype except for the
* name mips_cm_phys_base (without underscores). * name mips_cm_phys_base (without underscores).
*/ */
......
...@@ -33,7 +33,7 @@ ...@@ -33,7 +33,7 @@
/* Packet buffers */ /* Packet buffers */
#define CVMX_FPA_PACKET_POOL (0) #define CVMX_FPA_PACKET_POOL (0)
#define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE #define CVMX_FPA_PACKET_POOL_SIZE CVMX_FPA_POOL_0_SIZE
/* Work queue entrys */ /* Work queue entries */
#define CVMX_FPA_WQE_POOL (1) #define CVMX_FPA_WQE_POOL (1)
#define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE #define CVMX_FPA_WQE_POOL_SIZE CVMX_FPA_POOL_1_SIZE
/* PKO queue command buffers */ /* PKO queue command buffers */
......
...@@ -189,7 +189,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr) ...@@ -189,7 +189,7 @@ static inline uint64_t cvmx_ptr_to_phys(void *ptr)
static inline void *cvmx_phys_to_ptr(uint64_t physical_address) static inline void *cvmx_phys_to_ptr(uint64_t physical_address)
{ {
if (sizeof(void *) == 8) { if (sizeof(void *) == 8) {
/* Just set the top bit, avoiding any TLB uglyness */ /* Just set the top bit, avoiding any TLB ugliness */
return CASTPTR(void, return CASTPTR(void,
CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS, CVMX_ADD_SEG(CVMX_MIPS_SPACE_XKPHYS,
physical_address)); physical_address));
......
...@@ -269,16 +269,16 @@ typedef struct bridge_err_cmdword_s { ...@@ -269,16 +269,16 @@ typedef struct bridge_err_cmdword_s {
union { union {
u32 cmd_word; u32 cmd_word;
struct { struct {
u32 didn:4, /* Destination ID */ u32 didn:4, /* Destination ID */
sidn:4, /* Source ID */ sidn:4, /* Source ID */
pactyp:4, /* Packet type */ pactyp:4, /* Packet type */
tnum:5, /* Trans Number */ tnum:5, /* Trans Number */
coh:1, /* Coh Transacti */ coh:1, /* Coh Transaction */
ds:2, /* Data size */ ds:2, /* Data size */
gbr:1, /* GBR enable */ gbr:1, /* GBR enable */
vbpm:1, /* VBPM message */ vbpm:1, /* VBPM message */
error:1, /* Error occurred */ error:1, /* Error occurred */
barr:1, /* Barrier op */ barr:1, /* Barrier op */
rsvd:8; rsvd:8;
} berr_st; } berr_st;
} berr_un; } berr_un;
......
...@@ -147,7 +147,7 @@ struct hpc3_ethregs { ...@@ -147,7 +147,7 @@ struct hpc3_ethregs {
#define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */ #define HPC3_EPCFG_P1 0x000f /* Cycles to spend in P1 state for PIO */
#define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */ #define HPC3_EPCFG_P2 0x00f0 /* Cycles to spend in P2 state for PIO */
#define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */ #define HPC3_EPCFG_P3 0x0f00 /* Cycles to spend in P3 state for PIO */
#define HPC3_EPCFG_TST 0x1000 /* Diagnistic ram test feature bit */ #define HPC3_EPCFG_TST 0x1000 /* Diagnostic ram test feature bit */
u32 _unused2[0x1000/4 - 8]; /* padding */ u32 _unused2[0x1000/4 - 8]; /* padding */
......
...@@ -144,7 +144,7 @@ struct linux_tinfo { ...@@ -144,7 +144,7 @@ struct linux_tinfo {
struct linux_vdirent { struct linux_vdirent {
ULONG namelen; ULONG namelen;
unsigned char attr; unsigned char attr;
char fname[32]; /* XXX imperical, should be a define */ char fname[32]; /* XXX empirical, should be a define */
}; };
/* Other stuff for files. */ /* Other stuff for files. */
...@@ -179,7 +179,7 @@ struct linux_finfo { ...@@ -179,7 +179,7 @@ struct linux_finfo {
enum linux_devtypes dtype; enum linux_devtypes dtype;
unsigned long namelen; unsigned long namelen;
unsigned char attr; unsigned char attr;
char name[32]; /* XXX imperical, should be define */ char name[32]; /* XXX empirical, should be define */
}; };
/* This describes the vector containing function pointers to the ARC /* This describes the vector containing function pointers to the ARC
......
...@@ -355,7 +355,7 @@ struct ioc3_etxd { ...@@ -355,7 +355,7 @@ struct ioc3_etxd {
#define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */ #define SSCR_PAUSE_STATE 0x40000000 /* sets when PAUSE takes effect */
#define SSCR_RESET 0x80000000 /* reset DMA channels */ #define SSCR_RESET 0x80000000 /* reset DMA channels */
/* all producer/comsumer pointers are the same bitfield */ /* all producer/consumer pointers are the same bitfield */
#define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */ #define PROD_CONS_PTR_4K 0x00000ff8 /* for 4K buffers */
#define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */ #define PROD_CONS_PTR_1K 0x000003f8 /* for 1K buffers */
#define PROD_CONS_PTR_OFF 3 #define PROD_CONS_PTR_OFF 3
......
...@@ -628,7 +628,7 @@ typedef union h1_icrbb_u { ...@@ -628,7 +628,7 @@ typedef union h1_icrbb_u {
/* /*
* Values for field imsgtype * Values for field imsgtype
*/ */
#define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Meessage from Xtalk */ #define IIO_ICRB_IMSGT_XTALK 0 /* Incoming Message from Xtalk */
#define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */ #define IIO_ICRB_IMSGT_BTE 1 /* Incoming message from BTE */
#define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */ #define IIO_ICRB_IMSGT_SN0NET 2 /* Incoming message from SN0 net */
#define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */ #define IIO_ICRB_IMSGT_CRB 3 /* Incoming message from CRB ??? */
......
...@@ -95,7 +95,7 @@ static inline bool eva_kernel_access(void) ...@@ -95,7 +95,7 @@ static inline bool eva_kernel_access(void)
} }
/* /*
* Is a address valid? This does a straighforward calculation rather * Is a address valid? This does a straightforward calculation rather
* than tests. * than tests.
* *
* Address valid if: * Address valid if:
......
...@@ -24,7 +24,7 @@ static char *cm2_tr[8] = { ...@@ -24,7 +24,7 @@ static char *cm2_tr[8] = {
"0x04", "cpc", "0x06", "0x07" "0x04", "cpc", "0x06", "0x07"
}; };
/* CM3 Tag ECC transation type */ /* CM3 Tag ECC transaction type */
static char *cm3_tr[16] = { static char *cm3_tr[16] = {
[0x0] = "ReqNoData", [0x0] = "ReqNoData",
[0x1] = "0x1", [0x1] = "0x1",
......
...@@ -530,7 +530,7 @@ static void mipspmu_enable(struct pmu *pmu) ...@@ -530,7 +530,7 @@ static void mipspmu_enable(struct pmu *pmu)
/* /*
* MIPS performance counters can be per-TC. The control registers can * MIPS performance counters can be per-TC. The control registers can
* not be directly accessed accross CPUs. Hence if we want to do global * not be directly accessed across CPUs. Hence if we want to do global
* control, we need cross CPU calls. on_each_cpu() can help us, but we * control, we need cross CPU calls. on_each_cpu() can help us, but we
* can not make sure this function is called with interrupts enabled. So * can not make sure this function is called with interrupts enabled. So
* here we pause local counters and then grab a rwlock and leave the * here we pause local counters and then grab a rwlock and leave the
......
...@@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state) ...@@ -472,7 +472,7 @@ static void * __init cps_gen_entry_code(unsigned cpu, enum cps_pm_state state)
/* /*
* Disable all but self interventions. The load from COHCTL is defined * Disable all but self interventions. The load from COHCTL is defined
* by the interAptiv & proAptiv SUMs as ensuring that the operation * by the interAptiv & proAptiv SUMs as ensuring that the operation
* resulting from the preceeding store is complete. * resulting from the preceding store is complete.
*/ */
uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core); uasm_i_addiu(&p, t0, zero, 1 << cpu_data[cpu].core);
uasm_i_sw(&p, t0, 0, r_pcohctl); uasm_i_sw(&p, t0, 0, r_pcohctl);
......
...@@ -615,7 +615,7 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value) ...@@ -615,7 +615,7 @@ int mips_set_process_fp_mode(struct task_struct *task, unsigned int value)
* allows us to only worry about whether an FP mode switch is in * allows us to only worry about whether an FP mode switch is in
* progress when FP is first used in a tasks time slice. Pretty much all * progress when FP is first used in a tasks time slice. Pretty much all
* of the mode switch overhead can thus be confined to cases where mode * of the mode switch overhead can thus be confined to cases where mode
* switches are actually occuring. That is, to here. However for the * switches are actually occurring. That is, to here. However for the
* thread performing the mode switch it may take a while... * thread performing the mode switch it may take a while...
*/ */
if (num_online_cpus() > 1) { if (num_online_cpus() > 1) {
......
...@@ -2214,7 +2214,7 @@ void __init trap_init(void) ...@@ -2214,7 +2214,7 @@ void __init trap_init(void)
/* /*
* Copy the generic exception handlers to their final destination. * Copy the generic exception handlers to their final destination.
* This will be overriden later as suitable for a particular * This will be overridden later as suitable for a particular
* configuration. * configuration.
*/ */
set_handler(0x180, &except_vec3_generic, 0x80); set_handler(0x180, &except_vec3_generic, 0x80);
......
...@@ -632,7 +632,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu) ...@@ -632,7 +632,7 @@ void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu); kvm_debug("%s: vcpu %p, cpu: %d\n", __func__, vcpu, cpu);
/* Alocate new kernel and user ASIDs if needed */ /* Allocate new kernel and user ASIDs if needed */
local_irq_save(flags); local_irq_save(flags);
......
...@@ -500,7 +500,7 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu) ...@@ -500,7 +500,7 @@ static int kvm_trap_emul_vcpu_setup(struct kvm_vcpu *vcpu)
kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10)); kvm_write_c0_guest_config7(cop0, (MIPS_CONF7_WII) | (1 << 10));
/* /*
* Setup IntCtl defaults, compatibilty mode for timer interrupts (HW5) * Setup IntCtl defaults, compatibility mode for timer interrupts (HW5)
*/ */
kvm_write_c0_guest_intctl(cop0, 0xFC000000); kvm_write_c0_guest_intctl(cop0, 0xFC000000);
......
...@@ -97,7 +97,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) ...@@ -97,7 +97,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
{ {
assert(xm); /* we don't gen exact zeros (probably should) */ assert(xm); /* we don't gen exact zeros (probably should) */
assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no execess */ assert((xm >> (DP_FBITS + 1 + 3)) == 0); /* no excess */
assert(xm & (DP_HIDDEN_BIT << 3)); assert(xm & (DP_HIDDEN_BIT << 3));
if (xe < DP_EMIN) { if (xe < DP_EMIN) {
...@@ -165,7 +165,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) ...@@ -165,7 +165,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
/* strip grs bits */ /* strip grs bits */
xm >>= 3; xm >>= 3;
assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
assert(xe >= DP_EMIN); assert(xe >= DP_EMIN);
if (xe > DP_EMAX) { if (xe > DP_EMAX) {
...@@ -198,7 +198,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm) ...@@ -198,7 +198,7 @@ union ieee754dp ieee754dp_format(int sn, int xe, u64 xm)
ieee754_setcx(IEEE754_UNDERFLOW); ieee754_setcx(IEEE754_UNDERFLOW);
return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm); return builddp(sn, DP_EMIN - 1 + DP_EBIAS, xm);
} else { } else {
assert((xm >> (DP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (DP_FBITS + 1)) == 0); /* no excess */
assert(xm & DP_HIDDEN_BIT); assert(xm & DP_HIDDEN_BIT);
return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT); return builddp(sn, xe + DP_EBIAS, xm & ~DP_HIDDEN_BIT);
......
...@@ -97,7 +97,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) ...@@ -97,7 +97,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
{ {
assert(xm); /* we don't gen exact zeros (probably should) */ assert(xm); /* we don't gen exact zeros (probably should) */
assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no execess */ assert((xm >> (SP_FBITS + 1 + 3)) == 0); /* no excess */
assert(xm & (SP_HIDDEN_BIT << 3)); assert(xm & (SP_HIDDEN_BIT << 3));
if (xe < SP_EMIN) { if (xe < SP_EMIN) {
...@@ -163,7 +163,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) ...@@ -163,7 +163,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
/* strip grs bits */ /* strip grs bits */
xm >>= 3; xm >>= 3;
assert((xm >> (SP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
assert(xe >= SP_EMIN); assert(xe >= SP_EMIN);
if (xe > SP_EMAX) { if (xe > SP_EMAX) {
...@@ -196,7 +196,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm) ...@@ -196,7 +196,7 @@ union ieee754sp ieee754sp_format(int sn, int xe, unsigned xm)
ieee754_setcx(IEEE754_UNDERFLOW); ieee754_setcx(IEEE754_UNDERFLOW);
return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm); return buildsp(sn, SP_EMIN - 1 + SP_EBIAS, xm);
} else { } else {
assert((xm >> (SP_FBITS + 1)) == 0); /* no execess */ assert((xm >> (SP_FBITS + 1)) == 0); /* no excess */
assert(xm & SP_HIDDEN_BIT); assert(xm & SP_HIDDEN_BIT);
return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT); return buildsp(sn, xe + SP_EBIAS, xm & ~SP_HIDDEN_BIT);
......
...@@ -158,7 +158,7 @@ static inline int __init indy_sc_probe(void) ...@@ -158,7 +158,7 @@ static inline int __init indy_sc_probe(void)
return 1; return 1;
} }
/* XXX Check with wje if the Indy caches can differenciate between /* XXX Check with wje if the Indy caches can differentiate between
writeback + invalidate and just invalidate. */ writeback + invalidate and just invalidate. */
static struct bcache_ops indy_sc_ops = { static struct bcache_ops indy_sc_ops = {
.bc_enable = indy_sc_enable, .bc_enable = indy_sc_enable,
......
...@@ -12,7 +12,7 @@ ...@@ -12,7 +12,7 @@
* Copyright (C) 2011 MIPS Technologies, Inc. * Copyright (C) 2011 MIPS Technologies, Inc.
* *
* ... and the days got worse and worse and now you see * ... and the days got worse and worse and now you see
* I've gone completly out of my mind. * I've gone completely out of my mind.
* *
* They're coming to take me a away haha * They're coming to take me a away haha
* they're coming to take me a away hoho hihi haha * they're coming to take me a away hoho hihi haha
......
...@@ -7,7 +7,7 @@ ...@@ -7,7 +7,7 @@
* Copyright (C) 2000 by Silicon Graphics, Inc. * Copyright (C) 2000 by Silicon Graphics, Inc.
* Copyright (C) 2004 by Christoph Hellwig * Copyright (C) 2004 by Christoph Hellwig
* *
* On SGI IP27 the ARC memory configuration data is completly bogus but * On SGI IP27 the ARC memory configuration data is completely bogus but
* alternate easier to use mechanisms are available. * alternate easier to use mechanisms are available.
*/ */
#include <linux/init.h> #include <linux/init.h>
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment