Commit 92f4beb7 authored by Keyon Jie's avatar Keyon Jie Committed by Mark Brown

ASoC: SOF: Intel: HDA: use macro for register polling retry count

Define macro and use it for the register polling retry count.
Signed-off-by: default avatarKeyon Jie <yang.jie@linux.intel.com>
Signed-off-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Link: https://lore.kernel.org/r/20191025224122.7718-12-pierre-louis.bossart@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent aae7c82d
...@@ -323,12 +323,11 @@ int hda_dsp_set_power_state(struct snd_sof_dev *sdev, ...@@ -323,12 +323,11 @@ int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
enum sof_d0_substate d0_substate) enum sof_d0_substate d0_substate)
{ {
struct hdac_bus *bus = sof_to_bus(sdev); struct hdac_bus *bus = sof_to_bus(sdev);
int retry = 50;
int ret; int ret;
u8 value; u8 value;
/* Write to D0I3C after Command-In-Progress bit is cleared */ /* Write to D0I3C after Command-In-Progress bit is cleared */
ret = hda_dsp_wait_d0i3c_done(sdev, retry); ret = hda_dsp_wait_d0i3c_done(sdev, HDA_DSP_REG_POLL_RETRY_COUNT);
if (ret < 0) { if (ret < 0) {
dev_err(bus->dev, "CIP timeout before D0I3C update!\n"); dev_err(bus->dev, "CIP timeout before D0I3C update!\n");
return ret; return ret;
...@@ -339,8 +338,7 @@ int hda_dsp_set_power_state(struct snd_sof_dev *sdev, ...@@ -339,8 +338,7 @@ int hda_dsp_set_power_state(struct snd_sof_dev *sdev,
snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value); snd_hdac_chip_updateb(bus, VS_D0I3C, SOF_HDA_VS_D0I3C_I3, value);
/* Wait for cmd in progress to be cleared before exiting the function */ /* Wait for cmd in progress to be cleared before exiting the function */
retry = 50; ret = hda_dsp_wait_d0i3c_done(sdev, HDA_DSP_REG_POLL_RETRY_COUNT);
ret = hda_dsp_wait_d0i3c_done(sdev, retry);
if (ret < 0) { if (ret < 0) {
dev_err(bus->dev, "CIP timeout after D0I3C update!\n"); dev_err(bus->dev, "CIP timeout after D0I3C update!\n");
return ret; return ret;
......
...@@ -214,6 +214,7 @@ ...@@ -214,6 +214,7 @@
#define HDA_DSP_CTRL_RESET_TIMEOUT 100 #define HDA_DSP_CTRL_RESET_TIMEOUT 100
#define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */ #define HDA_DSP_WAIT_TIMEOUT 500 /* 500 msec */
#define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */ #define HDA_DSP_REG_POLL_INTERVAL_US 500 /* 0.5 msec */
#define HDA_DSP_REG_POLL_RETRY_COUNT 50
#define HDA_DSP_ADSPIC_IPC 1 #define HDA_DSP_ADSPIC_IPC 1
#define HDA_DSP_ADSPIS_IPC 1 #define HDA_DSP_ADSPIS_IPC 1
......
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