Commit 93898eb7 authored by Vladimir Zapolskiy's avatar Vladimir Zapolskiy

arm: dts: lpc32xx: add clock properties to device nodes

The change adds clock properties to all described peripheral devices,
clock ids are taken from dt-bindings/clock/lpc32xx-clock.h

Some existing drivers expect to get clock names, in those cases
clock-names are added as well.
Signed-off-by: default avatarVladimir Zapolskiy <vz@mleia.com>
parent fe86131f
...@@ -13,6 +13,8 @@ ...@@ -13,6 +13,8 @@
#include "skeleton.dtsi" #include "skeleton.dtsi"
#include <dt-bindings/clock/lpc32xx-clock.h>
/ { / {
compatible = "nxp,lpc3220"; compatible = "nxp,lpc3220";
interrupt-parent = <&mic>; interrupt-parent = <&mic>;
...@@ -57,6 +59,7 @@ ahb { ...@@ -57,6 +59,7 @@ ahb {
slc: flash@20020000 { slc: flash@20020000 {
compatible = "nxp,lpc3220-slc"; compatible = "nxp,lpc3220-slc";
reg = <0x20020000 0x1000>; reg = <0x20020000 0x1000>;
clocks = <&clk LPC32XX_CLK_SLC>;
status = "disabled"; status = "disabled";
}; };
...@@ -64,6 +67,7 @@ mlc: flash@200a8000 { ...@@ -64,6 +67,7 @@ mlc: flash@200a8000 {
compatible = "nxp,lpc3220-mlc"; compatible = "nxp,lpc3220-mlc";
reg = <0x200a8000 0x11000>; reg = <0x200a8000 0x11000>;
interrupts = <11 0>; interrupts = <11 0>;
clocks = <&clk LPC32XX_CLK_MLC>;
status = "disabled"; status = "disabled";
}; };
...@@ -71,6 +75,8 @@ dma: dma@31000000 { ...@@ -71,6 +75,8 @@ dma: dma@31000000 {
compatible = "arm,pl080", "arm,primecell"; compatible = "arm,pl080", "arm,primecell";
reg = <0x31000000 0x1000>; reg = <0x31000000 0x1000>;
interrupts = <0x1c 0>; interrupts = <0x1c 0>;
clocks = <&clk LPC32XX_CLK_DMA>;
clock-names = "apb_pclk";
}; };
usb { usb {
...@@ -110,6 +116,8 @@ clcd: clcd@31040000 { ...@@ -110,6 +116,8 @@ clcd: clcd@31040000 {
compatible = "arm,pl110", "arm,primecell"; compatible = "arm,pl110", "arm,primecell";
reg = <0x31040000 0x1000>; reg = <0x31040000 0x1000>;
interrupts = <0x0e 0>; interrupts = <0x0e 0>;
clocks = <&clk LPC32XX_CLK_LCD>;
clock-names = "apb_pclk";
status = "disabled"; status = "disabled";
}; };
...@@ -117,11 +125,14 @@ mac: ethernet@31060000 { ...@@ -117,11 +125,14 @@ mac: ethernet@31060000 {
compatible = "nxp,lpc-eth"; compatible = "nxp,lpc-eth";
reg = <0x31060000 0x1000>; reg = <0x31060000 0x1000>;
interrupts = <0x1d 0>; interrupts = <0x1d 0>;
clocks = <&clk LPC32XX_CLK_MAC>;
}; };
emc: memory-controller@31080000 { emc: memory-controller@31080000 {
compatible = "arm,pl175", "arm,primecell"; compatible = "arm,pl175", "arm,primecell";
reg = <0x31080000 0x1000>; reg = <0x31080000 0x1000>;
clocks = <&clk LPC32XX_CLK_DDRAM>, <&clk LPC32XX_CLK_DDRAM>;
clock-names = "mpmcclk", "apb_pclk";
#address-cells = <1>; #address-cells = <1>;
#size-cells = <1>; #size-cells = <1>;
...@@ -142,6 +153,8 @@ ssp0: ssp@20084000 { ...@@ -142,6 +153,8 @@ ssp0: ssp@20084000 {
compatible = "arm,pl022", "arm,primecell"; compatible = "arm,pl022", "arm,primecell";
reg = <0x20084000 0x1000>; reg = <0x20084000 0x1000>;
interrupts = <0x14 0>; interrupts = <0x14 0>;
clocks = <&clk LPC32XX_CLK_SSP0>;
clock-names = "apb_pclk";
}; };
spi1: spi@20088000 { spi1: spi@20088000 {
...@@ -153,6 +166,8 @@ ssp1: ssp@2008c000 { ...@@ -153,6 +166,8 @@ ssp1: ssp@2008c000 {
compatible = "arm,pl022", "arm,primecell"; compatible = "arm,pl022", "arm,primecell";
reg = <0x2008c000 0x1000>; reg = <0x2008c000 0x1000>;
interrupts = <0x15 0>; interrupts = <0x15 0>;
clocks = <&clk LPC32XX_CLK_SSP1>;
clock-names = "apb_pclk";
}; };
spi2: spi@20090000 { spi2: spi@20090000 {
...@@ -169,6 +184,8 @@ sd: sd@20098000 { ...@@ -169,6 +184,8 @@ sd: sd@20098000 {
compatible = "arm,pl18x", "arm,primecell"; compatible = "arm,pl18x", "arm,primecell";
reg = <0x20098000 0x1000>; reg = <0x20098000 0x1000>;
interrupts = <0x0f 0>, <0x0d 0>; interrupts = <0x0f 0>, <0x0d 0>;
clocks = <&clk LPC32XX_CLK_SD>;
clock-names = "apb_pclk";
status = "disabled"; status = "disabled";
}; };
...@@ -185,6 +202,7 @@ uart5: serial@40090000 { ...@@ -185,6 +202,7 @@ uart5: serial@40090000 {
interrupts = <9 0>; interrupts = <9 0>;
clock-frequency = <13000000>; clock-frequency = <13000000>;
reg-shift = <2>; reg-shift = <2>;
clocks = <&clk LPC32XX_CLK_UART5>;
status = "disabled"; status = "disabled";
}; };
...@@ -194,6 +212,7 @@ uart3: serial@40080000 { ...@@ -194,6 +212,7 @@ uart3: serial@40080000 {
interrupts = <7 0>; interrupts = <7 0>;
clock-frequency = <13000000>; clock-frequency = <13000000>;
reg-shift = <2>; reg-shift = <2>;
clocks = <&clk LPC32XX_CLK_UART3>;
status = "disabled"; status = "disabled";
}; };
...@@ -203,6 +222,7 @@ uart4: serial@40088000 { ...@@ -203,6 +222,7 @@ uart4: serial@40088000 {
interrupts = <8 0>; interrupts = <8 0>;
clock-frequency = <13000000>; clock-frequency = <13000000>;
reg-shift = <2>; reg-shift = <2>;
clocks = <&clk LPC32XX_CLK_UART4>;
status = "disabled"; status = "disabled";
}; };
...@@ -212,6 +232,7 @@ uart6: serial@40098000 { ...@@ -212,6 +232,7 @@ uart6: serial@40098000 {
interrupts = <10 0>; interrupts = <10 0>;
clock-frequency = <13000000>; clock-frequency = <13000000>;
reg-shift = <2>; reg-shift = <2>;
clocks = <&clk LPC32XX_CLK_UART6>;
status = "disabled"; status = "disabled";
}; };
...@@ -222,6 +243,7 @@ i2c1: i2c@400A0000 { ...@@ -222,6 +243,7 @@ i2c1: i2c@400A0000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pnx,timeout = <0x64>; pnx,timeout = <0x64>;
clocks = <&clk LPC32XX_CLK_I2C1>;
}; };
i2c2: i2c@400A8000 { i2c2: i2c@400A8000 {
...@@ -231,6 +253,7 @@ i2c2: i2c@400A8000 { ...@@ -231,6 +253,7 @@ i2c2: i2c@400A8000 {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
pnx,timeout = <0x64>; pnx,timeout = <0x64>;
clocks = <&clk LPC32XX_CLK_I2C2>;
}; };
mpwm: mpwm@400E8000 { mpwm: mpwm@400E8000 {
...@@ -302,6 +325,7 @@ rtc: rtc@40024000 { ...@@ -302,6 +325,7 @@ rtc: rtc@40024000 {
compatible = "nxp,lpc3220-rtc"; compatible = "nxp,lpc3220-rtc";
reg = <0x40024000 0x1000>; reg = <0x40024000 0x1000>;
interrupts = <0x34 0>; interrupts = <0x34 0>;
clocks = <&clk LPC32XX_CLK_RTC>;
}; };
gpio: gpio@40028000 { gpio: gpio@40028000 {
...@@ -315,6 +339,8 @@ timer4: timer@4002C000 { ...@@ -315,6 +339,8 @@ timer4: timer@4002C000 {
compatible = "nxp,lpc3220-timer"; compatible = "nxp,lpc3220-timer";
reg = <0x4002C000 0x1000>; reg = <0x4002C000 0x1000>;
interrupts = <0x3 0>; interrupts = <0x3 0>;
clocks = <&clk LPC32XX_CLK_TIMER4>;
clock-names = "timerclk";
status = "disabled"; status = "disabled";
}; };
...@@ -322,17 +348,22 @@ timer5: timer@40030000 { ...@@ -322,17 +348,22 @@ timer5: timer@40030000 {
compatible = "nxp,lpc3220-timer"; compatible = "nxp,lpc3220-timer";
reg = <0x40030000 0x1000>; reg = <0x40030000 0x1000>;
interrupts = <0x4 0>; interrupts = <0x4 0>;
clocks = <&clk LPC32XX_CLK_TIMER5>;
clock-names = "timerclk";
status = "disabled"; status = "disabled";
}; };
watchdog: watchdog@4003C000 { watchdog: watchdog@4003C000 {
compatible = "nxp,pnx4008-wdt"; compatible = "nxp,pnx4008-wdt";
reg = <0x4003C000 0x1000>; reg = <0x4003C000 0x1000>;
clocks = <&clk LPC32XX_CLK_WDOG>;
}; };
timer0: timer@40044000 { timer0: timer@40044000 {
compatible = "nxp,lpc3220-timer"; compatible = "nxp,lpc3220-timer";
reg = <0x40044000 0x1000>; reg = <0x40044000 0x1000>;
clocks = <&clk LPC32XX_CLK_TIMER0>;
clock-names = "timerclk";
interrupts = <0x10 0>; interrupts = <0x10 0>;
}; };
...@@ -347,6 +378,7 @@ adc: adc@40048000 { ...@@ -347,6 +378,7 @@ adc: adc@40048000 {
compatible = "nxp,lpc3220-adc"; compatible = "nxp,lpc3220-adc";
reg = <0x40048000 0x1000>; reg = <0x40048000 0x1000>;
interrupts = <0x27 0>; interrupts = <0x27 0>;
clocks = <&clk LPC32XX_CLK_ADC>;
status = "disabled"; status = "disabled";
}; };
...@@ -354,6 +386,7 @@ tsc: tsc@40048000 { ...@@ -354,6 +386,7 @@ tsc: tsc@40048000 {
compatible = "nxp,lpc3220-tsc"; compatible = "nxp,lpc3220-tsc";
reg = <0x40048000 0x1000>; reg = <0x40048000 0x1000>;
interrupts = <0x27 0>; interrupts = <0x27 0>;
clocks = <&clk LPC32XX_CLK_ADC>;
status = "disabled"; status = "disabled";
}; };
...@@ -361,6 +394,8 @@ timer1: timer@4004C000 { ...@@ -361,6 +394,8 @@ timer1: timer@4004C000 {
compatible = "nxp,lpc3220-timer"; compatible = "nxp,lpc3220-timer";
reg = <0x4004C000 0x1000>; reg = <0x4004C000 0x1000>;
interrupts = <0x11 0>; interrupts = <0x11 0>;
clocks = <&clk LPC32XX_CLK_TIMER1>;
clock-names = "timerclk";
}; };
key: key@40050000 { key: key@40050000 {
...@@ -374,18 +409,22 @@ timer2: timer@40058000 { ...@@ -374,18 +409,22 @@ timer2: timer@40058000 {
compatible = "nxp,lpc3220-timer"; compatible = "nxp,lpc3220-timer";
reg = <0x40058000 0x1000>; reg = <0x40058000 0x1000>;
interrupts = <0x12 0>; interrupts = <0x12 0>;
clocks = <&clk LPC32XX_CLK_TIMER2>;
clock-names = "timerclk";
status = "disabled"; status = "disabled";
}; };
pwm1: pwm@4005C000 { pwm1: pwm@4005C000 {
compatible = "nxp,lpc3220-pwm"; compatible = "nxp,lpc3220-pwm";
reg = <0x4005C000 0x4>; reg = <0x4005C000 0x4>;
clocks = <&clk LPC32XX_CLK_PWM1>;
status = "disabled"; status = "disabled";
}; };
pwm2: pwm@4005C004 { pwm2: pwm@4005C004 {
compatible = "nxp,lpc3220-pwm"; compatible = "nxp,lpc3220-pwm";
reg = <0x4005C004 0x4>; reg = <0x4005C004 0x4>;
clocks = <&clk LPC32XX_CLK_PWM2>;
status = "disabled"; status = "disabled";
}; };
...@@ -393,6 +432,8 @@ timer3: timer@40060000 { ...@@ -393,6 +432,8 @@ timer3: timer@40060000 {
compatible = "nxp,lpc3220-timer"; compatible = "nxp,lpc3220-timer";
reg = <0x40060000 0x1000>; reg = <0x40060000 0x1000>;
interrupts = <0x13 0>; interrupts = <0x13 0>;
clocks = <&clk LPC32XX_CLK_TIMER3>;
clock-names = "timerclk";
status = "disabled"; status = "disabled";
}; };
}; };
......
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