Commit 949e8ab3 authored by Chris Wilson's avatar Chris Wilson

drm/i915: Use the size/type of address space to make decisions

Once the address space has been created (using 3 or 4 levels of page
tables), we should use that to program the appropriate type into the
contexts. This gives us the flexibility to handle different types of
address spaces at runtime.
Signed-off-by: default avatarChris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/20170209144036.23664-1-chris@chris-wilson.co.ukReviewed-by: default avatarMika Kuoppala <mika.kuoppala@intel.com>
parent 8d2b47dd
...@@ -236,16 +236,20 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out) ...@@ -236,16 +236,20 @@ static int assign_hw_id(struct drm_i915_private *dev_priv, unsigned *out)
return 0; return 0;
} }
static u32 default_desc_template(const struct drm_i915_private *dev_priv) static u32 default_desc_template(const struct drm_i915_private *i915,
const struct i915_hw_ppgtt *ppgtt)
{ {
u32 address_mode;
u32 desc; u32 desc;
desc = GEN8_CTX_VALID | desc = GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
GEN8_CTX_PRIVILEGE |
GEN8_CTX_ADDRESSING_MODE(dev_priv) <<
GEN8_CTX_ADDRESSING_MODE_SHIFT;
if (IS_GEN8(dev_priv)) address_mode = INTEL_LEGACY_32B_CONTEXT;
if (ppgtt && i915_vm_is_48bit(&ppgtt->base))
address_mode = INTEL_LEGACY_64B_CONTEXT;
desc |= address_mode << GEN8_CTX_ADDRESSING_MODE_SHIFT;
if (IS_GEN8(i915))
desc |= GEN8_CTX_L3LLC_COHERENT; desc |= GEN8_CTX_L3LLC_COHERENT;
/* TODO: WaDisableLiteRestore when we start using semaphore /* TODO: WaDisableLiteRestore when we start using semaphore
...@@ -329,7 +333,8 @@ __create_hw_context(struct drm_i915_private *dev_priv, ...@@ -329,7 +333,8 @@ __create_hw_context(struct drm_i915_private *dev_priv,
i915_gem_context_set_bannable(ctx); i915_gem_context_set_bannable(ctx);
ctx->ring_size = 4 * PAGE_SIZE; ctx->ring_size = 4 * PAGE_SIZE;
ctx->desc_template = default_desc_template(dev_priv); ctx->desc_template =
default_desc_template(dev_priv, dev_priv->mm.aliasing_ppgtt);
ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier); ATOMIC_INIT_NOTIFIER_HEAD(&ctx->status_notifier);
/* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not /* GuC requires the ring to be placed above GUC_WOPCM_TOP. If GuC is not
...@@ -387,6 +392,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv, ...@@ -387,6 +392,7 @@ i915_gem_create_context(struct drm_i915_private *dev_priv,
} }
ctx->ppgtt = ppgtt; ctx->ppgtt = ppgtt;
ctx->desc_template = default_desc_template(dev_priv, ppgtt);
} }
trace_i915_context_create(ctx); trace_i915_context_create(ctx);
......
...@@ -525,6 +525,12 @@ i915_vm_to_ggtt(struct i915_address_space *vm) ...@@ -525,6 +525,12 @@ i915_vm_to_ggtt(struct i915_address_space *vm)
return container_of(vm, struct i915_ggtt, base); return container_of(vm, struct i915_ggtt, base);
} }
static inline bool
i915_vm_is_48bit(const struct i915_address_space *vm)
{
return (vm->total - 1) >> 32;
}
int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv); int i915_ggtt_probe_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_init_hw(struct drm_i915_private *dev_priv); int i915_ggtt_init_hw(struct drm_i915_private *dev_priv);
int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv); int i915_ggtt_enable_hw(struct drm_i915_private *dev_priv);
......
...@@ -3373,9 +3373,6 @@ enum { ...@@ -3373,9 +3373,6 @@ enum {
#define GEN8_CTX_L3LLC_COHERENT (1<<5) #define GEN8_CTX_L3LLC_COHERENT (1<<5)
#define GEN8_CTX_PRIVILEGE (1<<8) #define GEN8_CTX_PRIVILEGE (1<<8)
#define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3
#define GEN8_CTX_ADDRESSING_MODE(dev_priv) (USES_FULL_48BIT_PPGTT(dev_priv) ?\
INTEL_LEGACY_64B_CONTEXT : \
INTEL_LEGACY_32B_CONTEXT)
#define GEN8_CTX_ID_SHIFT 32 #define GEN8_CTX_ID_SHIFT 32
#define GEN8_CTX_ID_WIDTH 21 #define GEN8_CTX_ID_WIDTH 21
......
...@@ -332,7 +332,7 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq) ...@@ -332,7 +332,7 @@ static u64 execlists_update_context(struct drm_i915_gem_request *rq)
* PML4 is allocated during ppgtt init, so this is not needed * PML4 is allocated during ppgtt init, so this is not needed
* in 48-bit mode. * in 48-bit mode.
*/ */
if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) if (ppgtt && !i915_vm_is_48bit(&ppgtt->base))
execlists_update_context_pdps(ppgtt, reg_state); execlists_update_context_pdps(ppgtt, reg_state);
return ce->lrc_desc; return ce->lrc_desc;
...@@ -1447,7 +1447,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req, ...@@ -1447,7 +1447,7 @@ static int gen8_emit_bb_start(struct drm_i915_gem_request *req,
* not needed in 48-bit.*/ * not needed in 48-bit.*/
if (req->ctx->ppgtt && if (req->ctx->ppgtt &&
(intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) {
if (!USES_FULL_48BIT_PPGTT(req->i915) && if (!i915_vm_is_48bit(&req->ctx->ppgtt->base) &&
!intel_vgpu_active(req->i915)) { !intel_vgpu_active(req->i915)) {
ret = intel_logical_ring_emit_pdps(req); ret = intel_logical_ring_emit_pdps(req);
if (ret) if (ret)
...@@ -2045,7 +2045,7 @@ static void execlists_init_reg_state(u32 *reg_state, ...@@ -2045,7 +2045,7 @@ static void execlists_init_reg_state(u32 *reg_state,
ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0),
0); 0);
if (ppgtt && USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) {
/* 64b PPGTT (48bit canonical) /* 64b PPGTT (48bit canonical)
* PDP0_DESCRIPTOR contains the base address to PML4 and * PDP0_DESCRIPTOR contains the base address to PML4 and
* other PDP Descriptors are ignored. * other PDP Descriptors are ignored.
......
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