Commit 971afec3 authored by Weinan Li's avatar Weinan Li Committed by Zhenyu Wang

drm/i915/gvt: ignore unexpected pvinfo write

There is pvinfo writing come from vgpu might be unexpected, like
writing to one unknown address, GVT-g should do as reserved register
to discard any invalid write. Now GVT-g lets it write to the vreg
without prompt error message, should ignore the unexpected pvinfo
write access and leave the vreg as the default value.

For possible guest query GVT-g host feature, this returned proper
value instead of wrong guest setting.

v2: ignore unexpected pvinfo write instead of return predefined value

Fixes: e39c5add ("drm/i915/gvt: vGPU MMIO virtualization")
Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Reviewed-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: default avatarWeinan Li <weinan.z.li@intel.com>
Signed-off-by: default avatarZhenyu Wang <zhenyuw@linux.intel.com>
parent 15e7f52a
...@@ -1254,18 +1254,15 @@ static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready) ...@@ -1254,18 +1254,15 @@ static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes) void *p_data, unsigned int bytes)
{ {
u32 data; u32 data = *(u32 *)p_data;
int ret; bool invalid_write = false;
write_vreg(vgpu, offset, p_data, bytes);
data = vgpu_vreg(vgpu, offset);
switch (offset) { switch (offset) {
case _vgtif_reg(display_ready): case _vgtif_reg(display_ready):
send_display_ready_uevent(vgpu, data ? 1 : 0); send_display_ready_uevent(vgpu, data ? 1 : 0);
break; break;
case _vgtif_reg(g2v_notify): case _vgtif_reg(g2v_notify):
ret = handle_g2v_notification(vgpu, data); handle_g2v_notification(vgpu, data);
break; break;
/* add xhot and yhot to handled list to avoid error log */ /* add xhot and yhot to handled list to avoid error log */
case _vgtif_reg(cursor_x_hot): case _vgtif_reg(cursor_x_hot):
...@@ -1282,13 +1279,19 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset, ...@@ -1282,13 +1279,19 @@ static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
case _vgtif_reg(execlist_context_descriptor_hi): case _vgtif_reg(execlist_context_descriptor_hi):
break; break;
case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]): case _vgtif_reg(rsv5[0])..._vgtif_reg(rsv5[3]):
invalid_write = true;
enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE); enter_failsafe_mode(vgpu, GVT_FAILSAFE_INSUFFICIENT_RESOURCE);
break; break;
default: default:
invalid_write = true;
gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n", gvt_vgpu_err("invalid pvinfo write offset %x bytes %x data %x\n",
offset, bytes, data); offset, bytes, data);
break; break;
} }
if (!invalid_write)
write_vreg(vgpu, offset, p_data, bytes);
return 0; return 0;
} }
......
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