staging: comedi: me_daq: remove broken workaround for PLX bug
The PLX PCI 9050 interface chip has a bug where its local configuration registers accessible through PCI BAR 0 and/or PCI BAR 1 (depending on settings loaded from a serial EEPROM or local bus processor) are unreadable (always read 0 instead of the true register values) if the base address starts on an odd multiple of 0x80 (i.e. has bit 7 set to 1). The "me_daq" driver attempts to work around this by writing to the PCI config space to swap the addresses assigned to PCI BAR 0 and PCI BAR 5 (which has been initially configured by serial EEPROM load as a spare region of the same length as the PCI BAR 0 region). (If the PCI BAR 5 region is absent, it attempts to reduce the PCI BAR 0 address by 0x80, which is likely to cause havoc for some other device, but that case shouldn't be reachable in practice.) The workaround in the driver is ineffective because it has already ioremapped the memory from `pci_resource_start(pcidev, 0)` *before* it does the workaround, so after swapping PCI BAR 0 and PCI BAR 5, this memory will end up accessing whatever onboard registers PCI BAR 5 was linked to instead of the local configuration registers. It also leaves the addresses in the physical PCI BAR registers set differently to the resource start addresses recorded in the `struct pci_dev`. The workaround could be fixed by ioremapping `pci_resource_start(pcidev, 5)` if the PCI BAR addresses were physically swapped (and the fallback workaround of subtracting 0x80 from the base address should really be removed altogether). However, it's not really worth it. This sort of thing should be worked around in "drivers/pci/quirks.c" by ensuring that PCI BAR 0 and/or PCI BAR 1 do not end up on an odd multiple of 0x80 bytes. Signed-off-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Showing
Please register or sign in to comment