Commit 9770a16f authored by Yuan-Hsin Chen's avatar Yuan-Hsin Chen Committed by Felipe Balbi

usb: gadget: fusb300_udc: add FUSB300_EPSET0_STL_CLR for clearing EP0 stall

The final version of fusb300 controller adds EPSET0_STL_CLR
for clearing EP0 stall and also removes EPSET0_EPn_TX0BYTE.

fusb300_udc driver is tested on FARADAY platform a369 with
FUSB300 FPGA v1.8
Signed-off-by: default avatarYuan-Hsin Chen <yhchen@faraday-tech.com>
Signed-off-by: default avatarFelipe Balbi <balbi@ti.com>
parent 19fda7cd
...@@ -394,7 +394,7 @@ static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep) ...@@ -394,7 +394,7 @@ static void fusb300_clear_epnstall(struct fusb300 *fusb300, u8 ep)
if (reg & FUSB300_EPSET0_STL) { if (reg & FUSB300_EPSET0_STL) {
printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep); printk(KERN_DEBUG "EP%d stall... Clear!!\n", ep);
reg &= ~FUSB300_EPSET0_STL; reg |= FUSB300_EPSET0_STL_CLR;
iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep)); iowrite32(reg, fusb300->reg + FUSB300_OFFSET_EPSET0(ep));
} }
} }
......
...@@ -111,8 +111,8 @@ ...@@ -111,8 +111,8 @@
/* /*
* * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 ) * * EPn Setting 0 (EPn_SET0, offset = 020H+(n-1)*30H, n=1~15 )
* */ * */
#define FUSB300_EPSET0_STL_CLR (1 << 3)
#define FUSB300_EPSET0_CLRSEQNUM (1 << 2) #define FUSB300_EPSET0_CLRSEQNUM (1 << 2)
#define FUSB300_EPSET0_EPn_TX0BYTE (1 << 1)
#define FUSB300_EPSET0_STL (1 << 0) #define FUSB300_EPSET0_STL (1 << 0)
/* /*
......
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