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Commit 9c3f2b54 authored by Alex Deucher's avatar Alex Deucher
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drm/amdgpu: rename amdgpu_program_register_sequence 

add device for consistency with other functions in this file.
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 131b4b36
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Showing with 311 additions and 311 deletions
drivers/gpu/drm/amd/amdgpu/amdgpu.h
View file @ 9c3f2b54
...@@ -1913,7 +1913,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev); ...@@ -1913,7 +1913,7 @@ int amdgpu_device_resize_fb_bar(struct amdgpu_device *adev);
void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size); void amdgpu_ttm_set_active_vram_size(struct amdgpu_device *adev, u64 size);
int amdgpu_ttm_init(struct amdgpu_device *adev); int amdgpu_ttm_init(struct amdgpu_device *adev);
void amdgpu_ttm_fini(struct amdgpu_device *adev); void amdgpu_ttm_fini(struct amdgpu_device *adev);
void amdgpu_program_register_sequence(struct amdgpu_device *adev, void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
const u32 *registers, const u32 *registers,
const u32 array_size); const u32 array_size);
......
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
View file @ 9c3f2b54
...@@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) ...@@ -342,7 +342,7 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
} }
/** /**
* amdgpu_program_register_sequence - program an array of registers. * amdgpu_device_program_register_sequence - program an array of registers.
* *
* @adev: amdgpu_device pointer * @adev: amdgpu_device pointer
* @registers: pointer to the register array * @registers: pointer to the register array
...@@ -351,9 +351,9 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev) ...@@ -351,9 +351,9 @@ static void amdgpu_device_vram_scratch_fini(struct amdgpu_device *adev)
* Programs an array or registers with and and or masks. * Programs an array or registers with and and or masks.
* This is a helper for setting golden registers. * This is a helper for setting golden registers.
*/ */
void amdgpu_program_register_sequence(struct amdgpu_device *adev, void amdgpu_device_program_register_sequence(struct amdgpu_device *adev,
const u32 *registers, const u32 *registers,
const u32 array_size) const u32 array_size)
{ {
u32 tmp, reg, and_mask, or_mask; u32 tmp, reg, and_mask, or_mask;
int i; int i;
......
drivers/gpu/drm/amd/amdgpu/cik.c
View file @ 9c3f2b54
...@@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct amdgpu_device *adev) ...@@ -755,74 +755,74 @@ static void cik_init_golden_registers(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_BONAIRE: case CHIP_BONAIRE:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
bonaire_mgcg_cgcg_init, bonaire_mgcg_cgcg_init,
ARRAY_SIZE(bonaire_mgcg_cgcg_init)); ARRAY_SIZE(bonaire_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
bonaire_golden_registers, bonaire_golden_registers,
ARRAY_SIZE(bonaire_golden_registers)); ARRAY_SIZE(bonaire_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
bonaire_golden_common_registers, bonaire_golden_common_registers,
ARRAY_SIZE(bonaire_golden_common_registers)); ARRAY_SIZE(bonaire_golden_common_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
bonaire_golden_spm_registers, bonaire_golden_spm_registers,
ARRAY_SIZE(bonaire_golden_spm_registers)); ARRAY_SIZE(bonaire_golden_spm_registers));
break; break;
case CHIP_KABINI: case CHIP_KABINI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_mgcg_cgcg_init, kalindi_mgcg_cgcg_init,
ARRAY_SIZE(kalindi_mgcg_cgcg_init)); ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_golden_registers, kalindi_golden_registers,
ARRAY_SIZE(kalindi_golden_registers)); ARRAY_SIZE(kalindi_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_golden_common_registers, kalindi_golden_common_registers,
ARRAY_SIZE(kalindi_golden_common_registers)); ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_golden_spm_registers, kalindi_golden_spm_registers,
ARRAY_SIZE(kalindi_golden_spm_registers)); ARRAY_SIZE(kalindi_golden_spm_registers));
break; break;
case CHIP_MULLINS: case CHIP_MULLINS:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_mgcg_cgcg_init, kalindi_mgcg_cgcg_init,
ARRAY_SIZE(kalindi_mgcg_cgcg_init)); ARRAY_SIZE(kalindi_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
godavari_golden_registers, godavari_golden_registers,
ARRAY_SIZE(godavari_golden_registers)); ARRAY_SIZE(godavari_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_golden_common_registers, kalindi_golden_common_registers,
ARRAY_SIZE(kalindi_golden_common_registers)); ARRAY_SIZE(kalindi_golden_common_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
kalindi_golden_spm_registers, kalindi_golden_spm_registers,
ARRAY_SIZE(kalindi_golden_spm_registers)); ARRAY_SIZE(kalindi_golden_spm_registers));
break; break;
case CHIP_KAVERI: case CHIP_KAVERI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
spectre_mgcg_cgcg_init, spectre_mgcg_cgcg_init,
ARRAY_SIZE(spectre_mgcg_cgcg_init)); ARRAY_SIZE(spectre_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
spectre_golden_registers, spectre_golden_registers,
ARRAY_SIZE(spectre_golden_registers)); ARRAY_SIZE(spectre_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
spectre_golden_common_registers, spectre_golden_common_registers,
ARRAY_SIZE(spectre_golden_common_registers)); ARRAY_SIZE(spectre_golden_common_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
spectre_golden_spm_registers, spectre_golden_spm_registers,
ARRAY_SIZE(spectre_golden_spm_registers)); ARRAY_SIZE(spectre_golden_spm_registers));
break; break;
case CHIP_HAWAII: case CHIP_HAWAII:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hawaii_mgcg_cgcg_init, hawaii_mgcg_cgcg_init,
ARRAY_SIZE(hawaii_mgcg_cgcg_init)); ARRAY_SIZE(hawaii_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hawaii_golden_registers, hawaii_golden_registers,
ARRAY_SIZE(hawaii_golden_registers)); ARRAY_SIZE(hawaii_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hawaii_golden_common_registers, hawaii_golden_common_registers,
ARRAY_SIZE(hawaii_golden_common_registers)); ARRAY_SIZE(hawaii_golden_common_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hawaii_golden_spm_registers, hawaii_golden_spm_registers,
ARRAY_SIZE(hawaii_golden_spm_registers)); ARRAY_SIZE(hawaii_golden_spm_registers));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
View file @ 9c3f2b54
...@@ -145,20 +145,20 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -145,20 +145,20 @@ static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
fiji_mgcg_cgcg_init, fiji_mgcg_cgcg_init,
ARRAY_SIZE(fiji_mgcg_cgcg_init)); ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_fiji_a10, golden_settings_fiji_a10,
ARRAY_SIZE(golden_settings_fiji_a10)); ARRAY_SIZE(golden_settings_fiji_a10));
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
ARRAY_SIZE(tonga_mgcg_cgcg_init)); ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_tonga_a11, golden_settings_tonga_a11,
ARRAY_SIZE(golden_settings_tonga_a11)); ARRAY_SIZE(golden_settings_tonga_a11));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
View file @ 9c3f2b54
...@@ -154,28 +154,28 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -154,28 +154,28 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_CARRIZO: case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_mgcg_cgcg_init, cz_mgcg_cgcg_init,
ARRAY_SIZE(cz_mgcg_cgcg_init)); ARRAY_SIZE(cz_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_golden_settings_a11, cz_golden_settings_a11,
ARRAY_SIZE(cz_golden_settings_a11)); ARRAY_SIZE(cz_golden_settings_a11));
break; break;
case CHIP_STONEY: case CHIP_STONEY:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_golden_settings_a11, stoney_golden_settings_a11,
ARRAY_SIZE(stoney_golden_settings_a11)); ARRAY_SIZE(stoney_golden_settings_a11));
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS12: case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
polaris11_golden_settings_a11, polaris11_golden_settings_a11,
ARRAY_SIZE(polaris11_golden_settings_a11)); ARRAY_SIZE(polaris11_golden_settings_a11));
break; break;
case CHIP_POLARIS10: case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
polaris10_golden_settings_a11, polaris10_golden_settings_a11,
ARRAY_SIZE(polaris10_golden_settings_a11)); ARRAY_SIZE(polaris10_golden_settings_a11));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
View file @ 9c3f2b54
...@@ -679,55 +679,55 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -679,55 +679,55 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ: case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
iceland_mgcg_cgcg_init, iceland_mgcg_cgcg_init,
ARRAY_SIZE(iceland_mgcg_cgcg_init)); ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_iceland_a11, golden_settings_iceland_a11,
ARRAY_SIZE(golden_settings_iceland_a11)); ARRAY_SIZE(golden_settings_iceland_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
iceland_golden_common_all, iceland_golden_common_all,
ARRAY_SIZE(iceland_golden_common_all)); ARRAY_SIZE(iceland_golden_common_all));
break; break;
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
fiji_mgcg_cgcg_init, fiji_mgcg_cgcg_init,
ARRAY_SIZE(fiji_mgcg_cgcg_init)); ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_fiji_a10, golden_settings_fiji_a10,
ARRAY_SIZE(golden_settings_fiji_a10)); ARRAY_SIZE(golden_settings_fiji_a10));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
fiji_golden_common_all, fiji_golden_common_all,
ARRAY_SIZE(fiji_golden_common_all)); ARRAY_SIZE(fiji_golden_common_all));
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
ARRAY_SIZE(tonga_mgcg_cgcg_init)); ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_tonga_a11, golden_settings_tonga_a11,
ARRAY_SIZE(golden_settings_tonga_a11)); ARRAY_SIZE(golden_settings_tonga_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tonga_golden_common_all, tonga_golden_common_all,
ARRAY_SIZE(tonga_golden_common_all)); ARRAY_SIZE(tonga_golden_common_all));
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS12: case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_polaris11_a11, golden_settings_polaris11_a11,
ARRAY_SIZE(golden_settings_polaris11_a11)); ARRAY_SIZE(golden_settings_polaris11_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
polaris11_golden_common_all, polaris11_golden_common_all,
ARRAY_SIZE(polaris11_golden_common_all)); ARRAY_SIZE(polaris11_golden_common_all));
break; break;
case CHIP_POLARIS10: case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_polaris10_a11, golden_settings_polaris10_a11,
ARRAY_SIZE(golden_settings_polaris10_a11)); ARRAY_SIZE(golden_settings_polaris10_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
polaris10_golden_common_all, polaris10_golden_common_all,
ARRAY_SIZE(polaris10_golden_common_all)); ARRAY_SIZE(polaris10_golden_common_all));
WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C); WREG32_SMC(ixCG_ACLK_CNTL, 0x0000001C);
if (adev->pdev->revision == 0xc7 && if (adev->pdev->revision == 0xc7 &&
((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) || ((adev->pdev->subsystem_device == 0xb37 && adev->pdev->subsystem_vendor == 0x1002) ||
...@@ -738,26 +738,26 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -738,26 +738,26 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev)
} }
break; break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_mgcg_cgcg_init, cz_mgcg_cgcg_init,
ARRAY_SIZE(cz_mgcg_cgcg_init)); ARRAY_SIZE(cz_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_golden_settings_a11, cz_golden_settings_a11,
ARRAY_SIZE(cz_golden_settings_a11)); ARRAY_SIZE(cz_golden_settings_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_golden_common_all, cz_golden_common_all,
ARRAY_SIZE(cz_golden_common_all)); ARRAY_SIZE(cz_golden_common_all));
break; break;
case CHIP_STONEY: case CHIP_STONEY:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_mgcg_cgcg_init, stoney_mgcg_cgcg_init,
ARRAY_SIZE(stoney_mgcg_cgcg_init)); ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_golden_settings_a11, stoney_golden_settings_a11,
ARRAY_SIZE(stoney_golden_settings_a11)); ARRAY_SIZE(stoney_golden_settings_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_golden_common_all, stoney_golden_common_all,
ARRAY_SIZE(stoney_golden_common_all)); ARRAY_SIZE(stoney_golden_common_all));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
View file @ 9c3f2b54
...@@ -67,12 +67,12 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -67,12 +67,12 @@ static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ: case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
iceland_mgcg_cgcg_init, iceland_mgcg_cgcg_init,
ARRAY_SIZE(iceland_mgcg_cgcg_init)); ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_iceland_a11, golden_settings_iceland_a11,
ARRAY_SIZE(golden_settings_iceland_a11)); ARRAY_SIZE(golden_settings_iceland_a11));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
View file @ 9c3f2b54
...@@ -120,44 +120,44 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -120,44 +120,44 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
fiji_mgcg_cgcg_init, fiji_mgcg_cgcg_init,
ARRAY_SIZE(fiji_mgcg_cgcg_init)); ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_fiji_a10, golden_settings_fiji_a10,
ARRAY_SIZE(golden_settings_fiji_a10)); ARRAY_SIZE(golden_settings_fiji_a10));
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
ARRAY_SIZE(tonga_mgcg_cgcg_init)); ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_tonga_a11, golden_settings_tonga_a11,
ARRAY_SIZE(golden_settings_tonga_a11)); ARRAY_SIZE(golden_settings_tonga_a11));
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS12: case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_polaris11_a11, golden_settings_polaris11_a11,
ARRAY_SIZE(golden_settings_polaris11_a11)); ARRAY_SIZE(golden_settings_polaris11_a11));
break; break;
case CHIP_POLARIS10: case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_polaris10_a11, golden_settings_polaris10_a11,
ARRAY_SIZE(golden_settings_polaris10_a11)); ARRAY_SIZE(golden_settings_polaris10_a11));
break; break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_mgcg_cgcg_init, cz_mgcg_cgcg_init,
ARRAY_SIZE(cz_mgcg_cgcg_init)); ARRAY_SIZE(cz_mgcg_cgcg_init));
break; break;
case CHIP_STONEY: case CHIP_STONEY:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_mgcg_cgcg_init, stoney_mgcg_cgcg_init,
ARRAY_SIZE(stoney_mgcg_cgcg_init)); ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_stoney_common, golden_settings_stoney_common,
ARRAY_SIZE(golden_settings_stoney_common)); ARRAY_SIZE(golden_settings_stoney_common));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
View file @ 9c3f2b54
...@@ -918,9 +918,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) ...@@ -918,9 +918,9 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
bool value; bool value;
u32 tmp; u32 tmp;
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_vega10_hdp, golden_settings_vega10_hdp,
ARRAY_SIZE(golden_settings_vega10_hdp)); ARRAY_SIZE(golden_settings_vega10_hdp));
if (adev->gart.robj == NULL) { if (adev->gart.robj == NULL) {
dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
......
drivers/gpu/drm/amd/amdgpu/mxgpu_vi.c
View file @ 9c3f2b54
...@@ -279,32 +279,32 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) ...@@ -279,32 +279,32 @@ void xgpu_vi_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
xgpu_fiji_mgcg_cgcg_init, xgpu_fiji_mgcg_cgcg_init,
ARRAY_SIZE( ARRAY_SIZE(
xgpu_fiji_mgcg_cgcg_init)); xgpu_fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
xgpu_fiji_golden_settings_a10, xgpu_fiji_golden_settings_a10,
ARRAY_SIZE( ARRAY_SIZE(
xgpu_fiji_golden_settings_a10)); xgpu_fiji_golden_settings_a10));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
xgpu_fiji_golden_common_all, xgpu_fiji_golden_common_all,
ARRAY_SIZE( ARRAY_SIZE(
xgpu_fiji_golden_common_all)); xgpu_fiji_golden_common_all));
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
xgpu_tonga_mgcg_cgcg_init, xgpu_tonga_mgcg_cgcg_init,
ARRAY_SIZE( ARRAY_SIZE(
xgpu_tonga_mgcg_cgcg_init)); xgpu_tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
xgpu_tonga_golden_settings_a11, xgpu_tonga_golden_settings_a11,
ARRAY_SIZE( ARRAY_SIZE(
xgpu_tonga_golden_settings_a11)); xgpu_tonga_golden_settings_a11));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
xgpu_tonga_golden_common_all, xgpu_tonga_golden_common_all,
ARRAY_SIZE( ARRAY_SIZE(
xgpu_tonga_golden_common_all)); xgpu_tonga_golden_common_all));
break; break;
default: default:
BUG_ON("Doesn't support chip type.\n"); BUG_ON("Doesn't support chip type.\n");
......
drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
View file @ 9c3f2b54
...@@ -93,12 +93,12 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) ...@@ -93,12 +93,12 @@ static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ: case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
iceland_mgcg_cgcg_init, iceland_mgcg_cgcg_init,
ARRAY_SIZE(iceland_mgcg_cgcg_init)); ARRAY_SIZE(iceland_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_iceland_a11, golden_settings_iceland_a11,
ARRAY_SIZE(golden_settings_iceland_a11)); ARRAY_SIZE(golden_settings_iceland_a11));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
View file @ 9c3f2b54
...@@ -192,47 +192,47 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) ...@@ -192,47 +192,47 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
fiji_mgcg_cgcg_init, fiji_mgcg_cgcg_init,
ARRAY_SIZE(fiji_mgcg_cgcg_init)); ARRAY_SIZE(fiji_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_fiji_a10, golden_settings_fiji_a10,
ARRAY_SIZE(golden_settings_fiji_a10)); ARRAY_SIZE(golden_settings_fiji_a10));
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
ARRAY_SIZE(tonga_mgcg_cgcg_init)); ARRAY_SIZE(tonga_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_tonga_a11, golden_settings_tonga_a11,
ARRAY_SIZE(golden_settings_tonga_a11)); ARRAY_SIZE(golden_settings_tonga_a11));
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS12: case CHIP_POLARIS12:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_polaris11_a11, golden_settings_polaris11_a11,
ARRAY_SIZE(golden_settings_polaris11_a11)); ARRAY_SIZE(golden_settings_polaris11_a11));
break; break;
case CHIP_POLARIS10: case CHIP_POLARIS10:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
golden_settings_polaris10_a11, golden_settings_polaris10_a11,
ARRAY_SIZE(golden_settings_polaris10_a11)); ARRAY_SIZE(golden_settings_polaris10_a11));
break; break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_mgcg_cgcg_init, cz_mgcg_cgcg_init,
ARRAY_SIZE(cz_mgcg_cgcg_init)); ARRAY_SIZE(cz_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_golden_settings_a11, cz_golden_settings_a11,
ARRAY_SIZE(cz_golden_settings_a11)); ARRAY_SIZE(cz_golden_settings_a11));
break; break;
case CHIP_STONEY: case CHIP_STONEY:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_mgcg_cgcg_init, stoney_mgcg_cgcg_init,
ARRAY_SIZE(stoney_mgcg_cgcg_init)); ARRAY_SIZE(stoney_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_golden_settings_a11, stoney_golden_settings_a11,
ARRAY_SIZE(stoney_golden_settings_a11)); ARRAY_SIZE(stoney_golden_settings_a11));
break; break;
default: default:
break; break;
......
drivers/gpu/drm/amd/amdgpu/si.c
View file @ 9c3f2b54
...@@ -1390,65 +1390,65 @@ static void si_init_golden_registers(struct amdgpu_device *adev) ...@@ -1390,65 +1390,65 @@ static void si_init_golden_registers(struct amdgpu_device *adev)
{ {
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TAHITI: case CHIP_TAHITI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tahiti_golden_registers, tahiti_golden_registers,
ARRAY_SIZE(tahiti_golden_registers)); ARRAY_SIZE(tahiti_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tahiti_golden_rlc_registers, tahiti_golden_rlc_registers,
ARRAY_SIZE(tahiti_golden_rlc_registers)); ARRAY_SIZE(tahiti_golden_rlc_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tahiti_mgcg_cgcg_init, tahiti_mgcg_cgcg_init,
ARRAY_SIZE(tahiti_mgcg_cgcg_init)); ARRAY_SIZE(tahiti_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tahiti_golden_registers2, tahiti_golden_registers2,
ARRAY_SIZE(tahiti_golden_registers2)); ARRAY_SIZE(tahiti_golden_registers2));
break; break;
case CHIP_PITCAIRN: case CHIP_PITCAIRN:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
pitcairn_golden_registers, pitcairn_golden_registers,
ARRAY_SIZE(pitcairn_golden_registers)); ARRAY_SIZE(pitcairn_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
pitcairn_golden_rlc_registers, pitcairn_golden_rlc_registers,
ARRAY_SIZE(pitcairn_golden_rlc_registers)); ARRAY_SIZE(pitcairn_golden_rlc_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
pitcairn_mgcg_cgcg_init, pitcairn_mgcg_cgcg_init,
ARRAY_SIZE(pitcairn_mgcg_cgcg_init)); ARRAY_SIZE(pitcairn_mgcg_cgcg_init));
break; break;
case CHIP_VERDE: case CHIP_VERDE:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
verde_golden_registers, verde_golden_registers,
ARRAY_SIZE(verde_golden_registers)); ARRAY_SIZE(verde_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
verde_golden_rlc_registers, verde_golden_rlc_registers,
ARRAY_SIZE(verde_golden_rlc_registers)); ARRAY_SIZE(verde_golden_rlc_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
verde_mgcg_cgcg_init, verde_mgcg_cgcg_init,
ARRAY_SIZE(verde_mgcg_cgcg_init)); ARRAY_SIZE(verde_mgcg_cgcg_init));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
verde_pg_init, verde_pg_init,
ARRAY_SIZE(verde_pg_init)); ARRAY_SIZE(verde_pg_init));
break; break;
case CHIP_OLAND: case CHIP_OLAND:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
oland_golden_registers, oland_golden_registers,
ARRAY_SIZE(oland_golden_registers)); ARRAY_SIZE(oland_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
oland_golden_rlc_registers, oland_golden_rlc_registers,
ARRAY_SIZE(oland_golden_rlc_registers)); ARRAY_SIZE(oland_golden_rlc_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
oland_mgcg_cgcg_init, oland_mgcg_cgcg_init,
ARRAY_SIZE(oland_mgcg_cgcg_init)); ARRAY_SIZE(oland_mgcg_cgcg_init));
break; break;
case CHIP_HAINAN: case CHIP_HAINAN:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hainan_golden_registers, hainan_golden_registers,
ARRAY_SIZE(hainan_golden_registers)); ARRAY_SIZE(hainan_golden_registers));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hainan_golden_registers2, hainan_golden_registers2,
ARRAY_SIZE(hainan_golden_registers2)); ARRAY_SIZE(hainan_golden_registers2));
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
hainan_mgcg_cgcg_init, hainan_mgcg_cgcg_init,
ARRAY_SIZE(hainan_mgcg_cgcg_init)); ARRAY_SIZE(hainan_mgcg_cgcg_init));
break; break;
......
drivers/gpu/drm/amd/amdgpu/vi.c
View file @ 9c3f2b54
...@@ -282,29 +282,29 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) ...@@ -282,29 +282,29 @@ static void vi_init_golden_registers(struct amdgpu_device *adev)
switch (adev->asic_type) { switch (adev->asic_type) {
case CHIP_TOPAZ: case CHIP_TOPAZ:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
iceland_mgcg_cgcg_init, iceland_mgcg_cgcg_init,
ARRAY_SIZE(iceland_mgcg_cgcg_init)); ARRAY_SIZE(iceland_mgcg_cgcg_init));
break; break;
case CHIP_FIJI: case CHIP_FIJI:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
fiji_mgcg_cgcg_init, fiji_mgcg_cgcg_init,
ARRAY_SIZE(fiji_mgcg_cgcg_init)); ARRAY_SIZE(fiji_mgcg_cgcg_init));
break; break;
case CHIP_TONGA: case CHIP_TONGA:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
tonga_mgcg_cgcg_init, tonga_mgcg_cgcg_init,
ARRAY_SIZE(tonga_mgcg_cgcg_init)); ARRAY_SIZE(tonga_mgcg_cgcg_init));
break; break;
case CHIP_CARRIZO: case CHIP_CARRIZO:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
cz_mgcg_cgcg_init, cz_mgcg_cgcg_init,
ARRAY_SIZE(cz_mgcg_cgcg_init)); ARRAY_SIZE(cz_mgcg_cgcg_init));
break; break;
case CHIP_STONEY: case CHIP_STONEY:
amdgpu_program_register_sequence(adev, amdgpu_device_program_register_sequence(adev,
stoney_mgcg_cgcg_init, stoney_mgcg_cgcg_init,
ARRAY_SIZE(stoney_mgcg_cgcg_init)); ARRAY_SIZE(stoney_mgcg_cgcg_init));
break; break;
case CHIP_POLARIS11: case CHIP_POLARIS11:
case CHIP_POLARIS10: case CHIP_POLARIS10:
......
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