Commit 9cf74ebb authored by Matt Carlson's avatar Matt Carlson Committed by David S. Miller

tg3: Limit CLKREQ fix to A[01] of 57780 asic rev

This patch restricts the CLKREQ bugfix to the A0 and A1 revisions
of 57780 ASIC rev chips.
Signed-off-by: default avatarMatt Carlson <mcarlson@broadcom.com>
Signed-off-by: default avatarMichael Chan <mchan@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 8d519ab2
...@@ -11992,7 +11992,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp) ...@@ -11992,7 +11992,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2; tp->tg3_flags2 &= ~TG3_FLG2_HW_TSO_2;
if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 || if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 || GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780) tp->pci_chip_rev_id == CHIPREV_ID_57780_A0 ||
tp->pci_chip_rev_id == CHIPREV_ID_57780_A1)
tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG; tp->tg3_flags3 |= TG3_FLG3_CLKREQ_BUG;
} }
} else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) { } else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785) {
......
...@@ -95,6 +95,8 @@ ...@@ -95,6 +95,8 @@
#define CHIPREV_ID_5752_A1 0x6001 #define CHIPREV_ID_5752_A1 0x6001
#define CHIPREV_ID_5714_A2 0x9002 #define CHIPREV_ID_5714_A2 0x9002
#define CHIPREV_ID_5906_A1 0xc001 #define CHIPREV_ID_5906_A1 0xc001
#define CHIPREV_ID_57780_A0 0x57780000
#define CHIPREV_ID_57780_A1 0x57780001
#define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12) #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
#define ASIC_REV_5700 0x07 #define ASIC_REV_5700 0x07
#define ASIC_REV_5701 0x00 #define ASIC_REV_5701 0x00
......
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