Commit 9e1f670c authored by Russell King's avatar Russell King

[ARM] Fix entry-armv.S

Prevent the assembler putting constant pools in the middle of code.
Clean up shark ISA PIC handling.
parent e664b42a
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...@@ -189,11 +189,10 @@ irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43 ...@@ -189,11 +189,10 @@ irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
mov r4, #0xe0000000 mov r4, #0xe0000000
orr r4, r4, #0x20
mov \irqstat, #0x0C mov \irqstat, #0x0C
strb \irqstat, [r4] @outb(0x0C, 0x20) /* Poll command */ strb \irqstat, [r4, #0x20] @outb(0x0C, 0x20) /* Poll command */
ldrb \irqnr, [r4] @irq = inb(0x20) & 7 ldrb \irqnr, [r4, #0x10] @irq = inb(0x20) & 7
and \irqstat, \irqnr, #0x80 and \irqstat, \irqnr, #0x80
teq \irqstat, #0 teq \irqstat, #0
beq 43f beq 43f
...@@ -201,8 +200,8 @@ irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43 ...@@ -201,8 +200,8 @@ irq_prio_ld: .byte 40,40,41,40,42,42,42,42,43,43,43,43,43,43,43,43
teq \irqnr, #2 teq \irqnr, #2
bne 44f bne 44f
43: mov \irqstat, #0x0C 43: mov \irqstat, #0x0C
strb \irqstat, [r4, #0x80] @outb(0x0C, 0xA0) /* Poll command */ strb \irqstat, [r4, #0xa0] @outb(0x0C, 0xA0) /* Poll command */
ldrb \irqnr, [r4, #0x80] @irq = (inb(0xA0) & 7) + 8 ldrb \irqnr, [r4, #0xa0] @irq = (inb(0xA0) & 7) + 8
and \irqstat, \irqnr, #0x80 and \irqstat, \irqnr, #0x80
teq \irqstat, #0 teq \irqstat, #0
beq 44f beq 44f
...@@ -655,7 +654,7 @@ __und_invalid: sub sp, sp, #S_FRAME_SIZE ...@@ -655,7 +654,7 @@ __und_invalid: sub sp, sp, #S_FRAME_SIZE
and r2, r6, #31 @ int mode and r2, r6, #31 @ int mode
b bad_mode b bad_mode
#if defined CONFIG_FPE_NWFPE || defined CONFIG_FPE_FASTFPE #if 1 /* defined CONFIG_FPE_NWFPE || defined CONFIG_FPE_FASTFPE */
/* The FPE is always present */ /* The FPE is always present */
.equ fpe_not_present, fpundefinstr .equ fpe_not_present, fpundefinstr
#else #else
...@@ -766,6 +765,8 @@ preempt_return: ...@@ -766,6 +765,8 @@ preempt_return:
msr spsr, r0 msr spsr, r0
ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr ldmia sp, {r0 - pc}^ @ load r0 - pc, cpsr
.ltorg
#ifdef CONFIG_PREEMPT #ifdef CONFIG_PREEMPT
svc_preempt: teq r9, #0 @ was preempt count = 0 svc_preempt: teq r9, #0 @ was preempt count = 0
ldreq r6, .LCirq_stat ldreq r6, .LCirq_stat
...@@ -902,6 +903,8 @@ __irq_usr: sub sp, sp, #S_FRAME_SIZE ...@@ -902,6 +903,8 @@ __irq_usr: sub sp, sp, #S_FRAME_SIZE
mov why, #0 mov why, #0
b ret_to_user b ret_to_user
.ltorg
.align 5 .align 5
__und_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go __und_usr: sub sp, sp, #S_FRAME_SIZE @ Allocate frame size in one go
stmia sp, {r0 - r12} @ Save r0 - r12 stmia sp, {r0 - r12} @ Save r0 - r12
......
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