Commit a1369978 authored by Qipan Li's avatar Qipan Li Committed by Olof Johansson

ARM: dts: sirf: fix fifosize, clks, dma channels for UART

sirf uart and usp-based uart driver with full dma support has
hit 3.12, here we fix the fifosize, dma channels for some HW
prop.
Signed-off-by: default avatarQipan Li <Qipan.Li@csr.com>
Signed-off-by: default avatarBarry Song <Baohua.Song@csr.com>
Signed-off-by: default avatarOlof Johansson <olof@lixom.net>
parent 4dc3231f
...@@ -181,6 +181,8 @@ uart0: uart@b0050000 { ...@@ -181,6 +181,8 @@ uart0: uart@b0050000 {
interrupts = <17>; interrupts = <17>;
fifosize = <128>; fifosize = <128>;
clocks = <&clks 13>; clocks = <&clks 13>;
sirf,uart-dma-rx-channel = <21>;
sirf,uart-dma-tx-channel = <2>;
}; };
uart1: uart@b0060000 { uart1: uart@b0060000 {
...@@ -199,6 +201,8 @@ uart2: uart@b0070000 { ...@@ -199,6 +201,8 @@ uart2: uart@b0070000 {
interrupts = <19>; interrupts = <19>;
fifosize = <128>; fifosize = <128>;
clocks = <&clks 15>; clocks = <&clks 15>;
sirf,uart-dma-rx-channel = <6>;
sirf,uart-dma-tx-channel = <7>;
}; };
usp0: usp@b0080000 { usp0: usp@b0080000 {
...@@ -206,7 +210,10 @@ usp0: usp@b0080000 { ...@@ -206,7 +210,10 @@ usp0: usp@b0080000 {
compatible = "sirf,prima2-usp"; compatible = "sirf,prima2-usp";
reg = <0xb0080000 0x10000>; reg = <0xb0080000 0x10000>;
interrupts = <20>; interrupts = <20>;
fifosize = <128>;
clocks = <&clks 28>; clocks = <&clks 28>;
sirf,usp-dma-rx-channel = <17>;
sirf,usp-dma-tx-channel = <18>;
}; };
usp1: usp@b0090000 { usp1: usp@b0090000 {
...@@ -214,7 +221,10 @@ usp1: usp@b0090000 { ...@@ -214,7 +221,10 @@ usp1: usp@b0090000 {
compatible = "sirf,prima2-usp"; compatible = "sirf,prima2-usp";
reg = <0xb0090000 0x10000>; reg = <0xb0090000 0x10000>;
interrupts = <21>; interrupts = <21>;
fifosize = <128>;
clocks = <&clks 29>; clocks = <&clks 29>;
sirf,usp-dma-rx-channel = <14>;
sirf,usp-dma-tx-channel = <15>;
}; };
dmac0: dma-controller@b00b0000 { dmac0: dma-controller@b00b0000 {
......
...@@ -196,25 +196,32 @@ audio@b0040000 { ...@@ -196,25 +196,32 @@ audio@b0040000 {
uart0: uart@b0050000 { uart0: uart@b0050000 {
cell-index = <0>; cell-index = <0>;
compatible = "sirf,prima2-uart"; compatible = "sirf,prima2-uart";
reg = <0xb0050000 0x10000>; reg = <0xb0050000 0x1000>;
interrupts = <17>; interrupts = <17>;
fifosize = <128>;
clocks = <&clks 13>; clocks = <&clks 13>;
sirf,uart-dma-rx-channel = <21>;
sirf,uart-dma-tx-channel = <2>;
}; };
uart1: uart@b0060000 { uart1: uart@b0060000 {
cell-index = <1>; cell-index = <1>;
compatible = "sirf,prima2-uart"; compatible = "sirf,prima2-uart";
reg = <0xb0060000 0x10000>; reg = <0xb0060000 0x1000>;
interrupts = <18>; interrupts = <18>;
fifosize = <32>;
clocks = <&clks 14>; clocks = <&clks 14>;
}; };
uart2: uart@b0070000 { uart2: uart@b0070000 {
cell-index = <2>; cell-index = <2>;
compatible = "sirf,prima2-uart"; compatible = "sirf,prima2-uart";
reg = <0xb0070000 0x10000>; reg = <0xb0070000 0x1000>;
interrupts = <19>; interrupts = <19>;
fifosize = <128>;
clocks = <&clks 15>; clocks = <&clks 15>;
sirf,uart-dma-rx-channel = <6>;
sirf,uart-dma-tx-channel = <7>;
}; };
usp0: usp@b0080000 { usp0: usp@b0080000 {
...@@ -222,7 +229,10 @@ usp0: usp@b0080000 { ...@@ -222,7 +229,10 @@ usp0: usp@b0080000 {
compatible = "sirf,prima2-usp"; compatible = "sirf,prima2-usp";
reg = <0xb0080000 0x10000>; reg = <0xb0080000 0x10000>;
interrupts = <20>; interrupts = <20>;
fifosize = <128>;
clocks = <&clks 28>; clocks = <&clks 28>;
sirf,usp-dma-rx-channel = <17>;
sirf,usp-dma-tx-channel = <18>;
}; };
usp1: usp@b0090000 { usp1: usp@b0090000 {
...@@ -230,7 +240,10 @@ usp1: usp@b0090000 { ...@@ -230,7 +240,10 @@ usp1: usp@b0090000 {
compatible = "sirf,prima2-usp"; compatible = "sirf,prima2-usp";
reg = <0xb0090000 0x10000>; reg = <0xb0090000 0x10000>;
interrupts = <21>; interrupts = <21>;
fifosize = <128>;
clocks = <&clks 29>; clocks = <&clks 29>;
sirf,usp-dma-rx-channel = <14>;
sirf,usp-dma-tx-channel = <15>;
}; };
usp2: usp@b00a0000 { usp2: usp@b00a0000 {
...@@ -238,7 +251,10 @@ usp2: usp@b00a0000 { ...@@ -238,7 +251,10 @@ usp2: usp@b00a0000 {
compatible = "sirf,prima2-usp"; compatible = "sirf,prima2-usp";
reg = <0xb00a0000 0x10000>; reg = <0xb00a0000 0x10000>;
interrupts = <22>; interrupts = <22>;
fifosize = <128>;
clocks = <&clks 30>; clocks = <&clks 30>;
sirf,usp-dma-rx-channel = <10>;
sirf,usp-dma-tx-channel = <11>;
}; };
dmac0: dma-controller@b00b0000 { dmac0: dma-controller@b00b0000 {
......
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